JPS63276978A - Noise reduction circuit - Google Patents

Abstract

PURPOSE:To reduce noise of a video signal without using a memory of large capacity and without losing the precision by detecting a field difference or frame difference as to a signal of a high frequency component having a prescribed amplitude or below including noise. CONSTITUTION:An input signal S1 including noise is fed to an adder 3 via an LPF 12 and fed to an HPF 10. The output of the HPF 10 is fed to an adder 2 and an A/D converter 4 as a signal including noise via a limiter 11, the converted output becomes a signal retarded by one field via a field memory 5 and a D/A converter 6 and the result is fed to the adder 2. When the addition output is not zero, noise component is obtained, the difference signal is multiplied by a multiple of K at a multiplier 8 and fed to the adder 3. As a result, the output signal whose noise is reduced is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a noise reduction circuit for video signals used in television receivers and the like.

[Summary of the invention]

The present invention detects a signal with a one field difference or one frame difference with respect to a signal obtained by passing a video signal through a bypass filter and a limiter, and passes the video signal through a low pass filter to detect a signal with a one field difference or one frame difference. By adding the signals obtained by the above-described method, a noise reduction circuit with a simple circuit configuration is provided without impairing the definition of the screen.

[Conventional technology]

As a noise reduction circuit used in conventional television receivers and the like, one using a field memory (or frame memo) as shown in FIGS. 11 and 12 is known.

Fig. 11 shows an open loop configuration, in which the input video signal SI containing noise supplied from the input terminal 1 is added to the adder 2.3, and is also added to the A/D converter 4 to convert it into a digital signal. After being converted, it is written into the field memory 5.

The digital signal read from this memory 5 is a D/A
The converter 6 converts it into an analog signal S11.

Therefore, this analog signal S is delayed by one field with respect to the signal S1.

This signal S11 is added to the adder 2, and the signal S+
is subtracted from. A signal S r S + + representing the difference between the signal S obtained from the adder 2 and the signal 3+1 is applied to the motion detection circuit 7 and the multiplier 8 . Signal S of the above difference
+ S + r is considered to be a noise component when there is no movement between one field in the input signal S1, so at this time, it is multiplied by a predetermined coefficient K in the multiplier 8 by the signal from the motion detection circuit 7. Then, in adder 3, it is subtracted from signal S. Therefore, an output signal S with reduced noise is provided from the adder 3 to the output terminal 9. is obtained.

When motion is detected by the motion detection circuit 7, the difference signal s+ 311 is assumed to include a motion component, and the multiplier 8 sets the signal to =O based on the signal from the motion detection circuit 7, and the adder 3 Prohibit motion components from being subtracted.

The motion detection circuit 7 detects the level of the difference signal SI Sll, and when it exceeds a predetermined level, it is determined that there is movement. The motion detection circuit 7 may compare the input signal and output signal of the field memory 5, as shown by the dotted line in the figure.

Fig. 12 shows a closed loop configuration in which a signal S obtained by delaying a part of the output signal S0 by one field in the memory 5 and a signal S1 are subtracted by an adder 2, and the difference signal SI is subtracted from the signal S1. The signal passed through the multiplier 8 is subtracted from the signal S1 by the adder 3. That is, the noise-reduced signal S obtained from the adder 3. By delaying the signal S1 by one field and feeding it back, the noise contained in the signal S1 is gradually removed.

Incidentally, as a noise reduction circuit using a frame memory, one disclosed in Japanese Patent Application Laid-Open No. 157429/1983 is known. In addition, an invention similar to the present invention was filed in Japanese Patent Application No. 62-6740.
It has been filed as No. 3.

[Problem that the invention seeks to solve]

The noise reduction circuit using field memory (or frame memory) described above requires a large capacity memory and a motion detection circuit in order to prevent loss of screen definition. The disadvantage was that it was large in scale.

[Means for solving problems]

In the present invention, means for detecting a signal with a one field difference or one frame difference with respect to the signal obtained by passing the video signal through a bypass filter and a limiter, and a means for detecting a signal with a one field difference or one frame difference and the video signal are passed through a low pass. and means for adding the signals obtained through the filter.

[Effect]

The above-mentioned bypass filter and limiter extract the high-frequency component signal containing noise with a predetermined amplitude or less, and the field difference or frame difference is detected for this signal, so there is no need to use particularly large-capacity memory, and the definition is lost. Noise reduction can be performed without any noise. Furthermore, since the motion component is in the low frequency range, it is not included in the signal of the high frequency component below the predetermined amplitude. Therefore, the signal of the one field difference or l frame difference can be regarded as a noise component. In combination with a low-pass filter, the motion detection circuit can be omitted.

〔Example〕

FIG. 1 shows a first embodiment of the present invention, and parts corresponding to those in FIG. 11 are denoted by the same reference numerals, and their explanation will be omitted.

1 and 2, the input signal SI on which the noise N added to the input terminal 1 is superimposed is filtered through the low-pass filter 1.
2 and the bypass filter 10. The above low-pass filter 12 and bypass filter 10
A device with approximately the same cutoff frequency is used.

A low-pass signal SL from which high-frequency components including noise have been removed is obtained from the low-pass filter 12, and this signal SL is added to the adder 3. Further, the high frequency signal S old obtained from the bypass filter 10 is applied to the limiter 11. This limiter 11 has input/output characteristics as shown in FIG. 3, and an output signal is obtained when the input signal is between ■ and ■2,
The input signal is V, ,V.

The output is made constant at levels exceeding . Therefore, from this limiter 11, the high frequency signal 5l11
A signal between 71 and 72, ie, a signal S)+2 containing a noise component is obtained. This signal SOZ is sent to adder 2
is added to the signal SH2+, and is delayed by one field by the A/D converter 4, field memory 5, and D/A converter 6 to become the signal SH2+, which is subtracted from the signal SOZ by the adder 2.

Here, since screen movement generally has a low frequency, the above-mentioned high frequency signal SHz, 5) I2+ contains almost no movement component. Therefore, the difference signal S 82 obtained from adder 2
If S, 121 is not zero, there is virtually no problem in considering it as a noise component.

That is, in this embodiment, there is no need to provide the motion detection circuit 7 shown in FIGS. 11 and 12, and this circuit is omitted.

The difference signal S 82 3821 is multiplied by the multiplier 8 and then added to the low frequency signal S1 by the adder 3, thereby providing the output signal S with reduced noise at the output terminal 9. is obtained.

In addition, in this embodiment, since noise detection is performed using the memory 5 for the narrow amplitude signal SH□ that has passed through the limiter 11, the memory 5 is used for the entire band of the input signal S1 as shown in FIG. The capacity of the memory 5 can be made smaller than when noise detection is performed. Experiments have confirmed that the number of bits of the signal processed by the A/D converter 4, memory 5, and D/A converter 6 can be reduced from the conventional 8 bits to about 6 bits.

FIG. 4 shows a second embodiment of the present invention, and parts corresponding to those in FIG. 1 are given the same reference numerals and their explanations will be omitted.

The first embodiment shown in FIG. 1 described above is a case in which an open loop is constructed, but this embodiment shows a case in which a closed loop is constructed.

In FIG. 4, the signals S and lI are applied to an adder 14, and the signal SHI from which the signal SHz has passed through the adder 13 is applied to an A/D converter 4, a field memory 5 and a D/A converter 6. As a result, the signal SH! is delayed by one field and becomes the signal 5H2l. 1 is subtracted from signal SH2 in adder 2.

The difference signal S□23Nz+ obtained from the adder 2 is added to the adder 13 via the multiplier 8 and subtracted from the signal SH□ to obtain the signal Sil+, and this signal 5i11 is fed back through the memory 5. That's what I do. Further, the difference signal SHtSM□8 from the multiplier 8 is subtracted from the signal SHI by the adder 14, and this subtracted output signal is added to the adder 3.

In the circuit shown in FIG. 4, the bypass filter 10 is provided before the limiter 11, but the input signal S1 may be passed through the bypass filter 10 after the amplitude is limited by the limiter 11. FIG. 5 shows a third embodiment of the present invention showing the circuit configuration in that case, and the same parts as those in FIG. 4 are given the same reference numerals and their explanation will be omitted.

In FIG. 5, the human input signal S1 passes through a capacitor 17, a limiter 11, and a bypass filter 10, thereby producing a signal 5) 12 that is substantially equivalent to the signal SH□ in FIG.
becomes. Further, the signal that has passed through the limiter 11, that is, the low-level signal SN including noise, is subtracted from the signal S2 in the adder 15, and the subtraction output is sent to the bypass filter 1.
Signal S leading to 6. get. This signal S,+ is substantially equivalent to the signal 5)12 described above.

Therefore, by adding the signal SH, the signal SL obtained from the low-pass filter 12, and the signal obtained from the adder 13 in the adder 3, a signal S with reduced noise is delivered to the output terminal 9. can be obtained.

In this embodiment, the limiter 11 is provided before the bypass filter 10.16. Therefore, if there is no capacitor 17, the input signal SI will be V, ,
If the level of the signal Sl is limited by the level of V, and if the level of the signal Sl exceeds the limited range of V, , V2, it becomes impossible to remove the noise existing in the area beyond the limit.

For this reason, in this embodiment, by providing the capacitor 17 and supplying the signal Sl as an alternating current bone to the limiter 11, V,
, V, is provided. In this case, in this embodiment, ■1 of the limiter 11 in FIG.
~V2 limit range 25% (however, white peak level 10%)
(when set to 0). That is, in FIG. 3, the input level is O (input signal S1 passed through capacitor 17).
The limit range is ±12.5% centered on the average level of

Note that the limiter 11 in each embodiment is not limited to the characteristics shown in FIG. 3, and may have the characteristics shown in FIG. 6 or 7. Further, in each embodiment, the field memory 5 is used, but it goes without saying that a frame memory may also be used.

In addition, in FIG. 1, the bypass filter 10 is replaced by the multiplier 8.
and the adder 3.

Next, the bypass filter 10 (16) will be described.

When the bypass filter 10 has a simple configuration consisting of a resistor and a capacitor, when there is a lot of noise, for example when the input electric field strength is small and the S/N is poor, a phenomenon in which the noise moves in the lateral direction may be observed. be. In order to improve this, the above noise phenomenon can be suppressed by giving the filter a group delay characteristic and making the delay time equal regardless of the frequency. An example of the bypass filter 10 in this case is shown in FIG.

In FIG. 8, a capacitor CI and a resistor RI are connected in parallel, and a series circuit of a resistor R2 and a capacitor C2 is connected in parallel to a capacitor C1.

Moreover, as shown in FIG. 9, bypass filter IO,,1
Two types of 02 may be provided and switched by the switch 18. That is, the capacitor CI+ and the resistor R0 form a bypass filter 10. with a cutoff frequency of 500kHz. and a capacitor C+z and a resistor R
, t, the cutoff frequency is 15.75 kll
Bypass filter 10z of z is configured such that these bypass filters IO8, 102 are selected by switch 17.

Then, when there is little noise, the cutoff frequency is set to a high frequency of 5, focusing on not erasing the motion component.
00kHz, and if there is a lot of noise, focus on noise removal, even if it comes at the cost of erasing the motion component.
It looks better to lower the cutoff frequency to about 15.75 kHz and remove noise. The switching may be performed manually by providing a switch 18 as shown in the figure, or the switch 18 may be automatically switched in response to a signal reflecting the input electric field strength, such as the AGC control voltage level of the tuner. good.

Alternatively, the bypass filter 10 may be constructed of a capacitor C1 and a variable resistor R3, as shown in FIG. 10, to continuously change the cutoff frequency.

This variable resistor R3 may be controlled manually, or the AG
Depending on the C voltage, the cutoff frequency was changed from 500kHz to 15.
It may be automatically controlled between 75 kllz.

Furthermore, the cutoff frequency of the low-pass filter 12 may be changed depending on the noise. In addition to using the AGC voltage described above, the input electric field strength may be detected by detecting the noise level in the synchronization signal, for example.

〔Effect of the invention〕

According to the present invention, the motion detection circuit used in the conventional noise reduction circuit can be omitted, and
Screen definition does not deteriorate. Furthermore, there is no need to use a particularly large-capacity field memory or frame memory, and furthermore, a motion detection circuit can be omitted.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a signal waveform diagram of each part in FIG. 1, FIG. 3 is a characteristic diagram of the limiter in FIG. 1, and FIG. FIG. 5 is a block diagram showing the third embodiment of the present invention, FIGS. 6 and 7 are other characteristic diagrams of the limiter, and FIGS. 8 to 10 are examples of the bypass filter. 11 and 12 are block diagrams of conventional noise reduction circuits. In addition, in the symbols used in the drawings, 3-・----1・−・−・−・Adder 5・−・−・−
1---------Field memory 10-・-1-
−−−−−Bypass filter 11−・−・−・−・・
-Limiter 12--------This is a low pass filter.

Claims (1)

[Claims] A signal with a one field difference or one frame difference is detected with respect to the signal obtained by passing the video signal through a bypass filter and a limiter, and the signal with the one field difference or one frame difference and the video signal are passed through a low-pass filter. A noise reduction circuit characterized in that the noise reduction circuit adds the signals obtained through the noise reduction circuit.