JPS63276188A - Coin discriminator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] (Industrial Application Field) This invention is applicable to V! ! The present invention relates to a negative sorting device, and particularly relates to an improvement of an electronic coin sorting device that electronically discriminates the type of coin.

(Prior art) Conventionally, coin sorting devices have been divided into two types: a mechanical coin sorting device that mechanically checks the properties of the coins and sorts the coins, and an electronic coin sorting device that checks the properties of the coins and sorts the coins.
There is an electronic coin sorting device that detects negative characteristics and sorts coins based on the detection output.Electronic coin sorting devices are popular because they have good sorting accuracy and can be made smaller. The scope of use has been expanded.

The general structure of an electronic coin sorting device is to arrange a transmitter coil excited by a signal of a predetermined frequency on one side of the coin passage, and a transmitter coil that is electromagnetically coupled to the transmitter coil on the other side. A receiving coil is provided, and the authenticity and type of the coin are determined based on the attenuated voltage waveform from the receiving coil generated when the coin passes, and the coin is discriminated based on the results of this determination. That is, focusing on the fact that the maximum attenuation voltage of the attenuation voltage waveform generated from the receiving coil when a coin passes varies depending on each coin A, B, C, and D as shown in FIG. 15, the determination range of this maximum attenuation voltage is determined. (window) is predetermined for each sorted coin (see Figure 16), and the coin's authenticity and type are determined based on whether the depletion voltage waveform generated from the receiving coil falls within the determination range. .

However, according to the above configuration, when a coin has a large amount of attenuation in the attenuation voltage waveform generated from the receiving coil, the attenuation voltage waveform crosses the tolerance range of other coins, so a genuine coin determination signal is generated each time. Put it away.

In other words, in the case of large recruitment of attenuation ω of the attenuation voltage waveform, 1
A plurality of genuine coin determination signals are generated for each coin inserted. Therefore, in the past, a maximum attenuation point detection circuit was provided to detect when the attenuation voltage waveform generated from the receiving coil reached the maximum attenuation point, and reception was received in synchronization with the peak signal (see Figure 17) from this maximum attenuation point detection circuit. I am trying to judge the output of the coil.

(Problems with the prior art) However, the maximum attenuation point detection circuit here consists of a circuit that sequentially stores the output of the receiving coil, a circuit that detects when the output of the receiving coil reverses from attenuation and starts rising, etc. This maximum attenuation point detection circuit makes the overall circuit configuration extremely complicated.

In addition, the peak signal output from the maximum attenuation point detection circuit is a discontinuous signal that occurs only when the output of the receiving coil is at maximum attenuation.
Therefore, if noise equivalent to this peak signal occurs outside the maximum attenuation voltage of the output of the receiving coil, there is a problem that malfunction will occur due to this noise. Therefore,
SUMMARY OF THE INVENTION An object of the present invention is to provide a coin sorting device with a simple structure and less malfunction.

(Means for Solving the Problems) In order to achieve the above object, the coin sorting device of the present invention is arranged in a coin passage, and coins with different waveforms corresponding to the types of coins that sequentially change as the coins pass through. A coin detection coil that outputs a detection signal and each detection Wf! a timer means for setting a plurality of different windows each corresponding to a negative value, monitoring the time during which the coin detection signal is within the window, and detecting the time when the time exceeds a predetermined value; The present invention is characterized by comprising: a counting means for counting the number of times the coin has entered the window; and a determining means for determining the authenticity and type of the coin based on the detection output of the timer means and the count value of the counting means.

(Operation) According to the present invention, the authenticity and type of coin are determined based on the output of the timer means and the output of the counting means. For example, if the detected coin is a genuine coin, the output of the receiving coil will gradually decrease as the coin passes, and after reaching a tolerance window set in advance corresponding to the detected coin, will rise and return to its original value. Return to level.

Here, the pulse width of the pulse signal output from the window means differs depending on whether the output of the receiving coil reaches the above-mentioned allowable range or when it simply crosses another window. Therefore, in the present invention, the pulse width of the pulse signal is monitored by a timer means.

Furthermore, if the output of the receiving coil crosses n windows before reaching the above tolerance range, n signals are generated from the window means until reaching this tolerance range, and one signal is generated when the output reaches this tolerance range. A signal is generated, and by the time it returns to any level from this tolerance range, n signals are generated, with a total of n+
One signal is generated. Here, the value 2n+1 differs depending on the type of coin to be detected. On the other hand, if the coin to be detected is a counterfeit coin, the output of the receiving coil does not reach any window or just crosses the window as the coin passes, so the light value of the counting means in this case is 2 m (m is O or an integer). Therefore, in the present invention, the authenticity of the coin to be detected and the type of the coin to be detected are determined based on both the visual output of the timer means and the count value of the counting means.

(Embodiment) FIG. 1 shows an embodiment of Komei's coin sorting device. In FIG. 1, an optical signal coil excited by the output of an optical oscillator 3 is disposed on one side of a coin passage 1. Here, the oscillation wave number of the oscillator 3 varies depending on the properties of interest (material, shape, etc.) of the detected coin 2; for example, 500 MHz is used when the material is the focus, and 2KMH2 is used when the shape is the focus. A receiving coil 5 is disposed on the other side of the coin passage 1, facing the transmitting coil 4. In this embodiment, the authenticity and type of the coin 2 are determined based on the output signal of the receiving coil 5, that is, the attenuated voltage waveform, which is generated when the coin 2 passes through the arrangement portion of the transmitting coil 4 and the receiving coil 5 in the coin passage 1. be done. The output signal of the receiving coil 5 is subjected to a detection image width in a detection amplifier circuit 6 and is applied to a window circuit 7.8.9.10. The window circuit 7.8.9.10 has a maximum attenuation voltage tolerance range corresponding to the A coin, B coin, C coin, and D coin, that is, a window, set in the window circuit 7.8.9.10. rises when the output of the detection amplifier circuit 6 enters the window, respectively,
Each escape from the window generates a rising pulse. Such window circuits 7, 8, 9; 10 can be formed by well-known window comparators. The outputs of window circuits 7.8.9.10 are sent to timers 11.12.13.
14 respectively.

Timers 11, 12, 13, and 14 start timing operation when the input pulse signal rises, and the pulse signal does not fall even after the respective set timer times T1, T2, ■3, and ■4 elapse. It outputs a high level signal. Here, as the coin 2 passes through the optical signal coil 4 and receiving coil 5 arrangement section, when a high level signal is output from the timer 11, it is determined that it is an A coin, and a high level signal is output from the timer 12. When it is output, it is determined to be a B coin, when a high level signal is output from the timer 13, it is determined to be a Ct coin, and when a high level signal is output from the timer 14, it is determined to be a D hard L1 coin. Also timer 11
．． If a high-level signal is not output from any of 12, 13, and 14, in this case, coin 2 is determined to be a counterfeit coin.

Figures 2 to 5 are regular 15A coins, B coins, and C coins, respectively.
This figure shows the attenuated voltage waveform output from the detection amplifier circuit 6 and the output pulse of the window circuit 7.8.9.10 as the coin, the D coin, passes through the transmitting coil 4 and receiving coil 5 arrangement section. be.

In addition, in FIGS. 2 to 5, windows A, B, and C1D indicate the allowable ranges (genie determination ranges) of the maximum attenuation voltage for AV& coins, B coins, C coins, and D coins, respectively.

Also, Fig. 2 (b) (c) (d) (e), Fig. 3 (b) (
c) (d) (e), Figure 4 (b) (c) (d) (e),
FIGS. 5(b), (c), (d), and (e) show the window circuit 7.
8.9.10 output pulses are shown.

First, in the case of A coin, the output of the detection amplifier circuit 6 attenuates to the window as shown in FIG. 2, and then rises and returns to the original level. That is, in this case, windows B and C have attenuated voltage waveforms corresponding to other coins.

Since it does not cross D at all, only one pulse is output from the window circuit 7. In this case, the pulse width of the output pulse of the determination circuit 7 is larger than the set pulse width T1 of the timer 11, so only the timer 11 outputs a high level signal.

In the case of the B coin, the attenuated voltage waveform attenuates to window B, as shown in FIG. 3, and then rises and returns to the original level. Here, the attenuated voltage waveform crosses one window A when the capital decreases and when the capital increases. In this case, the pulse width of the output pulse of the window circuit 7 is the set pulse width T of the timer 11.
Since it is smaller than 1, the timer 11 does not generate a high level signal.

However, since the pulse width of the pulse signal output from the window circuit 8 is larger than the set pulse width (2) of the timer 12, the timer 12 generates a high level signal.

Eventually, only the timer 12 generates a high level signal.

In the case of a C coin, the attenuated voltage waveform attenuates to window C, as shown in FIG. 4, and then increases and returns to the original level. Here, the decay voltage waveform crosses windows A and B when it decays, and crosses windows A and B again when it rises. And in this case window circuit 7
．． The pulse width of each output pulse of 8 is determined by timer 11.1.
Timer 1 is smaller than the set pulse width T1 and T2 of
From 1.12 onwards, high-level @ signs will not occur. However, since the pulse width of the pulse signal output from the window circuit 9 is larger than the set pulse width T3 of the timer 13, a high level signal is generated from the timer 13.

Further, in the case of a D coin, as shown in FIG. 5, the attenuated voltage waveform attenuates to the window and then returns to the original level. Here, the attenuated voltage waveform crosses windows A and 81G when attenuating, and crosses A and 81C again when rising. In this case, since the pulse width of the output pulse of the window circuit 7.8.9 is smaller than the set pulse widths T1, T2, and T3 of the timer 11.12.13, the high level signal is output from the timer 11.12.13. No signal is generated. However, the pulse width of the pulse signal output from the window circuit 10 is the set pulse width T4 of the timer 14.
Since it is larger, the timer 14 generates a high level signal.

In this way, if the coin passing through the coin path 1 is an A coin, a high level signal is generated only from the timer 11, and the Bt
In the case of a coin, a high level signal is generated only from the timer 12, in the case of a C coin, a high level signal is generated only from the timer 13, and in the case of a D coin, a high level signal is generated only from the timer 14.

FIG. 6 shows an example in which the coin 2 passing through the coin passage 1 is a counterfeit coin. Coin 2 passing through coin passage 1
If it is a counterfeit coin, the maximum attenuation voltage of the attenuation voltage waveform does not belong to any of windows A, B, C, and D. For example, as shown in FIG. 6, the attenuated voltage waveform crosses windows A and B and returns to its original level. In this case, the determination circuit 7
．． The pulse widths of the pulse signals output from the timers 8 and 8 are each smaller than the set pulse widths T1 and T2 of the timers 11.12, and as a result, no high level signals are generated from the timers 11.12.

In this way, if the coin passing through the coin path 1 is a counterfeit coin, no high level signal is generated from any of the timers 11, 12, 13, and 14.

The outputs of timers 11, 12, 13, and 14 are respectively connected to AND circuits AN1. AN2. ΔN3. Added to AN4.

Further, the outputs of the window circuits 7, 8, 9, and 10 are applied to the counter 15 via the OR circuit OR1. The counting value of the counter 15 is reset by an appropriate means before a coin enters the optical transmitting coil 4 and the receiving coil 5. Judgment circuits 7, 8, 9.1
Count the number of pulses generated from 0.

Figures 7 to 10 are specie Al1 negative, B coin,
The diagram shows the attenuated voltage waveform output from the detection amplifier circuit 6 and the output pulse of the window circuit 7.8.9.10 as the C coin and D coin pass through the transmitting coil 4 and receiving coil 5 arrangement section. It is.

In addition, windows A and 81C in FIGS. 7 to 10.

D indicates the allowable range of the maximum attenuation voltage (regular coin τ11 constant range) for A coin, B coin, C coin, and D coin, respectively.

Also, Fig. 7(b)(c)(d)(e), Fig. 8(b)(
c) (d) (e), Figure 9 (b) (c) (d>(e),
10(b),(c),(d)(e) are window circuits 7, respectively.
．． 8.9.10 output pulses are shown.

First, in the case of A coin, as shown in FIG. 7, the output of the detection amplifier circuit 6 decreases to window A, and then rises and returns to the original level. That is, in this case, since the attenuated voltage waveform does not cross the windows B and C1D corresponding to the other hard disks 15 at all, only one pulse is output from the window circuit 7. Therefore, the count value of the counter 15 in this case is "1".

In the case of the B coin, the attenuated voltage waveform attenuates to window B, as shown in FIG. 8, and then rises and returns to the original level. Here, the decay voltage waveform crosses gA once during decay and once during rise. Therefore, in this case, from window circuit 7 to 2
One pulse is output from the window circuit 8, and the count value of the counter 15 becomes "3".

In the case of a C coin, the attenuated voltage waveform attenuates to window C, as shown in FIG. 9, and then rises and returns to the original level. Here, the decay voltage waveform crosses windows A and B when it decays, and crosses windows A and B again when it rises. Therefore, in this case, two pulses are output from each of the window circuits 7 and 8, and one pulse is output from the window circuit 9, and the count value of the counter 15 becomes "5".

Further, in the case of a D coin, as shown in FIG. 10, the attenuation voltage waveform attenuates to the window and then returns to the original level.

Here, the attenuated voltage waveform crosses windows A, B, and C at the time of attenuation,
As you ascend, you will cross A and 81C again. Therefore, in this case, 2 it pulses each from the window circuit 7.8.9,
One light pulse is output from the window circuit 10, and the count value of the counter 15 becomes "7".

In this way, V! passes through the coin passage 1! ! If the coin is an A coin, the count value of the counter 15 will be "1", and if it is a B coin, the count value of the counter 15 will be "3", and C&J
! In the case of currency, the count value of the counter 15 is "5", and D
In the case of coins, the counting position of the counter 15 is "7". All of the counted values are odd numbers.

FIG. 11 shows an example in which the coins passing through the coin passage 1 are counterfeit coins. Coin 2 passing through coin passage 1
If it is a counterfeit coin, the maximum attenuation voltage of its attenuation voltage waveform does not belong to any of windows A, B, and C1D. For example, as shown in FIG. 11, the attenuated voltage waveform is
Cross it to return to the original level. In this case, window circuit 7
．． Two pulses are output from each pulse 8, and the count value of the counter 15 becomes "4".

In this way, vf! passes through the coin passage 1! If the coin is a counterfeit coin, the count value of the counter 15 will be an even number.

The output of counter 15 is applied to decoder 16. The decoder 16 outputs a signal indicating the detection of the A coin when the count value of the counter 15 is "1", outputs a signal indicating the detection of the B coin when it is "3", and outputs a signal indicating the detection of the B coin when the count value is "5". A signal indicating the detection of a coin is output, and when it is "7", a signal indicating the detection of a D coin is output. Further, the decoder 16 has a counter 15
If the count value of is an even number, input fjf! Outputs a counterfeit currency signal indicating that the currency is counterfeit.

A signal indicating the detection of the A coin output from the decoder 16,
Signal indicating detection of B coin, signal indicating detection of C coin, D
Signals indicating coin detection are sent to AND circuits AN1.
AN2. AN3. Added to other inputs of AN4.

Therefore, from the AND circuit AN1, the timer 11 determines that the coin is A, and the counter 15,
Only when the decoder 16 determines that the A coin is the A coin, an A coin signal indicating detection of the A coin is output. Further, the AND circuit AN2 outputs a B coin signal indicating detection of a B coin only when the timer 12 determines that the coin is BtlJ, and the parentheses counter 15 and decoder 16 determine that the coin is 8 coins. Further, the AND circuit AN3 outputs a C coin signal indicating detection of a C coin only when the timer 13 determines that the coin is a C coin, and the counter 15 and decoder 16 determine that the coin is a C coin. Also, AND circuit AN4
, a D coin signal indicating detection of a D coin is output only when the timer 14 determines that the coin is a D coin, and the counter 15 and the decoder 16 determine that the coin is a D coin.

In this way, the A coin signal, the B coin signal, the C coin signal output from the AND circuits AN1 to AN4, and the fake t5 signal output from the decoder 16 are applied to a coin sorting section (not shown), and are used to sort out positive and negative fake coins. Used for sorting denominations.

Note that in the embodiment shown in FIG.
The setting times of 2, 13 and 14 are respectively T1. T2, T
3 and T4 are set separately, but they may be set to the same value.

Further, in the embodiment shown in FIG. 1, the counterfeit currency signal is obtained from the even output of the decoder 16, but an AND circuit (not shown) is provided to take the AND condition of the inverted outputs of each of the timer circuits 11 to 14. The counterfeit currency signal may be generated from the output of this AND circuit, or the counterfeit currency signal may be obtained from the AND condition of the even output of the AND circuit and the decoder 16.

, FIG. 12 shows another embodiment of the invention.

In this embodiment, a transmitting coil 4 excited by an oscillator 3 is disposed on one side of the coin passage 1, and an oscillating coil 4'
On the other side of the coin path 1, a receiving coil 5 is arranged opposite to the transmitting coil 4, and further, a receiving coil 5' is arranged opposite to the transmitting coil 4'.
to be placed.

The output of the receiving coil 5 is sent via the detection amplifier circuit 6 to the window circuits 7, 8, 9, and 10, and the output of the receiving coil 5' is sent via the detection amplifier circuit 6 to the window circuit 7'.

Add to 8', 9', 10'. That is, in this embodiment, two pairs of transmitting coils and receiving coils are provided along the coin path 1, and separate window circuits 7 to 10 and window circuits 7' to 7' are provided for each pair of transmitting coils and receiving coils. 10' is provided. Here, the transmitting coils 4 and 4' are excited at different frequencies, and the window circuits 7 to 10 and the window circuits 7' to 10' are each provided with a separate window corresponding to each frequency. In this example, the window circuit 7.8
Based on the output of ゜9.10, timers 11, 12゜13.
14, the A coin, B coin, C coin, and D coin are determined, and the window circuit 7/87.9F.

Counter 15 and decoder 1 that count the output of 10'
A coin, a B coin, a C coin, and a D coin are determined by the AND circuit AN1. AN
2. AN3. A coin signal, B coin signal, C coin signal, and D coin signal are obtained from AN4, respectively. The basic operation of the embodiment shown in FIG. 12 is the same except that transmitter coils 4, 4' excited at different frequencies are used.

FIGS. 13 and 14 show another embodiment in which a part of the circuit is constructed using a central processing unit (CPU). The embodiment shown in FIGS. 13 and 14 functions functionally similar to that shown in FIG.

That is, the embodiment shown in FIG. 13 is constructed by replacing the timers 11 to 14, the OR circuit OR1, the counter 15, the decoder 16, and the AND circuits AN1 to AN4 in the embodiment shown in FIG. be done.

Furthermore, the embodiment shown in FIG. 14 has a configuration in which the output of the detection and amplification circuit 6 is converted into a digital signal by an analog-to-digital converter 18, and the signal is sent to the CPU 17. 14, OR circuit OR1
, counter 15, deco radar 16, AND circuit ANI~
In addition to AN4, the functions of window circuits 7 to 10 are also performed by CPU1.
I have it on 7.

In addition, in the above embodiments, the coins to be sorted are A coin,
B coin, C'g! The number of denominations is arbitrary.

(Effects of the Invention) As described above, according to the present invention, a coin sorting device with fewer malfunctions can be provided, and the configuration can be significantly simplified by eliminating the need for a peak signal at all.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 to 11 are waveform diagrams explaining the operation of the embodiment shown in FIG. 1, and FIGS. 12, 13, and 14. 15 is a block diagram showing another embodiment of the present invention, and FIGS. 15 to 17 are waveform diagrams for explaining the operation of the conventional device. 1... Coin passage, 2... Coin, 3... Oscillator, 4
... Transmitting coil, 5... Receiving coil, 6... Detection amplifier circuit, 7.8.9.10... Window circuit, 11.12
．． 13.14...Timer circuit, 15...Counter,
16...Decoder, 17...CPU, 18...A
/D converter. Fig. 1 22 --: Nini ni ni ni 2 = 1 = 2 = 2, 2 T knee': [-D Fig. 2 Fig. 3 Fig. 4 Fig. 5 Fig. 6 Fig. 7 Fig. 8 Fig. 9 Figure 10 Figure 11 Figure 13 Figure 14 ＼DgII Boiled Figure 15 Figure 16 Figure 17

Claims (3)

[Claims] (1) A coin detection coil that is disposed in the coin passage and outputs a coin detection signal with a different waveform depending on the type of coin that changes sequentially as the coin passes, and a plurality of different windows that correspond to each detected coin. is set, and the timer means monitors the time during which the coin detection signal remains within the window, and detects when the time exceeds a predetermined value; and the counter means counts the number of times the coin detection signal enters the window. A coin sorting device comprising: a determining means for determining authenticity and type of a coin based on the detection output of the timer means and the count value of the counting means. (2) first and second coin detection coils that are arranged along the coin path and output coin detection signals with different waveforms corresponding to the type of coin that sequentially change as the coin passes; A plurality of different first windows corresponding to coins are set, and the time during which the first coin detection signal is within any of the first windows is monitored, and when the time exceeds a predetermined value, A timer means for detecting this, and a plurality of different second windows corresponding to each detected coin are set, and when the second coin detection signal enters any of the second windows, it is detected. A coin sorting device comprising: a counting means for counting the number of times the coin has entered; and a determining means for determining the authenticity and type of the coin based on the detection output of the timer means and the count value of the counting means. (3) The coin sorting device according to claim (2), wherein the first and second coin detection coils are excited by excitation signals of different frequencies.