JPS63272116A - Band limiting circuit - Google Patents

Band limiting circuit

Info

Publication number
JPS63272116A
JPS63272116A JP10463387A JP10463387A JPS63272116A JP S63272116 A JPS63272116 A JP S63272116A JP 10463387 A JP10463387 A JP 10463387A JP 10463387 A JP10463387 A JP 10463387A JP S63272116 A JPS63272116 A JP S63272116A
Authority
JP
Japan
Prior art keywords
band
cyclic filter
filter part
filter
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10463387A
Other languages
Japanese (ja)
Inventor
Yukio Suzuki
幸夫 鈴木
Haruhiro Shiino
椎野 玄博
Yasuo Shoji
庄司 保夫
Hiromi Ando
安藤 博美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP10463387A priority Critical patent/JPS63272116A/en
Priority to EP88303795A priority patent/EP0289285A3/en
Priority to US07/186,576 priority patent/US4961160A/en
Priority to CA000565457A priority patent/CA1311844C/en
Publication of JPS63272116A publication Critical patent/JPS63272116A/en
Pending legal-status Critical Current

Links

Landscapes

  • Processing Of Color Television Signals (AREA)
  • Picture Signal Circuits (AREA)

Abstract

PURPOSE:To widely decrease the number of delay elements and arithmetic steps obtained by multiplying and adding, to miniaturize a circuit and to expand the function of a system as a whole, by making a filter part into a cyclic filter. CONSTITUTION:A sixth cyclic filter part 22 has 11 delaying elements together with an input delaying element 23 and an output delaying element 24, and a signal is band-limited by 15 times of multiplying and adding. A signal band- limited by a sixth cyclic filter part 23 is inputted from the output delaying element 24 of the sixth cyclic filter part 22 through a decimeter part 2 to sample down a signal to 16:1 and a 10th cyclic filter part 26. The 10th cyclic filter part 26 has 16 delaying elements together with an output delaying element 27 of the 10th cyclic filter part 26 and the signal is band-limited by 25 times of multiplying and adding. Thus, the signal band-limited by the 10th cyclic filter part 26 is outputted from the output delaying element 27 of the 10th cyclic filter part 26 through an output terminal 28.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は線形予測分析用の帯域制限回路に関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a band limiting circuit for linear predictive analysis.

(従来の技術) 従来、この種の帯域制限回路は、例えば音声信号の特徴
量の1つとなる線形予測係数の折り返し誤差を少なくす
る手法として、通過帯域内に於ける遅延が一定となる様
に周波数帯域を制限するために使用される。第2図は従
来の帯域制限回路を示すブロック図である。従来の帯域
制限回路は信号の周波数帯域制限をするフィルタ部11
゜12、・・・IM、並びに各フィルタ部間で信号のサ
ンプリングレートを落すデシメータ部21゜22、−2
Nより成る(但し、N=M−1)。ところで従来の帯域
制限回路ではフィルタ部11゜12、・−I Mは対象
非巡回型で構成されていた。
(Prior Art) Conventionally, this type of band-limiting circuit has been designed to reduce the aliasing error of linear prediction coefficients, which is one of the features of an audio signal, so that the delay within the passband is constant. Used to limit frequency bands. FIG. 2 is a block diagram showing a conventional band limiting circuit. A conventional band limiting circuit includes a filter section 11 that limits the frequency band of a signal.
゜12, ... IM and a decimator section 21゜22, -2 that reduces the sampling rate of the signal between each filter section
It consists of N (however, N=M-1). By the way, in the conventional band-limiting circuit, the filter sections 11, 12, . . . -IM are constructed of a symmetric acyclic type.

(発明が解決しようとする問題点) しかしながら、前記構成の帯域制限回路では、フィルタ
部に非巡回型フィルタを用いるので、非巡回型フィルタ
の性質上、目的とする周波数特性を得るためにはフィル
タ次数を犬きくとる必要があり、遅延素子数の増大、並
びに演算ステップ数の増大と云う問題点があった。この
様な問題点はハードウェア量の増大、所定の演算ステッ
プ中での占有率の増大から帯域制限回路を組み込んだシ
ステム全体の機能を制限してしまう原因となる。
(Problem to be Solved by the Invention) However, in the band-limiting circuit having the above configuration, since an acyclic filter is used in the filter section, due to the nature of the acyclic filter, it is necessary to filter the filter in order to obtain the desired frequency characteristics. It is necessary to increase the order, and there are problems of an increase in the number of delay elements and an increase in the number of calculation steps. Such problems cause an increase in the amount of hardware and an increase in the occupation rate during a predetermined calculation step, which limits the functions of the entire system incorporating the band limiting circuit.

本発明は上述した問題点を解決し、周波数帯域制限の能
力は従来と同等以上であって、遅延素子数及び演算ステ
ップ数の少ない線形予測分析用の帯域制限回路を提供す
る事を目的とする。
The present invention solves the above-mentioned problems, and aims to provide a band limiting circuit for linear predictive analysis, which has frequency band limiting capability equal to or higher than that of the conventional one, and which has a small number of delay elements and a small number of calculation steps. .

(問題点を解決するための手段) 本発明は館記問題点を解決するために、フィルタ部と、
サンプリングレートを落すデシメータ部とを交互に多段
接続させて成り、通過帯域内で遅延が一定となるように
周波数帯域を制限する線形予測用の帯域制限回路におい
て、前記フィルタ部が巡回型フィルタであるものである
(Means for Solving the Problems) In order to solve the problems in library records, the present invention includes a filter section,
In a band limiting circuit for linear prediction that limits a frequency band so that a delay is constant within a passband, the filter section is a recursive filter, and the filter section is a recursive filter. It is something.

(作用) 本発明によれば、以上のように帯域制限回路を構成した
ので、技術的手段は次のように作用する。フィルタ部を
構成する巡回型フィルタは従来の非巡回型フィルタの場
合に比べて、その性質上、目的とする帯域特性を得るの
に、遅延素子数及び乗加算による演算ステップ数が少な
くすむ。
(Operation) According to the present invention, since the band limiting circuit is configured as described above, the technical means operates as follows. Due to its nature, the recursive filter constituting the filter section requires fewer delay elements and fewer calculation steps for multiplication and addition than conventional non-recursive filters.

従って、前記従来技術の問題点を解決できるのである。Therefore, the problems of the prior art described above can be solved.

(実施例) 第1図は本発明の帯域制限回路の一実施例を示すプロ、
ツタ図である。同図において、21は入力端子、22は
6次巡回型フィルタ部、23は6次巡回型フィルタ部2
2の人力遅延素子、24は6次巡回型フィルタ22の出
力遅延素子、25は信号を16:1にダウンサンプリン
グするデシメータ部、26はlO次巡回型フィルタ部、
27は10次巡回型フィルタ24の出力遅延素子、28
は出力端子である。
(Embodiment) FIG.
It is an ivy diagram. In the figure, 21 is an input terminal, 22 is a 6th order recursive filter section, and 23 is a 6th order recursive filter section 2.
2 is a manual delay element of 2, 24 is an output delay element of the 6th order recursive filter 22, 25 is a decimator section that downsamples the signal to 16:1, 26 is an 1O order recursive filter section,
27 is an output delay element of the 10th-order cyclic filter 24; 28
is the output terminal.

次に動作を説明する。Next, the operation will be explained.

まず、人力信号は入力端子21から6次巡回型フィルタ
部22の人口である人力遅延素子23に人力される。6
次巡回型フィルタ部22は入力遅延素子23、出力遅延
素子24と合わせて11個の遅延素子を持ち、15回の
乗加算で信号を帯域制限する。6次巡回型フィルタ部2
3で帯域制限された信号は6次巡回型フィルタ部22の
出力遅延素子24から信号を16:1にダウンサンプリ
ングするデシメータ部2を経由して100次巡回型フイ
ルタ26に人力される。100次巡回型フイルタ26は
100次巡回型フイルタ26の出力遅延素子27と合わ
せて16個の遅延素子を持ち、25回の乗加算で信号を
帯域制限する。100次巡回型フイルタ26で帯域制限
された信号は100次巡回型フイルタ26の出力遅延素
子27から出力端子28を経て出力される。本実施例で
は6次巡回型フィルタ部23の出力遅延素子24は6次
巡回型フィルタ部23の出力サンプルを入力側に巡回さ
せるための6個の遅延素子の内の第1番目の機能と、1
00次巡回型フイルタ26の人力遅延素子(図示せず)
の機能を合わせ持ち、100次巡回型フイルタ26の出
力遅延素子27は10次巡回型フィルタ26の出力サン
プルを入力端に巡回させるための10個の遅延素子の内
の第1番目の機能を合わせ持っている。
First, a human input signal is input from the input terminal 21 to the input delay element 23 of the sixth-order recursive filter section 22 . 6
The next recursive filter section 22 has 11 delay elements including an input delay element 23 and an output delay element 24, and band-limits the signal by performing 15 multiplications and additions. 6th order recursive filter section 2
The signal band-limited by 3 is input from the output delay element 24 of the 6th order cyclic filter section 22 to the 100th order cyclic filter 26 via the decimator section 2 which downsamples the signal at a ratio of 16:1. The 100th order cyclic filter 26 has 16 delay elements including the output delay element 27 of the 100th order cyclic filter 26, and limits the band of the signal by multiplying and adding 25 times. The signal band-limited by the 100th order cyclic filter 26 is output from the output delay element 27 of the 100th order cyclic filter 26 via an output terminal 28. In this embodiment, the output delay element 24 of the 6th order cyclic filter section 23 has the function of being the first of 6 delay elements for circulating the output sample of the 6th order cyclic filter section 23 to the input side, 1
Manual delay element of 00th order cyclic filter 26 (not shown)
The output delay element 27 of the 100th order cyclic filter 26 has the function of the first of the 10 delay elements for circulating the output sample of the 10th order cyclic filter 26 to the input terminal. have.

このように本実施例では6次巡回フィルタ部23と10
0次巡回型フイルタ26の遅延素子数の合計が27であ
り、乗加算による演算ステップ数は合計40である。こ
れを従来の帯域制限回路における非巡回型フィルタ構成
で、本実施例と同等の帯域制限特性を持たせるには、遅
延素子数の合計が106、乗加算による演算ステップ数
の合計は105必要である。従って、本実施例の帯域制
限回路は従来と比較して、遅延素子の数で約1/イ、演
算ステップで約275となり、ハードウェア量、演算ス
テップ数共に大幅に減少した。この事に依り、ハードウ
ェア、演算共に他の機能を拡張する事も可能となる。
In this way, in this embodiment, the sixth-order cyclic filter sections 23 and 10
The total number of delay elements of the zero-order cyclic filter 26 is 27, and the total number of calculation steps by multiplication and addition is 40. In order to achieve the same band-limiting characteristics as in this example using an acyclic filter configuration in a conventional band-limiting circuit, the total number of delay elements must be 106, and the total number of calculation steps by multiplication and addition must be 105. be. Therefore, compared to the conventional band limiting circuit, the number of delay elements in the band limiting circuit of this embodiment is approximately 1/I, and the number of calculation steps is approximately 275, which significantly reduces both the amount of hardware and the number of calculation steps. This makes it possible to expand other functions in terms of hardware and calculations.

以上の実施例では、フィルタ部を6次と10次の巡回型
フィルタ部を2個、デシメータ部を1個で説明したが、
必要とする帯域制限特性に応じて次数及び段数が変更さ
れ得るのは明らかである。
In the above embodiment, the filter section was explained using two 6th-order and 10th-order cyclic filter sections and one decimator section.
It is clear that the order and number of stages can be varied depending on the required band-limiting characteristics.

(発明の効果) 以上詳細に説明したように、本発明によれば、フィルタ
部に巡回型フィルタを採用したことにより、遅延素子数
及び乗加算による演算ステップ数を大幅に低減させるこ
とができるので、回路が小型化できると共にシステム全
体の機能を拡大させることが可能となる。
(Effects of the Invention) As described in detail above, according to the present invention, by employing a recursive filter in the filter section, the number of delay elements and the number of calculation steps due to multiplication and addition can be significantly reduced. This makes it possible to reduce the size of the circuit and expand the functionality of the entire system.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す構成図、第2図は従来
の帯域制限回路を示すブロック図である。 21−・・入力端子、 22・・・6次巡回型フィルタ部、 23・・−人力遅延素子、 24.27−・・入力遅延素子、 25−・・デシメータ部、 26−10次巡回型フィルタ部、 28−・・出力端子。
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional band limiting circuit. 21--Input terminal, 22-6th-order cyclic filter section, 23--Manual delay element, 24.27--Input delay element, 25--Decimeter section, 26-10th-order cyclic filter Part, 28-... Output terminal.

Claims (1)

【特許請求の範囲】 フィルタ部と、サンプリングレートを落すデシメータ部
とを交互に多段接続させて成り、通過帯域内で遅延が一
定となるように周波数帯域を制限する線形予測用の帯域
制限回路において、 前記フィルタ部が巡回型フィルタであることを特徴とす
る帯域制限回路。
[Claims] In a band limiting circuit for linear prediction that limits a frequency band so that a delay is constant within a passband, the circuit consisting of a filter section and a decimator section that reduces the sampling rate connected in multiple stages alternately. . A band-limiting circuit, wherein the filter section is a recursive filter.
JP10463387A 1987-04-30 1987-04-30 Band limiting circuit Pending JPS63272116A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP10463387A JPS63272116A (en) 1987-04-30 1987-04-30 Band limiting circuit
EP88303795A EP0289285A3 (en) 1987-04-30 1988-04-27 Linear predictive coding analysing apparatus and bandlimited circuit therefor
US07/186,576 US4961160A (en) 1987-04-30 1988-04-27 Linear predictive coding analysing apparatus and bandlimiting circuit therefor
CA000565457A CA1311844C (en) 1987-04-30 1988-04-29 Linear predictive coding analysing apparatus and bandlimiting circuit therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10463387A JPS63272116A (en) 1987-04-30 1987-04-30 Band limiting circuit

Publications (1)

Publication Number Publication Date
JPS63272116A true JPS63272116A (en) 1988-11-09

Family

ID=14385849

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10463387A Pending JPS63272116A (en) 1987-04-30 1987-04-30 Band limiting circuit

Country Status (1)

Country Link
JP (1) JPS63272116A (en)

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