JPS6327050U - - Google Patents
Info
- Publication number
- JPS6327050U JPS6327050U JP1986121744U JP12174486U JPS6327050U JP S6327050 U JPS6327050 U JP S6327050U JP 1986121744 U JP1986121744 U JP 1986121744U JP 12174486 U JP12174486 U JP 12174486U JP S6327050 U JPS6327050 U JP S6327050U
- Authority
- JP
- Japan
- Prior art keywords
- cavity
- semiconductor device
- container
- substrate
- container substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986121744U JPS6327050U (enFirst) | 1986-08-07 | 1986-08-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986121744U JPS6327050U (enFirst) | 1986-08-07 | 1986-08-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6327050U true JPS6327050U (enFirst) | 1988-02-22 |
Family
ID=31011292
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986121744U Pending JPS6327050U (enFirst) | 1986-08-07 | 1986-08-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6327050U (enFirst) |
-
1986
- 1986-08-07 JP JP1986121744U patent/JPS6327050U/ja active Pending