JPS63269394A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve degree of integration, by providing a first input terminal by connecting load to the collector and the emitter of a resonant tunnel transistor in series and also, connecting a resistor to the base, and a second input terminal by connecting the resistor to the base, respectively. CONSTITUTION:The titled device is equipped with a transistor (for example, a transistor Q) whose base current has a differential negative resistance characteristic and whose collector current increases after the appearance of the differential negative resistance characteristic, the load (for example, a resistor R4) connected to the collector and the emitter of the transistor Q, the first input terminal (for example, an input terminal to which an input signal In1 is impressed) formed by connecting the resistor (for example, a resistor R1) to the base of the transistor Q, and the second input terminal (for example, the input terminal to which an input signal In2 is impressed) by connecting the resistor (for example, a resistor R2) similarly. In such a way, it is possible to reduce the number of required active devices, and to improve the degree of integration in a semiconductor memory device.

Description

[Detailed Description of the Invention] [Summary] The present invention provides a semiconductor memory device in which a load is connected in series with the collector-emitter of a resonant tunneling transistor, and a resistor is connected to the base of the resonant tunneling transistor. By providing an input terminal and a second input terminal by connecting a resistor to the base, a static random access memory can be constructed using only one active element.

[Industrial application field]

The present invention utilizes one resonant tunneling transistor (r
esonant-tunne 1 ingtransi
stor:RTT).

[Conventional technology]

Generally, static random access memory
(static random accesses
Memory: In SRAM), at least four FETs (FIG.
eld effect transistor
), two of which are applied to the clip-flop circuit, and the remaining two are applied to the transfer gate. Also, in the case of a double emitter bipolar transistor, at least two are required.

(Problems to be Solved by the Invention) At present, the greatest technical problem to be solved in semiconductor integrated circuit devices is high integration, and the above-mentioned semiconductor memory circuit is no exception.

By the way, in the past, efforts have been made to miniaturize the transistor itself in order to achieve this goal, but it is inevitable that such efforts will come to a dead end sooner or later.
It is necessary to adopt some other means.

Therefore, what can be considered is to maintain the same functions and effects as a semiconductor integrated circuit device, and to reduce the number of transistors that make up the device.

However, in the case of semiconductor memory circuits, as long as ordinary transistors are used, there is a limit to how these problems can be addressed, and this is also at an impasse.

The present invention is applicable to, for example, resonant-tunneling hot electron transistors.
ing hot electr.

RTT such as ntransistor (RHET)
By configuring a semiconductor memory circuit in this way, the number of required transistors is reduced and the degree of integration is improved.

[Means for solving problems]

In recent years, research and development of so-called RTT, including RHET, which utilizes a resonant tunnel barrier as a carrier injection source, has been active.

Figure 4 is a diagram showing the voltage/current characteristics of RHE T, which is a type of RTT, with the horizontal axis representing the base-emitter voltage, and the vertical axis representing the base current I and the collector current. Each IC was taken.

In the figure, base current is and collector current ■.

For the characteristic line of and S2 indicate the stable point.

As can be seen from the figure, the base current II in the RHET exhibits an N-shaped characteristic and has a so-called differential negative resistance characteristic, and the collector current I is almost constant until the differential negative resistance characteristic appears in the base current is. It does not flow, and after it appears, it quickly rises (in short, patent application 138630/1986)
(see issue).

By utilizing such characteristics, a flip-flop circuit can be constructed using one RHET.

FIG. 5 shows a flip-flop circuit using RHET, and the same symbols as those used in FIG. 4 indicate the same parts or have the same meanings.

In the figure, Q is a RHET transistor, R3 is a resistor inserted in series with the base and emitter, ■ is the base input voltage, and VCC is the positive power supply level.

The operation of the circuit shown in FIG. 5 will be explained with reference to FIG.

When Vm=VszO, there are two stable points S and 8 at the operating point.
2 exists, and in the case of a stable point SI, the collector current IC is hardly flowing, so this transistor Q is in the off state, and in the case of a stable point S2, the collector current ■, is flowing, so the transistor Q is in the on state.

In order to change the operating point from the stable point S1 to Sz, that is, to transition the transistor Q from off to on, once Vl > Vl3
, and then change it to VIl-VIl2 again.

In order to transition the operating point from the stable point S2 to Sl, that is, from on to off the transistor Q, once Vll<Vll
Then, set V,=VB□ again.

As can be seen from the foregoing description, the circuit shown in FIG. 5 is capable of flip-flop operation using only one transistor Q as an active element.

As described above, since a flip-flop circuit can be configured with only one RTT such as RHET, the inventor succeeded in realizing an SRAM extremely easily by making some modifications to the flip-flop circuit.

FIG. 1 shows a main circuit diagram for explaining the principle of a semiconductor memory device according to the present invention, and the same symbols as those used in FIG. 5 indicate the same parts or have the same meaning. do.

In the figure, R+, Rt, Ra are resistances, Io and ■
. 2 indicates an input signal, and O2 indicates an output signal. Note that here, the input signals Iru and I, l□ are connected to the resistor R
4 and R2, is assumed to be the base input terminal 8.

FIGS. 2(A) to (D) represent timing charts for explaining the operation of the semiconductor memory device shown in FIG. ,
(C) is the base input voltage■.

, (D) relates to the output signal O2, and in both cases, the horizontal axis represents time and the vertical axis represents level, which were used in Figures 1 and 4. Symbols and the same symbol indicate the same part or have the same meaning.

In the figure, T'+, Tz, T3, T4, Ts
indicates the timing.

The operation of the semiconductor memory device shown in FIG. 1 will be explained with reference to FIGS. 2(A) to 2(D).

Now, in the semiconductor memory device shown in FIG.
If the resistances R1 and R2 are set to be small compared to the sum of the resistance and the base-emitter resistance, the base input voltage V is determined approximately depending on the resistances R8 and R2. Note that although the resistance R3 and the RtO value are assumed to be equal here, the present invention is not limited to this. And resistors R3 and R2
When the values of are equal, the base input voltage V, is equal to the input signal Inl and 1. l! The value will be intermediate between . Also, if the operating point of the transistor Q is at the stable point SI, it is inconductive, that is, it is in the off state, and the output signal 0° is at "H" level, and if the operating point is at the stable point S2, it is conductive, that is, it is in the on state. Therefore, the output signal 0 is "L level".

Input signals ■1 and I. , the value of the base input voltage vll, which is the average voltage, becomes the high level (
“H” level), medium level (“M” level)
, low level (“L” level) are obtained, and when the input signals I, , , and I7□ are both “H” level, the base input voltage V, is also “H” level, and both are “H” level. L"
When the level is high, the level is "L", and at other times, the level is "M".

A case in which information is written or stored in this semiconductor memory device will be described.

Now, it is assumed that the operating point of the transistor Q is at the stable point SL, and as seen at timing 2 or T4 in FIG. Voltage ■.

When is at “H” level, it is vs.
If it is set to be larger than i, the transistor Q
The operating point of is a transition from the stable point S, to St.

Furthermore, as seen at timing T in FIG. 2, when both input signals ① and 11 are at the "L" level, that is, when the base input voltage VB is at the "L" level, the timing T in FIG. If you set it to be smaller,
The operating point of transistor Q transitions from stable point S2 to Sl.

Furthermore, either one of the input signals ■1 and I7□ is “H”.
” level and the other is “L” level, if the base input voltage VIl is set to be between V113 and V in FIG. 4, no transition will occur in the operating point of transistor Q. .

To summarize the above, input signals 1 and 1.
, are both at H" level or "L" level, information is written (rewritten). Otherwise,
Information is stored, that is, the semiconductor memory device performs a memory operation. Here, as shown in Figure 2, if the input signal IME, which is a pulse, is a timing pulse for information writing (rewriting), when this timing pulse is input, the input signal I0 goes to the "H" level. If so, the output signal O4 changes from the “H” level to the “L” level, and in that case, if the input signal In+ is the “L” level, the output signal Ot changes from the “L” level to the “H” level. It changes depending on the level.

Next, a case in which information is read from this semiconductor memory device will be described.

In this case, the "M" level is applied as the input signal 1 nl, so when the input signal I+sz is input, the operating point of the transistor Q changes from the stable point Sl to St.
Alternatively, a situation such as a transition in the opposite direction does not occur, and therefore no writing (rewriting) is performed.

Now, suppose that the operating point of the transistor Q is at the stable point SI, and as seen at the timing Tt in FIG. 2, the input signal 1.11 is at the "M" level, and the timing
Even if the input signal 1nt, which is a pulse, is input, the output signal OL changes very little because the transistor Q is inconductive, that is, in an off state. In other words, in this case, input signals 1. Even if there is a change in the output signal 01, there is almost no change in the output signal 01, and in FIG. 2(D), this state is indicated by a circle and a symbol A.

However, if the operating point of the transistor Q is at the stable point S2, as seen at timing T5 in FIG. In! , the transistor Q
is conductive, that is, is in an on state;
Moreover, as can be seen from FIG. 4, the collector current T changes rapidly with a slight change in the base input voltage (4), so that the output signal 0. A large change occurs, and in FIG. 2 CD>, this state is indicated by a circle and a symbol B.

If the magnitude of such fluctuation in the output signal OL is detected, the transistor Q will be adjusted to the stable points S1 and S! It is possible to know which operating point the current state is in, and to read information.

As described above, in the semiconductor memory device according to the present invention, the base current has a differential negative resistance characteristic, and the collector current flows significantly after the differential negative resistance characteristic appears (for example, the transistor Q). ), a load (e.g., resistor R,) connected in series with the collector/emitter of the transistor, and a first input terminal (e.g., input signal 1) and a second input terminal (for example, an input terminal to which an input signal rnz is applied), which is also formed by connecting a resistor (for example, a resistor R1) to the base.

[Effect]

By adopting the above means, by applying an input signal of "H" level or "L level" to the first input terminal and the second input terminal, information can be written to the first input terminal. “M
It is possible to read out information by applying a level input signal and a human input signal, which is a timing pulse, to the second input terminal.
Since the AM is composed of only one RTT and several resistors, the number of required active elements is reduced compared to the conventional technology, and therefore the degree of integration of the semiconductor memory device is dramatically improved.

〔Example〕

FIG. 3 shows a circuit diagram of a main part of an embodiment of the present invention, and the same symbols as those used in FIGS. 1 and 2 indicate the same parts or have the same meanings.

In the figure, Ql, Q2... are RHET transistors, WLI, WL2... are word lines, BL
I, BL2... are bit lines, RRl, RL2...
・indicates a readout line, respectively.

As can be seen from the figure, in this embodiment, the semiconductor memory devices explained in connection with FIGS. 1 and 2 are arranged in a matrix to form an array, and transistors Q1, Q2, . . .
Input signals In+ for the respective word lines WLI, WL2, . . . and input signals 1 .
2 is also the corresponding bit line BL1. BL2...
Also, the transistors Ql, Q2...
The output ends of the respective read lines RL1. R.L.
2... is connected to...

In this embodiment, to write (rewrite),
Word line WL (representative of WL 1, WL 2, etc.) and bit line BL (BLI, BL2, etc.)
(representative) to “H” level, or
Goes to "L" level. For example, when the word line WL is set to the "H" level and a timing pulse of the "H" level is applied to the bit line BLI, the transistor Q1 is selected and writing is performed.

In addition, in order to read, for example, the word line WL is
M” level and apply timing signal to bit line BLI.
When a pulse is applied, information is read out from transistor Ql to readout line RLI. At this time, it goes without saying that there is no change in other transistors Q2, etc., but if there is a concern that the read information, that is, the current, will affect other memory cells. For example, transistor Q
If you insert a capacitor between the output terminal of the terminal (representing Ql, Q2, etc.) and the readout line RL (representing RLI, RL2, etc.) and take out only the voltage change, the problem will be solved. will disappear.

〔Effect of the invention〕

In the semiconductor memory device according to the present invention, a load is connected in series with the collector-emitter of the resonant tunneling transistor, a resistor is connected to the base of the resonant tunneling transistor, and the first input terminal is connected to the base of the resonant tunneling transistor. A resistor is connected to each provide a second input terminal.

By adopting such a configuration, information can be written by applying an input signal of ``H'' level or ``L level to the first input terminal and the second input terminal, and information can be written to the first input terminal. By applying an “M” level input signal and an input signal that is a timing pulse to the second input terminal, it is possible to read information, respectively. Compared to the conventional method, the number of active elements required is reduced, and the degree of integration of the semiconductor memory device is therefore dramatically improved.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a main part of a semiconductor memory device for explaining the present invention in detail, and FIGS. 2(A) to (D) are timing diagrams for explaining the operation of the semiconductor memory device shown in FIG.・Chart, Figure 3 is a circuit diagram of the main part of one embodiment of the present invention, Figure 4 is a diagram showing the voltage/current characteristics of RHET, Figure 5 is a diagram of RHET.
Each shows a circuit diagram of a main part of a flip-flop circuit using ET. In the figure, 1. is the base current, I is the collector N? M
,, ■, is the base-emitter voltage, S1 and 'C) S
z is the stability point, Q is the RHET transistor, R+
, Rz, R3, and Ra are resistors, I7□ and 17□ are input signals, 0. is the output signal, ■ is the base input voltage, V
CC indicates the positive power level. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney: Akira Aitani Representative Patent Attorney: Hiroshi Watanabe - Figure 1 Main part circuit diagram of a semiconductor storage device using RHET Figure 1 Main part circuit diagram of an embodiment Figure 3 Figure 4: Diagram showing voltage and current characteristics Figure 5: Main part circuit diagram of frill-flop circuit using RHET

Claims (1)

[Claims] A transistor whose base current has a differential negative resistance characteristic and whose collector current flows significantly after the differential negative resistance characteristic appears; a load connected in series with the collector and emitter of the transistor; A semiconductor memory device comprising: a first input terminal formed by connecting a resistor to the base of a transistor; and a second input terminal formed by connecting a resistor to the base.