JPS63263577A - Parallel processing device for image - Google Patents

Abstract

PURPOSE:To effectively execute the parallel image processing and to attain the high speed processing by sending one unit of the image processing composed of plural picture elements to an empty processor as the input pair of a picture element address and image data and also making the address and the image data after the image processing into an output pair and returning them. CONSTITUTION:The device is the parallel processing device for an image to execute in parallel the image processing to make plural picture elements into one processing unit with individual processors, and equipped with a means 11 to control the emptiness of respective processors 13 and the processing completion at respective processors, and a supplying means 20 to supply an input pair composed of the image data of the picture element and the address of the input image space of the picture element to the unspecified empty processor concerning the individual picture element of one processing unit. The processors 13, to which the input pair of one processing unit is supplied, processes the input pair of one processing unit and returns the output pair to add the address of the output image space of the image data to the image data after the processing. Thus, the parallel image processing is effectively executed with plural processing units and the high speed processing can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image parallel processing apparatus, and more particularly to an image parallel processing apparatus using a plurality of processors.

[Prior Art] Pipeline processing has conventionally been used as a means for performing image processing at high speed. In this method, one process of image processing is subdivided into n sequential processing steps that do not interfere with each other, and the n subdivided processing steps are integrated into one processor. Then, the image data string is manually input to this processor, as if it were processing n pieces of image data at once, with the aim of increasing the speed as a result.

[Problems to be Solved by the Invention] However, this method requires special hardware, and the hardware is dedicated to specific processing, and is not flexible with respect to other processing or general-purpose processing.

On the other hand, one general-purpose MPU (Micro Process
When image processing is performed using ``Sor IJnit'', the versatility is high because various processes are processed by software, but on the other hand, the processing speed is slow.

These problems are basically due to the special nature of the image that is the object of processing. In other words, in normal data processing other than image processing, relationships and correlations between data are not so much of a problem, whereas in images, a collection of individual pixels constitutes one image. Therefore, if these pixels are processed separately, the image itself will not be formed. This is because a pixel essentially consists of image data and pixel position information (address).

The present invention was proposed in order to eliminate the above-mentioned conventional drawbacks by going back to the essence of images and essentially considering their suitability for parallel processing of images. The purpose of this invention is to propose a parallel image processing device that can effectively perform parallel image processing and perform high-speed processing.

[Means for Solving the Problems] The configuration of the parallel processing device according to the present invention for solving the above problems is an image processing system in which individual processors perform image processing in parallel with a plurality of pixels as one processing unit. A parallel processing device, comprising: means for managing availability of each processor and completion of processing in each processor; and input consisting of image data of a pixel and an address of an input image space of this pixel for each pixel of the one processing unit; and a supply means for supplying the pairs to an unspecified vacant processor.

[Operation] According to the above configuration, the processor supplied with the input pair of one processing unit processes the input pair of one processing unit,
An output pair is returned in which the address of the output image space of the image data is added to the image data after this processing.

[Examples] Examples of the present invention will be described in detail below with reference to the accompanying drawings.

(Outline of Embodiment Apparatus) FIG. 1 shows an embodiment of a parallel processing apparatus to which the present invention is applied.

In the figure, 10 is an image memory that stores image data to be image processed, 13-1 to 13x are MPUs that are processing units for image processing, and 20 is the above-mentioned MPU III to 1.
11 is the image memory 10
16 is a display device that displays the contents of the image memory 10; . As will be described later, in this embodiment, in order to achieve high-speed processing, the CPU 20 is only involved in the initial setting process and final process of image processing.

The image memory 10 consists of an IC memory that accommodates, for example, 1024×1024 pixels. Since this pixel has color data, one pixel has 24 bits (R = 8 bits,
G zero 8 bits, B=8 bits). MP
N numbers from 1 to N are used for U (13-, ~13-
), the contents of the image memory 10 are stored in the display controller 15.
The zero image memory 10 displayed on the display device 16 via the dual port RA is accessed by the R/W controller 11 and the display controller 15.
It is configured using M.

Each MPU has its own RAM (14-Otori to 14-N), and this RAM is used normally as a storage area for programs executed by each MPU, and as a work memory for temporarily storing image data that is being processed. . Thus, each MPU
A processing unit (PE) is formed by the RAM 1 associated therewith and a queue buffer to be described later. Master CPU
20 has its own local memory RAM 19,
As will be described later, this RAM 19 stores the control program of the master CPU and, if necessary, each MPt) (t3-,
~13-. ) contains a processing program for image processing that is sent to

The image data processed by each processing unit and the processed image data are temporarily stored in queue buffers 12-1 to 121 corresponding to each processing unit. These queue buffers have input and output queues, and the input queue mainly stores multiple pieces of unprocessed image data.
A plurality of pieces of processed image data are stored in the output queue. That is, each queue buffer forms a queue for each processing unit.

<Storage of Processing Program in RAM> The processing program stored in the RAM (111 to 14-N) of each processing unit will be described. The parallel processing method in this embodiment is SIMD (SingleIn
structure Stream / Multi
Data Stream), each M
All PUs execute the same processing program. When performing certain image processing, there are two methods for how the processing program corresponding to that processing is stored in the RAM of each MPU and how each MPU executes that program. It will be done.

One is that for each image process, the master CPU 20 creates a corresponding processing program (this is stored in the RAM 19).
to the RAM (14-, ~l4-N) of each MPU via bus 1
8. Another method is to
The master CPU 20 has a plurality of processing programs, and the master CPU 20 only sends instructions on which processing to perform to each MPU. The former is RAM14-t~14 that each MPU has.
-N requires a small capacity, but it takes time to load the program. The latter requires each MPU to have a fi-embedded program, which increases the capacity of the RAMs 14-r to 14-8. The latter is better if the program to be processed is small, but the former is better in order to be able to perform any general processing. Therefore, use them appropriately depending on the purpose.

In the embodiment described below, all image processing programs are stored in the local RAM 14 of each MPU.

(Image Memory Addressing) As shown in FIG. 2, the image memory address is configured so that it can be specified using an X-address and a Y-address. That is, the X-address can take values from 0 to X, 8, and the Y-address can take values from 0 to Y, , 8. This (x.

Image data at any point in the image memory can be retrieved depending on the value of Y). Now, the image memory 10 is 1024
x 1024 pieces of image data, X□, F Y□, = 1024 children 210, each with 10
Bit address space.

<Format of Bus Data> The format of data flowing on the bus 17 connecting each queue buffer and the R/W controller 11 is shown in FIGS. 3A to 3B.

The first field of each format is a 5YNC field. This is so that the hardware at the physical layer level recognizes that data exists on the bus.

The first field of each format in Figures 3A to 3C stores the MPU number; for example, if the number of MPUs is 4, it is 2 bits (0° 1.2.3) long and 2. .

The format shown in Figure 343A is used by the R/W controller 11 in the selecting sequence, and by this selecting, the control bits, the (x, y) address of the image memory, the image data of the image memory, etc.
The data is sent to the queue buffer 12 of the MPU with the number indicated in the PU number field. Here, the two control bits have the contents shown in FIG. 4, but their detailed contents and how they are used will become clear from the embodiments described below.

FIG. 3B shows the poll sequence from the R/W controller 11; once the R/W controller 11 has sent up the ball, the corresponding PE that has data to send will subsequently put the data on the bus 17.

Figure 3C shows the response data from PE, where ACK indicates that the data was successfully received for the selecting sequence from PE, and NAK indicates that the input queue is full.
MPTY indicates that the input queue was empty for polling.

<Schematic principle of the embodiment> The embodiment described below has two configurations (first embodiment and second embodiment).
Basically, the hardware configuration shown in Figure 1 is common, and the data transfer form between each MPU and image memory, each MPU
This is achieved by skillfully changing and configuring the image processing format.

FIGS. 5A and 5B show the source/destination of image data transfer, etc., performed in the first embodiment and the second embodiment, respectively.

The image processing in the first embodiment (FIG. 5A) is mainly represented by masking processing, γ conversion processing, binarization processing, and the like. That is, the number of pixels to be image processed is one, and the image processing is such that only information regarding the one target pixel is required for IA filling. On the other hand, in the second embodiment (Fig. 5B), image processing such as Laplacian processing, emphasis processing, edge detection, and smoothing processing is characterized by having a spatial extent (-dimensional, two-dimensional), that is, In order to perform image processing, information regarding a plurality of pixels is required.

The information regarding this pixel is an address in the image memory and image data such as density and brightness of one color.

According to the first embodiment shown in FIG. 5A, three consecutive pixels (n, n+1.n+2) in the image memory 10 are
I don't mind being sent to. That is, in order to increase the efficiency of parallel processing, pixel information is sent as a pair of address and image data from the image memory 1° to any available PE, where the image is processed at high speed, and then After image processing,
The processed image data and the processed address are paired as R/
It is sent back to the W controller 11. The R/W controller 11 stores this returned image data according to the same returned address.

In this way, image processing such as masking processing, γ conversion processing, binarization processing, etc., that is, the number of pixels to be processed is one, and for this purpose only information regarding the one target pixel is required. If such image processing is performed in the first embodiment shown in FIG. 5A, the efficiency of the overall image processing will depend on the number of PEs, and moreover, the image data and memory address will be transferred in pairs. Therefore, the integrity of the image after processing is not lost.

According to the second embodiment shown in FIG. 5B, since the unit of image processing performed by one PE includes a plurality of pixels, this one unit, that is, the information of the plurality of pixels of this unit is summarized, P
Transfer it to E.

If pixels within the same unit are transferred to the same PE,
The processing unit can be transferred to any PE as shown in FIG. 5B, increasing the parallelism of the overall image processing and improving efficiency.

In addition to the image processing described above, there are, for example, affine transformation such as parallel translation and one rotation, and binarization processing such as dither processing. Affine transformation and the like can basically be handled by the first embodiment shown in FIG. 5A, since memory address calculation corresponds to image processing. Furthermore, even if the binarization matrix is two-dimensional, the binarization process can be handled by the first embodiment because image processing of one pixel does not require information about surrounding pixels.

Now, as is clear from FIGS. 5A and 5B, the presence of the queue buffer 12 is not wooden in the present invention. However, in reality, the time required for image processing performed by each MPU is longer than the time required for exchanging data on the bus 17. That is, if the vehicle is configured only as shown in FIGS. 5A and 5B, an increase in the idle time of the R/W controller 11 becomes a problem. In order to minimize the idle time, the queue buffer 12 shown in FIG. 1 etc. is provided.

(R/W controller) The R/W controller 11 shown next is a controller that controls data input/output between the image memory 10 and each MPU 13. In other words, this controller The functions are: (1) Allocating the image data in the image memory 10 to each MPU, (2) Returning the image data processed by each MPU to the image memory, and (3) For that purpose, communication between each queue buffer. 6 shows the configuration of the R/W controller 11 and its connections with the data memory 10 and each queue buffer.In the R/W controller 11, a bus 17 is a bus interface. 54 to the MPU 51. This bus interface 54 performs communication control. The ROM 52 stores a program shown in FIG. 13, which will be described later. The RAM 53 stores intermediate information and flags shown in FIG. etc. are stored.The MPU 51 is connected to the image memory 10 via the bus 50.

(MPU = interface between R/W controllers) Figure 7 shows queue 1, which includes two queues for input and output.
2a and interface 12b, it generally shows how the queue buffer 12 interfaces with the MPU 13 and the bus 17.

The data exchanged between the MPU 13 and the bus 17 are memory address/image data pairs shown in FIGS. 3A and 3B. The interface signals shown in FIG. 7 are used to exchange this pair of data.

When the interface control unit 12b receives the poll sequence shown in FIG. 3B, only the interface control unit 12b that matches the MPU in this poll format passes a signal poll to the queue 12a. Upon receiving this poll, the queue 12a passes the memory address/image data pair etc. stored in the output queue to the control unit 12, and the control unit 12b transfers the memory address/image data pair etc. onto the bus 17. , ``Send in the format shown in Figure 3B.

When the control section 12b detects a selecting sequence on the bus 17, the operation of the control section 12b differs depending on the configuration of the control bits of the format. In FIG. 4, in the flow from the image memory to the MPU, when the control bit=00.01, the memory address/image data pair, etc. in the selecting sequence are stored in the input queue. Control bit =
11, the signal INT (interrupt signal) interrupts the MPU and the MPU is quickly processed without queuing.
The reason why queuing is not performed when the control bit = 11 when the memory address/image data pair is passed to the PU will become clear in the explanation of the second embodiment.

The MPU receives data from the input queue by transmitting the input queue's device address and read (R) signal to queue 12.
This is done by sending it to a. The MPU sends data to the output queue by sending a write signal (W) to the queue 12a.

<Queue> Figures 8A and 8B show input queues, respectively. Shows the configuration of the output queue. The queue is a first-in, first-out (FIFO) memory consisting of a shift register or the like. To perform first-in, first-out, the input queue is as shown in Figure 8A.
An up/down counter 32, a decoder 33 that decodes the count value of this counter, a shift register 35 that receives a pair of memory address/image data as a shift input, and the output of the decoder 33 selects one of the shift registers 35. and a selector 34 that selects the output of the stage and outputs it to the MPU. On the other hand, the configuration of the output queue is as shown in FIG. 8B, but since it is roughly the same as that in FIG. 8A, a description thereof will be omitted.

In the input queue of FIG. 8A, R/W controller 1
When receiving selection from 1, the counter 32 increments by 1 according to the output of the gate 31, and at the same time, the shift register 35 shifts and inputs the memory address/image data pair, etc. Conversely, when there is an R signal from the MPU, the counter 32 decrements by one. That is, the counter 32 points to the position of the data stored earliest in the shift register 35 and not yet taken out by the MPU. Thus, a first-in, first-out function of the queue is realized.

Incidentally, when the shift register 35 is full of input queues, that is, when the value of the counter 32 is maximum, a signal F'U LL is returned to the interface control section 12b. At this time, if there is selection from the R/W controller 11, the NAK shown in FIG. 3C is returned. Further, in the output queue of FIG. 8B, when a poll sequence is received when the queue is empty, the control section 12b which receives the signal EMPTY from the queue 12a outputs EMPTY in the format of FIG. 3C.
Return TY.

Input queue. Regarding the size of the output queue, if the image data to be handled is 8 bits each for the three colors RGB, the size of the image memory is 1024x1024, the number of MPUs is 4, and the types of control bits are 4, the memory address is 20 bits are required for image data, 24 bits are required for image data, and 8 bits are required for control bits, making a total of 52 bits. Therefore, the length of the queue is set to 52 bits, and the width (capacity) is set to 1 image memory.
The number is 1024, which corresponds to the number of pixels in one line of 0. That is, one queue is 52 bits x 1024. still,
As can be seen from FIG. 8A and the explanation of the flowcharts described later, in this embodiment, the processing when the queue is full is taken into account, so the queue is reduced to 256, 128, etc. It is also possible to increase the scale, and in that case, the processing efficiency should be kept as low as possible.

[Blank below] (Pixel allocation by R/W controller) As shown in Fig. 1, the basic premise of this embodiment is to have a plurality of PEs.
, 5B, the present invention is characterized in that there is no restriction that a certain pixel before processing should be sent to any specific PE. This feature allows parallel processing to be performed at high speed.

However, in the second embodiment, which performs spatial filter processing such as Laplacian, for example, when performing filter processing on two consecutive pixels, the overlapping part (the shaded part in Fig. 9) in the block corresponding to the filter is ) will appear. FIG. 9 shows a case where 3×3 Laplacian processing is performed on the center j pixel. If it is assumed that there is no gender, the R/W controller 11
Therefore, the above-mentioned duplication judgment should not be made.

If the R/W controller 11 sends pixel information to vacant PEs in a random manner without making any judgments, as shown in FIGS. 5A and 5B, even if the above-mentioned duplicate pixels exist, it is necessary to resend them. It comes out.

However, in this case, the feature of the present invention, which increases the speed of parallel processing by breaking the dependency relationship between pixels and PEs, is somewhat diminished.

Therefore, in the second embodiment, special measures are taken to access the image memory of the R/W controller 11.
Consecutive pixels are sent to the same PE as much as possible, eliminating the need to resend duplicate pixel information and reducing the number of data transfers between the L/PE and the R/W controller 11.
This points to an even faster parallel processing than the configuration shown in FIG. 5B. This idea is to equally divide the memory space of the image memory 10 into the number of PEs, as shown in FIG. In the example of FIG. 10, the number of PEs is four, so it is divided into four. After dividing in this way, the pixel information of the image memory is allocated to each PE as follows. The start address in each area is expressed as: (n, z5axsc). Here, k means area number, k=
0.1, 2.3, and n represents the address value of the image memory in the X direction, and 0≦n≦1023. Further, each pixel position within the area is expressed as =(n, m+256xk). Here, 1 and m represent address values in the Y direction, and O≦m≦255. After representing the pixel addresses in this way, each area and each PE are made to correspond one to one. Then, the R/W controller 11 sequentially scans the pixels from the beginning of each area and extracts one pixel at a time, and sends the memory address/image data pair of that pixel to the corresponding PE. In this way, consecutive pixels in the horizontal (X) direction will be sent to the same PE, eliminating the above-mentioned retransmission of duplicated pixel information, reducing the operating rate of the first bus, and preventing collisions. This results in more efficient parallel processing.

In addition, in Fig. 10, (n [k], m [k] + zssxsc) is used because the correspondence between PEs and areas is determined, and when they are transferred independently and in parallel, the current transfer address is transferred between areas. This is because there is a possibility that they differ.

Let us now consider what the above correspondence should be like when performing spatial filter processing as shown in FIG. 9. In this case, if we take the correspondence between PEs and areas as shown in Figure 10, the center pixel and the eight surrounding pixels will be sent to the same PE, and the next center pixel will also be sent to the same PE. .

That is, a route between each PE and each area as shown in FIG. 11A is established. The capacity of each area is 1024×256 pixels, and the capacity of the input queue is 1024×1 pixel. Since loading an image into a queue is faster than processing an image in a PE, there is a possibility that a certain PE's manual queue is full.

However, rather than waiting for a certain PE's input queue to become empty when it is full, there is a possibility that another PE's queue is empty, so instead of searching for this empty PE and sending the above message to that queue. It is more efficient to send information about pixels that could not be transmitted. In Figure 11A, if the PEI queue is full and there is space in the PE2 queue, the 11th
Change the correspondence between PE and area as shown in Figure B. If you do this, when you change the correspondence, the continuity of the data in the input queue before and after the change will be lost, but the correspondence after the change will be changed until some queue becomes full again. As long as it is not changed, it will be maintained and continuity will be maintained, making processing more efficient.

<Outline of data transfer procedure> FIG. 12A explains the outline of the transfer of the memory address/image data pair in the first embodiment, and FIG. 12B explains the outline of the transfer of the memory address/image data pair in the first embodiment.
Let's talk about it in an example. Data transfer in this embodiment uses, for example, a polling/selecting method, in which the R/W controller 11 is a master station and each PE is a slave station.

In the first embodiment, the memory address before processing is periodically
The R/W controller 11 reads the image data pair from the image memory 10, adds a control bit=00, and sends it to the input queue of the PE in a selecting sequence. The PE returns ACK if the input queue is empty, and returns NAK if it is not. For the memory address/image data pair of the human queue, the MPU performs image processing on the image data in the case of γ transformation, etc., and calculates the pixel address in the case of affine transformation, etc., and calculates the image processing result. Return the memory address/image data pair to the output queue with control bit=11. The R/W controller 11 periodically polls the output queue,
Memory address / where this control bit = 10
A pair of image data is taken from the output queue and stored in the image memory 10 pointed to by the memory address. In the configuration shown in FIG. 1, since both the input queue and the output queue have a capacity of 1024 pixels, the R/W controller 11 transfers the memory address/image data pair to the PE and the processed memory address from the PE. /The transfer of image data pairs is performed asynchronously. The presence of the queue and this asynchronous processing eliminates bottlenecks on the bus 17 and achieves high-speed processing.

In the second embodiment as well, the R/W controller 11 periodically reads out the unprocessed memory address/image data pair from the image memory 10 and sets the control bit to 0.
and sends it to the PE's input queue in the selecting sequence. The PE returns ACK if the input queue is empty, and returns NAK if it is not. Everything up to this point is the same as the first embodiment. The pixels placed in this input queue are
For example, this is the center pixel of the 3×3 block in FIG. 17.

The MPU calculates the addresses of pixels around this center pixel and sends the image data of the surrounding pixels to the R/W controller 1.
In order to request 1, the address of the peripheral pixel with control bit=11 added is placed in the output queue. The R/W controller 11 periodically polls this output queue and retrieves it, reads out the image data of the pixel at this address from the image memory 10, and stores the read image data, its memory address, and the controller.5. PE = 11 by selecting sequence again.
send it back to

When the PE side receives the selecting sequence with control bit=11, the interface control unit 12b of the PE interrupts the MPU without putting it into the input queue. The interrupted MPU reads this data on the bus 17 with a read command. In the example of FIG. 17, there are 8 peripheral pixels, so there are 8 requests with control bit = 11 stored in the output queue.
As a result, eight of the above-mentioned interrupts occur due to the selecting sequence of control bit=11. Thus 8
When the two peripheral pixels are aligned within the PE, image processing such as filter processing is performed, and the resulting memory address/image data pair is assigned a control bit of 10 and stored in the output queue. The R/W controller 11 obtains the memory address/image data pair of the output queue after image processing by polling, and stores it in the image memory 1o. In this way, image processing such as spatial filtering is performed.

By the way, the reason why interrupts are used in the second embodiment is that most of the input queue is used for the memory address/image data pair of the center pixel, and the output queue is used for the request of peripheral pixels and the memory address/image data after processing. This is because they are mostly used in pairs. It is also conceivable that the R/W controller 11 allocates the peripheral pixels and puts the memory address/image data pairs of the center pixel and eight peripheral pixels into an input queue, but it would take time and effort to process pixels that span between areas. , and the utilization rates of the input queue and output queue become unbalanced. Therefore, it is better to allocate the peripheral pixels mentioned above by the PE and obtain the peripheral pixels by reading I10 using an interrupt from the MPU. desirable.

Furthermore, by not providing the R/W controller 11 with a transfer algorithm that depends on image processing, the R/W controller 11 can continuously send unprocessed pixels one after another to the PE, and the first This has the effect that the transfer algorithm of the R/W controller 11 can be made common to the image processing of the embodiment and the second embodiment.

(Transfer control in R/W controller) Fig. 13A,
R/W controller 11 using Fig. 13B and Fig. 14.
The control procedure will be explained. Figure 14 shows the R/W controller 1 when PE is connected to N systems.
1 shows intermediate data, flags, etc. used for control.

As described above, n [kl, m [kl] indicates the relative address of the pixel that is about to be sent to the PE. Transmission completion flag [kl is a flag indicating that all pixel information for the second area has been transmitted to the PE side. Further, for each PE, a reception buffer for receiving data from the PE and a transmission buffer for sending data to the PE are prepared.

In the flowcharts of Figures H13A and 13B, PE
The notation PE [1] is used to specify the first PE from among. Also, R is added to indicate the receiving side, and S is added to indicate the transmitting side to distinguish them.

Further, the X address and Y address of the image memory are expressed as XMS (for sending) and XYR (for receiving).

Incidentally, the storage in the reception buffer and the actual transfer of data from the transmission buffer are performed by the bus interface 54.

A flowchart of the R/W controller 1 will be explained according to FIG.

First, a case will be described in which memory address/image data pairs of 200 control bits are transferred to the PE in order from the beginning of each area.

In step S2, the subscript 1 indicating PE is initialized to the subscript indicating the area. In step S4, a poll sequence (FIG. 3B) is sent to the first PE. Now, when data transfer is started from the image memory 10 to the PE, EMPTY shown in FIG.
Find out. Since the transmission has not finished yet, step S
Proceed to 42. In step S42, the control bit S of the transmission buffer is set to 00. When a control bit is set to this value, the PE that receives this control bit can confirm that the data was sent not as a specific PE but as an arbitrary PE (4th
(see figure).

In step S44, (n [k], m [k]
+256Xk) accesses the pixel at address. When step S44 is first reached, n[k], m[k]±0. At step 346, (n[k].

The image data of the pixel at address m [k] +256Xk) is stored in the image data S of the transmission buffer. Step S4
8, the value of (n [k], m [k] +256Xk) is stored in XYS of the transmission buffer. This completes the contents of the send buffer. In step S50, [-1
The contents of this [−11th] transmission buffer are sent to the ]th PE. In step S52, an ACK from the interface control unit 12b of the PE is confirmed. This is because nothing other than ACK will be returned until the input queue is full. After confirming ACK, the next pixel in the kth area is pointed at step S54 or step S60. That is, when it is the turn to send out the pixels of the th area again, (n [k] +1゜m [k] +25
6Xk), or (n [k].

m[k]+1+256xk).

From step S56 or step S62, step S6
Go to 6 and move the pointer l to point to the next PE.
Increment by one. In step S72, the pointer k is incremented by one in order to point to the next area. In this way, from step S74, the process returns to step s4, and the operation of sending one pixel of one area to one PE ends.

In the cycle from the next step S4, the PE is PE[
1+1], the area is pointing to +1,
The sending pixel address of area [k+13 is (n [k+1
] , m [k+1] +256Xk) or (n[k+
1, m [k+1] +256xk) (Step S44. Step 548). In this way, information on one pixel in the k+1th area is sent to PE[1+1.

Steps S56 to Sho are control at line changes. Steps S68 and 370, and steps S72 and S74 are control for circulating PEs and areas when the number of PEs is four, respectively.

Steps S62 and S64 are controls for setting a flag indicating that all pixels in one area have been sent to the PE. When this transmission end flag [kl is set, step S40→Step! The process advances to block S66 and below, and no transmission is performed to the area where this flag is set.

When the input queue is full and a NAK is received from the PE in step S52, as explained in connection with FIGS. 11A and 11B, 1 is incremented in step S80, and the NAK is returned in step S82. data to the next page
Send to H. In a loop of step S52→step S84→step S52, the same data is sent to the vacant PE.

The reason why PEs are not cycled until an ACK is returned is to prevent the input queue and output queue from becoming full and causing a deadlock.

Control bit=10 Data with control bit=10 is data including the results of image processing related to both the first and second embodiments. In step S4, send the ball to PE [1] and
When data is returned from [1], the process advances from step S6 to step S10 to check the control bit.

If the control bit = 10, the image memory is accessed at the address indicated by XYR (Fig. 14) of the reception buffer in step S12, and the data R is accessed in step S14.
is stored in the image memory 10.

It is the 12th A that proceeds from step S14 to step 566.
This is to maintain the relationship between the PE and the area described in connection with FIG. 12B.

Control bit = 11 This control bit = 11 data is request data requesting to send data of peripheral pixels.

If it is found in step S10 that the control bit≠11, the process advances to step S20, and the address
accesses the image memory in step S22, sends the image data at that address to the data S in the transmission buffer (Fig. 14), similarly sets the control bit S in the transmission buffer to 11, and in step S28 sets the control bit limit to 11. The selection sequence is returned to the source PE of No. 11. As explained in connection with FIG. 12B, since this response to the PE with control bit=11 is performed by an interrupt, an ACK is always returned from the interface control unit 12b (step 530).

As mentioned above, if control bit = 00 is set to 1 in PE,
When one central pixel is sent, requests for eight control bits=11 come in sequence from the PEs, and the R/W controller 11 returns information on peripheral pixels to each one in turn.

(Processing on the PE side according to the first embodiment) FIG. 15 is a flowchart showing a control procedure of the MPU according to the first embodiment. As described above, the program related to the MPU control procedure is loaded by the master CPU 20 into each MPU for each different image process. That is, when performing the image processing of the second embodiment, the program is loaded anew.

In the image processing of this first embodiment, processing of one pixel is performed using one P.
E will be in charge. In step S80, it waits for the data of control bit 200 to be stored in the manual queue. If even one of these data is entered, step S
82 and counter 32 (eighth) in step S84.
Figure A) counts down by one. In step S86, the image processing assigned to the MPU is performed on the memory address/image data pair just taken out. The image processing is, for example, color processing of a color image or γ conversion. This γ conversion converts the three components R and G of the pixel.

A matrix operation is performed on B (8 bits) and R' is obtained.

This is to convert into G' and B'. That is, the following processing is performed.

If the image processing is affine transformation, addresses will be subjected to matrix calculations instead of RGB image data. When the image processing is completed, it is checked in step S88 whether the output queue is full, and if there is space, the control bit is set to 10 in step S90, the output queue is loaded in step S92, and the counter 42 (number 1) is loaded in step S94. 8B) is incremented. The memory address/image data pair loaded into the output queue is eventually stored in the image memory 10 by the R/W controller 11.

<Effects of the first embodiment> Fig. 16A shows the sequence of image processing in units of one pixel by one PE in the conventional example. First, image data is read from the image memory 10 a), and processed by the MPU. (b), return the processed result to the image memory (C), and (a) and (b) above.

This is executed by repeating the cycle (C).

On the other hand, in the first embodiment when four MPUs are used, the 16th B
As shown in the figure, parallelism is increased to the limit processing capacity of the R/W controller, and performance improves in proportion. That is, ①: Conventionally, when multiple MPUs share one image memory, the image memory has only one input/output location, so each MPU must use it by time-sharing.
Therefore, it is necessary to use the same bus, and collisions occur. The ft/W controller 11 performs this traffic control and the waiting time is short.

(2) Normally, the time it takes to process an image in the MPU is much longer than the time it takes to input and output it to the image memory. Therefore, when using N PEs, if there is no waiting time for human output, N
The speed can be doubled.

(2): As a result, the R/W controller 11 frequently performs input/output between the image memory 10 and each PE, resulting in an extremely high usage rate.

<Processing on the PE side according to the second embodiment> The image processing procedure of the second embodiment on the PE side will be explained using FIG. 17 and subsequent figures. The image processing in this second embodiment is Laplacian processing having the matrix shown in FIG. In order to perform this process, the 18th A
Secure two calculation blocks of the same size as the Laplacian filter shown in the figure. As shown in FIG. 18B, there are two calculation blocks, a #1 calculation block and a #2 calculation block. One calculation block includes data consisting of information about one central pixel (control bit=OO) and information about eight peripheral pixels (control bit=11). The RAMI 4 is further provided with two transmission buffers (SB) for storing calculation results.

In order to manage the two calculation blocks and the transmission buffer, six flags as shown in FIG. 18B are used. These flags include the #1 busy flag, which indicates that the #1 calculation block is in use, and the #1 used flag, which indicates that the #1 calculation block is used.
The #IB full flag indicates that all 1 center pixel information and 8 peripheral pixel information are complete, and the #IS full flag indicates that the image processing of the #1 calculation block has been completed and the calculation results have been stored in the #ISB. be. The same applies to #2 calculation block.

First, the memory address/image data pair of the center pixel with control bit = 00 is retrieved from the manual queue #1.
The process from inputting to the calculation block to requesting information on eight peripheral pixels around the center pixel to the R/W controller 11 will be explained. At step 5100 in FIG. 19A, it is confirmed that the #1 calculation block is not in use, and the process proceeds to step 5102, where if the input queue is not empty, the input queue-calculation block subroutine is executed. In step 5200 of this subroutine in FIG. 19B, the center pixel information with control bit = 00 is stored from the input queue into the #1 calculation block, the counter 32 is decremented in step 5202, and the #1 calculation block is decremented in step 5204.
1 in use flag is set, and in step 5206, peripheral pixel addresses are calculated and the calculated address data is stored in the XY area of the #1 calculation block.

In step 3208, the XY of calculation block #2 is examined to find overlapping pixels (see FIG. 9).

At the initial stage, of course, there are no pixels that overlap with the #2 calculation block, but if consecutive Laplacian processing is performed on the #, 1 calculation block and the #2 calculation block one after another, overlapping pixels will inevitably appear. If there is a duplicate pixel, the image data of that pixel is copied in step 5210. By doing this, the R/W controller 1
The process becomes more efficient as it saves the time and effort required to make a request.

At this point, the #1 calculation block contains the memory address/image data pair of the center pixel (control bit = 0
0), the memory address/image data pair (control bits = 00, 11) duplicated from #2 calculation block, and the address of the pixel that requests image data to be sent to the R/W controller 11. are available. Furthermore, in step 5212, only the XY address is #1.
The control bit is set to 11 for those existing in the calculation block. In step 5216, the request presence flag is set and the process returns.

When the process returns to step 5106, it is confirmed that the output queue is not full, and the request data with control bit=11 is loaded into the output queue in the subroutine of step 3108. That is, in step 5220 of the request output queue subroutine of FIG. 19C, this request is loaded into the output queue, and step S
At step 222, the counter 42 (FIG. 8B) is incremented, and at step 5224 it is checked whether all requests have been loaded into the output queue. If all requests have been loaded, the request presence flag is reset at step 8226. From this subroutine, the process returns to step 5100.

In step 5100 of the next cycle, since the in-use flag is set, the process advances to step 5120. #IB full flag is not set yet, so step P12
Proceed to step 2 and check the request flag. Since this flag was set in step 5216, step 5124
The request output queue load subroutine is executed in step 5100, and the process returns to step 5100.

(,,Kera23...-,,fV2S 120-*,,
f”) 5122 → Step 5124 → Step 5tO
In a loop of 0, eventually all control bits = 1
1 request data is loaded into the output queue, and the request presence flag is reset in step 8226.

If the request presence flag is reset before all of the data in the #1 calculation block is collected, the process advances from step 5122 to step 5130 to check the usage status of the #2 calculation block. The procedure for storing data in the #2 calculation block is roughly the same as that for the #1 calculation block, so a description thereof will be omitted.

The R/W controller 11 sends the ball to the interface control unit, and the control bit = 1 from the output queue.
Receive 1 request. The R/W controller 11 sets the control bit to 1 according to the sequence described above.
1 is attached and the image data of the surrounding pixels is returned to the PE in a selecting sequence. Upon receiving this data, the interface control unit 12b interrupts the MPU. The interrupt routine is shown in Figure 19D.

Upon receiving the interrupt, the MPU retrieves the memory address/image data pair on bus 17 (step 5240).
, is stored in a vacant calculation block according to its memory address (step 5242). In step 5244, it is checked whether all the information on the surrounding pixels is complete, and if it is complete, the #IB full flag is set in step 5246.

Interrupts occur as many times as there are request queues stored in the output queue, and the #IB full flag is set.

While storing the information of the control bit 11 in the #1 calculation block by interrupt, step 5100 → step 5120 → step 5122 → step 5130
→ Step 5132 → Step 5134 → Step 51
In step 36, the request queue for #2 calculation block (control bit=11) is stored in the output queue and sent to the R/W controller 11. Then, as in the case of the #1 calculation block, the #2 calculation block is also filled with necessary data by an interrupt.

#IB full flag 5 flag or #2B full flag (or
both) are set, step 5152 (step 5
At step 140), an image processing subroutine is executed. The image processing subroutine is shown in FIG. 19E.

This image processing subroutine performs the Laplacian processing shown in FIG. If the filter element is a-th, and the image data of the center pixel after uIJ% processing of the image data of each pixel stored in the calculation block is vnffi, then v n, = Σ u n-1 + 凰, m-1 + J
' a IJIJs.

It is expressed as Steps 3170 to 5182 sequentially perform this matrix calculation. ,
When the calculation is completed, in step 3184, the memory address of the center pixel is stored in the XY area of the transmission buffer, and the calculated ■ is stored in the image data area of the transmission buffer, and in step 8186, image filling is completed and R/ The #IS full flag is set in the W controller 11 to indicate that it is ready for sending out via the output queue.

In step 5154 (step 5142), Rita 1 -
to check whether the output queue is full in order to output the calculation result to the output queue. If not full, step 5ts
6 (step 5146), the control bit of the transmission buffer is set to 10, and the result output queue load subroutine is executed. This subroutine is shown in FIG. 19F. If the output queue is full in step 5154 (step 5142), step 5100 → step 5
120 → step 5150 → step 5154 → step 5too loop, or step 5100 → step 5120 → step 5122 → step 5130 → step 5132 → step 8138 → step 5142
→ In the loop of step 5100, wait until the output queue becomes free.

In the result output queue load subroutine (FIG. 19F), the results are loaded into the output queue, and the in-use flag, S full flag, S full flag, etc. are reset.

Effects of the second embodiment> In addition to the effects of the first embodiment described above, the second embodiment has the following advantages. This assignment can be assigned to any PE if there is an empty P scale.
However, the R/W controller 11 side is freed from the trouble of allocation, and the R/W controller 11 achieves maximum processing speed.

02 Divide the image memory into areas equal to the number of PEs and loosely connect PEs in these areas on the route, and dynamically change the connection relationship as shown in Figure 11B even if the PE you want to send is not free. to maintain a loosely coupled relationship. By dividing into areas, the vertical connection relationship between the image memory and the PE becomes free.

(2): By maintaining the above-mentioned loose coupling relationship, consecutive pixels are sent to the same PE as much as possible, so there is no need for redundant images to be transferred over and over again on the bus.

Although the above description has been made using the two embodiments, various modifications thereof are possible. In particular, various modifications such as determining which task should be processed with highest priority on the PE side, replacing hardware with software, and vice versa are possible without departing from the spirit of the present invention.

[Effects of the Invention] As described above, according to the image parallel processing device of the present invention, one unit of image processing consisting of a plurality of pixels is processed as an input pair of a pixel address and image data, and a vacant processor is processed. Image processing is performed based on this address and image data, and the address and image data after image processing are also sent back as an output pair, so no matter which processor the above input pair is sent to, the image as a whole is Processing is performed reliably. Furthermore, the sender of the input pair is freed from the hassle of having to send the input pair to a specific processor, which makes parallel image processing more effective.
Processing becomes possible at high speed.

Furthermore, according to one embodiment of the present invention, the feature that when the memory for storing image data is divided into areas equal to the number of processors, the trouble of having to send the above-mentioned input pairs to a specific processor is relieved. While being maintained,
The continuity of pixels within the same divided area is preserved within the processor, further increasing processing efficiency.

[Brief explanation of drawings]

FIG. 1 is an overall block diagram of an embodiment to which the present invention is applied. FIG. 2 is a diagram showing the configuration of an image memory. FIGS. 3A to 3C are diagrams showing the format of data flowing on the bus. FIG. 5A and 5B are diagrams showing the transfer operation of the memory address/image data pair in the first embodiment and the second embodiment, respectively, FIG. 6 is a diagram showing the configuration of the R/W controller 11, FIG. 7 is a diagram showing the connection between the MPU and the queue buffer, and FIGS. 8A and 8B are diagrams showing the configurations of the input queue and output queue, respectively. , FIG. 9 is a diagram illustrating duplication of pixels within a block in the second embodiment, FIG. 10 is a diagram illustrating area division of the image memory, and FIGS. 11A and 11B are diagrams illustrating the second embodiment, respectively. In P
FIGS. 12A and 12B are diagrams illustrating how the correspondence relationship between E and area is changed, respectively, according to the first embodiment. Diagram 13 explaining the flow of data in the second embodiment
Figures A and 13B are flowcharts showing the control procedure of the R/W controller 11, Figure 14 is a diagram showing how the RAM of the R/W controller 11 is used, and Figure 15 is a flowchart showing the control procedure in MPLI. FIGS. 16A and 16B are timing charts comparing the conventional and this embodiment, FIG. 17 is a matrix diagram of the spatial filter used in the second embodiment, and FIGS. 18A and 18B are respectively , M in the second embodiment
Figures 19A to 19F, which are diagrams explaining how the RAM of the PU is used, are flowcharts showing the control procedure of the MPU in the second embodiment. In the figure, 10... Image memory, 11... R/W controller, 12-1 to 12-N... Queue buffer, 13-1
~13-N...MPU, 14-t~14-N, 19.
...RAM115...CRT controller, 16...
・Display device, 17, 18.50... bus, 20...
CPU, 51...MPU, 52...ROM, 53.
...RAM, 54...Bus interface, 30, 31
, 36.4O...AND gate, 32.42...Counter, 33.43...Decoder, 34.44...
Selector, 3-5.45...shift register. Figure 2 Figure 3A Figure 3B Figure 3C Figure 5A Figure 9 Figure 11A Figure 11B Figure 12A Figure 128 Figure 16A Figure 168 Figure 17 Figure 15 Old figure Figure Old B Figure 198 Figure 19E Figure 19F

Claims (4)

[Claims] (1) An image parallel processing device in which individual processors perform image processing in parallel with a plurality of pixels as one processing unit, comprising means for managing availability of each processor and completion of processing in each processor; Supply means for supplying, for each pixel of the processing unit, an input pair consisting of the image data of the pixel and the address of the input image space of this pixel to an unspecified free processor; and supplying the input pair of the one processing unit. A parallel image processing device characterized in that the processor processes the input pair of the one processing unit and returns an output pair obtained by adding an address of an output image space of the image data to the processed image data. . (2) The parallel image processing apparatus according to claim 1, wherein the image processing is spatial filtering processing. (3) When the supply means sends the input pair of one processing unit to the vacant processor, it sends the input pair multiple times, and sends the first input pair to the vacant processor, and the second and subsequent input pairs to the relevant processor. An image parallel processing device according to claim 1, characterized in that: (4) The supply means includes: a dividing means for dividing the memory for storing image data into areas equal to the number of processors; a combining means for combining each processing unit of each area with the processor; 2. The image parallel processing apparatus according to claim 1, further comprising a changing means for changing the connection relationship.