JPS63261874A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable the free writing and erasing of data, by a method wherein each output of a threshold circuit is connected independently to all inputs of the threshold circuit by a voltage modulation circuit. CONSTITUTION:By storing in a floating gate 74 electric charge corresponding to Tij, the resistance between a drain 72 and a source 71 is changed. When a voltage is applied to an output line 4 a selection transistor 8 turns ON, and a voltage supplied from a selection line 9 is modulated by the resistance of a transistor 7. A modulated current is supplied to an input line 3, and added to the current of the input line 3. Thus, the output line 4 and the input line 3 are coupled each other, and as the result, the input voltage is modulated. In the case where design is so made that the stored charge and the conductance between the source 71 and the drain 72 of the transistor 7 are proportional to each other, Tij can be designed in an analog manner by storing electric charge proportional to the value of Tij.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit configured as a device using a neural network model.

[Conventional technology]

One of the algorithms that uses neural network models is the one proposed by Hobfield (Proceedings of the National Academy of Sciences,
79, pp. 2554-2558 (1982), and vol. 81, pp. 3088-3092 (1984)).

The algorithm according to the above document will be explained next.

A processing element is called a neuron, borrowing the term from physiology, and a system in which N neurons are interconnected is considered. The connecting portion is called a synapse in physiological terminology, and the neuron i can have two states. That is, V
i=o and V,=1, and the i-th neuron is connected to the j-th neuron with a connection strength T i J.

Here, TiJ is a real number, and T+j=O represents that there is no bond. The state of the system at a certain moment is Vi
is characterized by N columns. That is, it is represented by an N-bit binary word. The above state changes over time according to the following algorithm.

That is, each neuron i has a certain threshold value U
, and each neuron calculates its own state at the next moment depending on whether the sum of the values of the states of neurons other than itself, weighted by the connection strength, exceeds that threshold or not. Determine the state.

Namely.

Σ TiJ VJ > Ui (1)
If j≠j, set v+=1, otherwise set v+=0.

T i J is represented by NXN matrices.

Memory can be created using the above algorithm. Store the information you want to store in n N-bit binary words V+
, s=1.2. ..., n, the coupling strength can be set as follows. n is the number of overwrites.

Here, simulations have shown that if n<0.15N, the above-mentioned system with TiJ has a stable state of 1. For example, when a word similar to V= or information about a part of vi is input into the memory, the system changes according to equation (1) and becomes steady at Vt. In other words, insufficient information can be corrected to bring it closer to complete information, and a content retrieval memory (content addressable memory, hereinafter referred to as CAM) can be configured.

Also, as is clear from equation (2), T + J is positive,
It can take either negative or 0 value, but if it is positive, it will be +1,
If it is negative, replace it with -1 and make T i J a matrix with +1.0 elements, but the accuracy will only slightly deteriorate,
The fact that it has the above-mentioned memory function is also shown by the memory loss.

A method of actually configuring the memory described above is shown in the above-mentioned document, volume 81, pages 3088-3092 (1984). In the above distribution method, wiring is formed in a lattice shape as shown in Figure 5, and T i J is defined by whether or not intersections (synapses) 1 are connected via resistance components 2. It is. The vertical wiring is the input line 3, and the horizontal wiring is the output line 4. *Since it is necessary to store both positive and negative voltages as TiJ, the output line 4 is connected to a threshold circuit 5 that outputs positive and negative voltages, and There are two for each neuron, corresponding to the outputs from 50. When connecting via a resistance component, one of the above two wires is selected. T
When i J = 1, it is connected to the upper side of each output 1iA4 pair, when T, j = -1, it is connected to the lower side of each output line 4 pair, and when T; J = O, each output line It is not connected to either of the pairs of 4. When connected to the upper side, the self or other input voltage is coupled, and when connected to the lower side, the self or other input voltage is inverted and coupled.

The operation of one neuron will be explained using a simple equivalent circuit shown in FIG. The input voltage ui of the threshold circuit 5 is determined by setting the input resistance 6 as ρi, the output voltage of another neuron as VJ, and the conductance of the connected part as TiJ−.
If the current input from the outside through the input line 3 is 1, then u i'' 9 i (ΣT+j(Vj-u;)+I
+) (3) Represented by j#i. That is, the self-input voltage is determined by adding the current obtained by multiplying the difference between each output voltage and the self-input voltage by the coupling coefficient to the current, and then multiplying it by the value of the resistor 6. Here, ρi is set so that ui is smaller than VJ.
By choosing ui”ρi(Σ TiJ VJ+
r! (4) It can be approximated as j≠i. 1. is introduced to determine the initial state, and may be set to O. The threshold circuit 5 compares the input ui with its own threshold value U, and finds that u H>U
; If so, output V, = 1; otherwise, output 0.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, it is not specifically specified how to realize the resistance coupling of the synapse portion. Also,
Since the threshold circuit 5 or 50 is arranged at the end of the grid wiring group, the output line 4 must be detoured to the end of the grid wiring group, which increases the wiring distance and slows down the operation speed. Moreover, there is a drawback that higher density is hindered due to the increase in area due to the detour wiring.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit that is capable of writing and reading data, has reduced delay time due to wiring, and is capable of high speed and high density.

[Means for solving problems]

The above object includes a plurality of threshold circuits and a plurality of voltage modulation circuits, and each output of the threshold circuit is independently connected to all the threshold inputs via the voltage modulation circuit. This is achieved by connecting to.

[For production]

The present invention constructs a device using Hobfield's algorithm on a semiconductor substrate using LSI technology, and uses an E"PROM type transistor with a floating gate as a resistive connection in the synapse part, which corresponds to a neuron. Threshold circuits are arranged on diagonal lines of the grid wiring group.In the conventional technique, the threshold circuits are arranged at the ends of the grid wiring group.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a synapse part in an embodiment of a semiconductor integrated circuit according to the present invention, FIG. 2 is a circuit diagram explaining a data writing method, and FIG. 3 is a circuit diagram explaining a data erasing method. FIG. 4 is a circuit diagram illustrating a neural network device according to the present invention.

FIG. 1 is a circuit diagram showing a synapse portion of an embodiment that best represents the features of the present invention, and the synapse portion includes a transistor 7 having a floating gate 74 and a selection transistor 8 connected in series. It is located in The source 71 and control gate 73 of the transistor 7 are connected to the input line 3, and the drain 72 is connected to the source 81 of the selection transistor 8. A drain 82 of the selection transistor 8 is connected to a line (referred to as a selection line Ω) 9 provided for selection, and a gate 83 is connected to the output line 4. A thin tunnel gate insulating film is provided between the drain 72 and the floating gate 74 to generate an electron tunneling current during programming.

The charge corresponding to T i J is transferred to the floating gate 74.
When stored in the drain 72 and source 71 due to the above charge,
The resistance between When a voltage is applied to the output line 4, the selection transistor 8 is turned on, and the voltage supplied from the selection line 9 is modulated by the resistance of the transistor 7.
A modulated current is supplied to the input line 3 and added to the current of the input line 3. (Normally, the resistance of transistor 8 is designed to be negligible compared to the resistance of transistor 7.) In the above manner, output line 4 and input line 3 are coupled, and as a result, the input voltage is modulated. . In this case, if the design is made so that the accumulated charge is proportional to the conductance between the source 71 and the drain 72 of the transistor 7, then by accumulating the charge proportional to the value of TiJ, T i J can be converted into analog It can be designed to However, it simply depends on the presence or absence of accumulated charge.

It is clear from what has been explained in the prior art section that simply turning on and off the transistor 7 (setting T iJ digitally) is effective.

If TiJ>O, the current 1 of input line 3 increases, and T
If + J < O, the current of input line 3 is 1. decreases.

T: For the portion related to the threshold voltage circuit 5 corresponding to J>O, an n-channel type transistor is used, and T5. The transistors in the portion related to the threshold circuit 50 corresponding to 0 are p-channel type, but the same effect can be obtained even if the polarity is reversed.

The specific operation is as shown below.

(a) When writing TtJ, the target input line 3 is grounded, the voltage V is applied to the output line 4, and the voltage V is applied to the selection line 9. The voltage V is the voltage at which the selection transistor 8 is turned on, and the voltage V is the voltage at which an appropriate tunnel current flows between the drain 72 and the floating gate 74. As a result, the floating gate 74
This means that electrons are extracted from the cell and positive charges are accumulated.

The above state is shown in FIG. 2, which shows a state where writing is about to be performed on the upper left transistor.

(b) When erasing Tej, voltage V is applied to the target input line 3, voltage V is applied to the output line 4, and the 1 selection line 9 is grounded. Electrons are injected into floating gate 74 from selection RfA 9 through selection transistor 8 . FIG. 3 shows the above state, in which the upper left transistor is about to be erased.

As above, N input lines 3 and 2N output lines 1
T i for all transistors placed at the intersection with 4
J information can be stored.

(c) Operation FIG. 4 shows an example of a circuit when N=4.

First, a binary word is input on input line 3 to determine the initial threshold circuit state. This voltage amplitude is V
, (binary values of o and v-), and the above value is a voltage such that the tunnel current to the floating gate 74 can be ignored. When the input is vo, the threshold circuit 5.5
0 to output line 4.4', an output voltage that turns on the selection transistor 8 (positive voltage on output line 4, negative voltage on output line 4') is obtained, and the initial state of the threshold circuit is is determined. At each synapse, if T+J>O, it is written to the upper floating gate, and if TrJ<O, it is written to the lower floating gate, both of which turn off the transistor 7. When T r J = 0, both the upper and lower transistors 7 are turned off. When the input is 0, the selection transistor 8 is kept off.

Next, the input line 3 is made floating, the operating voltage v0 is applied to all selection lines 9, and the operating voltage -vo is applied to all selection lines 9'. As a result, threshold circuits 5, 5
0 and the state of each synapse, the selection line 9
．． 9' is coupled to input line 3. If Tej>O, a positive current flows into the input line 3, and if T+J<O, a negative current flows into the input line 3, and the input voltage ui to the threshold circuit 5.50 is determined. Each threshold circuit 5.50 compares the input voltage ui with the threshold value U, and generates an output voltage on the output line 4.4' to turn on or off the selection transistor 8 again.

Depending on the state of the threshold circuit and the state of each synapse section, the current flowing into the input line 3 is further determined, and is returned to the input voltage to the threshold circuits 5 and 50. The output of any threshold circuit 5.50 is sent to another threshold circuit 5.5 through all the synapses connected to the output lines 4, 4'.
0 to the input line 3, so each threshold circuit 5.
50 performs the interaction through transistor coupling. The above interactions are sequentially repeated and a steady state (final state) is reached. The final state can be determined by the voltage on the output line 4.4'.

The circuit shown in FIG. 1 can be easily realized on a silicon substrate by the well-known E''FROM process.

Any device technology and process technology for E''FROM manufacturing can be applied to the present invention.

Next, a threshold circuit corresponding to that shown in FIG. 6 will be described. In this embodiment, as shown in FIG. 4, the threshold voltage circuit is arranged along one diagonal direction of the grid wiring. As is clear from the above equation (1), T++ may generally be set to O. Therefore, a threshold circuit 5 or 50 is placed in place of the synapse in the above portion. With the above configuration, compared to conventional technology, there is no need to route output lines, and the output lines can be made as short as possible, reducing the area required for wiring and shortening wiring delay time. I can do it,
This has the effect of realizing higher density and higher speed elements.

The circuit diagram of the neural network device shown in FIG. 4 uses the synapse structure explained in the first half of this example, but the way the neurons (neurons) are arranged in the threshold circuit has nothing to do with the synapse structure. It goes without saying that the above effects can be produced no matter what synaptic structure is used.

〔Effect of the invention〕

As described above, the semiconductor integrated circuit according to the present invention includes a plurality of threshold circuits and a plurality of modulation circuits including transistors having floating gates, and each output of the threshold circuit is connected to a voltage modulation circuit. By connecting all the inputs of the above threshold circuit independently, the synapse part of the neural network is constructed of transistors with floating gates, so data can be written and erased freely. In addition, since the neuron part is placed on the diagonal fffTl of the grid wiring that constitutes the synapse part, there is no need to draw the output line around, and the output line can be made as short as possible. This is because the area required for wiring can be reduced and the wiring delay time can be shortened.

This has the advantage of achieving higher density and higher speed elements.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a synapse part in an embodiment of a semiconductor integrated circuit according to the present invention, FIG. 2 is a circuit diagram explaining a data writing method, and FIG. 3 is a circuit diagram explaining a data erasing method. FIG. 4 is a circuit diagram showing a neural network device according to the present invention, FIG. 5 is a circuit diagram of a neural network device according to the prior art, and FIG. 6 is a diagram showing a part of the above circuit diagram in detail. 3...Input line 4,4'...Output line 5.
50... Threshold circuit 7.8... Transistor 9
...Selection line

Claims (1)

[Claims] 1. A plurality of threshold circuits and a plurality of voltage modulation circuits are provided, and each output of the threshold circuit is connected to all the threshold inputs via the voltage modulation circuit. Semiconductor integrated circuits each connected independently. 2. The semiconductor integrated circuit according to claim 1, wherein the voltage modulation circuit includes a transistor having a floating gate. 3. The threshold circuit is arranged along one diagonal direction of the lattice wiring network, and the voltage modulation circuit is arranged in a portion other than the one diagonal direction. A semiconductor integrated circuit as described in scope 1 or 2.