JPS63260082A - Floating gate type nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To remarkably reduce an ultraviolet ray incident amount by covering a first polycrystalline silicon layer through a thin oxide film with a second polycrystalline silicon layer, and connecting a second conductivity type impurity diffused layer to a metal layer to completely surround a PROM element including the second polycrystalline silicon layer. CONSTITUTION:A drain diffused layer 7 is connected by a contact 8 to a second polycrystalline silicon layer 16 to construct part of a drain signal line 6. A second polycrystalline silicon layer 17 forms part of a gate signal line 5. A PROM element is substantially completely surrounded by an N-type impurity diffused layer 2', and connected by contacts 18, 19 in the surrounded region to first polycrystalline silicon layers 13a, 13b. These first silicon layers cross over the defective part of the layer 2', which is covered through a second insulating film 14 of thin oxide films of the second layers 13a, 13b. The layer 2' is so connected to a source electrode 4 by a contact hole 3 as to completely surround the PROM element.

Description

DETAILED DESCRIPTION OF THE INVENTION [-Field of Application of Togami] The present invention relates to a floating gate type nonvolatile semiconductor memory device, and particularly to a redundant circuit used in a large-scale integrated EP.

[Conventional technology]

Traditionally, redundant circuits (
It is said that it is effective to use a defect relief circuit. Therefore, it is necessary to make the wiring connected to the defective area non-conductive.

There are various methods for this (for example, a method of cutting polycrystalline silicon wiring by passing a large current FE, a method of cutting by irradiating the wiring with a laser, etc.), but the first method for EPROM cell play is: From the viewpoint of process simplification, it is considered desirable to use nine PROM elements that do not erase immediately even when irradiated with ultraviolet rays.

A conventional technique of this kind will be explained using FIG. 5.

When ultraviolet rays propagate through the oxide film and reach the floating gate of the Pfl resistor in the redundant circuit, the program contents will be erased. Therefore, the cell area should be shielded from ultraviolet rays as much as possible (the drain gate should be To pull out the connecting wire,
It cannot be completely blocked. ) is the basic idea.

FIG. 5(a) is a plan view of a semiconductor chip showing the main parts of a conventional example (however, for convenience, the source 1! pole 104 in the top layer is shown with a broken line, and the diffusion layer is shaded). (b
) is a cross-sectional view taken along line A-A' of FIG. 5 (al).

The njJ impurity diffusion layer 2' connected to the PROM element (floating gate type MUD transistor) and the source diffusion layer has a partially missing part and is surrounded by an aluminum film (30,000 in the example shown) above the 280M element. - Covering, n-current impurity diffusion layer 2
’ by connecting with contact hole 3) upper and lateral 3
Blocks ultraviolet rays from entering the room. The aluminum film becomes the source electrode.

Gate signal line 5 (second layer polycrystalline silicon wiring) and drain signal line 6 (second layer polycrystalline silicon wiring connected to drain diffusion layer 7 through contact 8) are connected to the formation of n-type impurity diffusion layer 4. Pull it out from the missing part (lower blade in the figure) that is not attached.

It is limited to those that enter through the entrance and exit of the oxide film (that is, the portion where the R-type impurity diffusion layer is not formed with gold) and propagate through the oxide film. Naturally, the longer the propagation distance, the weaker the intensity of the 9 o'clock ultraviolet light will be when it reaches the PROM element, making it more difficult to erase. Moreover, the smaller the cross-sectional area of the oxide film in the part where the ultraviolet rays are incident, that is, T in FIG. 5(G). Roots with small X,
The amount of UV light that can enter is reduced, making the cell more difficult to erase.

[Problem that the invention seeks to solve]

The conventional floating gate type non-volatile semiconductor described above,
``''''PR, OM bare cheek extinguishing machine 6. When considering reducing the amount of ultraviolet rays incident from the entrance and exit of the drain signal line and gate signal line, is it necessary to reduce s Tox?・If the oxide film thickness of the entire play is reduced, the parasitic M(
JS) A problem arises in that the inversion voltage of the transistor decreases. Further, although it would be sufficient to reduce the oxide film thickness only at the entrance and exit portions of the drain signal line and gate signal line, there is no known means to achieve this without increasing the number of steps or complicating the manufacturing process.

[Means for solving problems]

The floating gate type nonvolatile semiconductor memory device of the present invention includes a memory cell matrix consisting of a memory transistor having a floating gate electrode and a control gate electrode, and a transistor t-PROM element of the same type as the memory transistor, on a first conductivity type semiconductor substrate. In a floating gate non-volatile semiconductor memory device in which a redundant circuit is integrated, a missing portion is provided directly below a gate signal line and a drain signal flA connected to a control gate electrode and a drain diffusion layer of the P-ROM element, respectively. a second conductivity type impurity diffusion layer surrounding the PROM element and connected to the source diffusion layer of the PROM element, and a first gate insulating film immediately below the floating gate in the missing part and in the vicinity thereof. A partial region of the gate signal line and a portion of the drain signal line are each formed of a first polycrystalline silicon layer having the same thickness as the floating gate electrode, and are provided through a first insulating film having the same thickness. and a second insulating film provided on the surface of each of these partial regions and having the same thickness as the second gate insulating film directly under the control gate electrode, and covering the first and second insulating films. a short-circuit prevention film made of a second polycrystalline silicon layer selectively provided at the same time as the control gate electrode; and an interlayer insulating film provided in parallel with the second conductivity type impurity diffusion layer. A metal film is provided, which is connected to the second conductivity type impurity diffusion layer and the short-circuit prevention film through contact holes, respectively, and covers the P-ROM element and its vicinity.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1(a) is a plan view of a semiconductor chip showing the main parts of the first embodiment of the present invention (for convenience, the uppermost metal film is shown with broken lines, and the diffusion layer is shown with diagonal lines). 1(b) is a sectional view taken along the line A-A'i in FIG. 1(a), and FIG.
FIG. 1 is a sectional view taken along line B-8' of FIG.

In this embodiment, a p-type well 51 is formed in an hp-type silicon substrate 50, a memory cell matrix is formed of a memory transistor having a floating gate 'ft@ and a control gate electrode, and a transistor 2PR, OM element of the same type as the aforementioned memory transistor. In a floating gate non-volatile semiconductor memory device in which a redundant circuit is integrated, a gate signal line 5 and a drain signal line 6 are connected to the control gate electrode l and drain diffusion layer 7 of the PROM element, respectively. an NFI impurity diffusion layer 2' having a cutout directly below and surrounding the PROM element and being connected to the source diffusion layer 2 of the PROM element;
A first insulating film 12 having the same thickness as the first gate insulating film (9) immediately below the floating gate is provided in the missing portion and the vicinity thereof, and the same thickness as the floating gate electrode is provided. A partial region 13a of the gate signal line and a partial region 13b of the drain signal line are made of the first polycrystalline silicon layer.
, a second insulating film 14 provided on the surface of each of these partial regions and having the same thickness as the second gate insulating film 11 directly under the control gate electrode l, and the first and second insulating films 12 . 1
A short-circuit prevention film 15 made of a second polycrystalline silicon layer is selectively provided covering the control gate electrode 1, and is formed simultaneously with the control gate electrode 1. each through contact holes of insulation $62
A metal film (4) is connected to the type impurity diffusion layer 2' and the short-circuit prevention film 15, and covers the above-mentioned PROM element and its vicinity.

That is, the drain diffusion layer 7 is connected to the second polycrystalline silicon layer 16 through the contact 8 and constitutes a part of the drain signal line 6. Similarly, 17 is a second polycrystalline silicon layer that constitutes a part of the gate signal line 5. A 280M element of the same type as a memory transistor 2 transistor is almost completely surrounded by an n-type impurity diffused layer 2', and 16.1
7 are connected to the first polycrystalline silicon layers 13a and 13b by contacts 18 and 19, respectively. These first polycrystalline silicon layers cross over the missing portions of the n-type impurity diffusion layer 2', and the second polycrystalline silicon layer 13 crosses over the missing portions of the n-type impurity diffusion layer 2'.
a, 13b as a second insulator 11111 which is a thin oxide film.
Covered through 4. And n-type impurity diffusion layer 2'
is connected to the source electrode 4 through the contact hole 3 so as to completely surround the PROM element.

In such a structure, as is clear from FIG. 1b), the incidence of ultraviolet rays at the entrances and exits of the drain signal line 6 and gate signal line 5 is caused by the first insulating film 1 made of a thin silicon oxide film.
This is possible only in the second and second insulating films 14, and the amount of incident ultraviolet rays can be dramatically reduced compared to the conventional structure.

Next, the manufacturing method of the present invention will be described.

2(a) to 2(f) are vertical cross-sectional views of semiconductor chips arranged in the order of steps for explaining the manufacturing method of the first embodiment of the present invention. ). Fig. 3 1! 3 to (f) are cross-sectional views of the semiconductor chip arranged in the order of steps for explaining the first embodiment of the present invention, and the final process is the same as Fig. 1 (b). become.

First, as shown in Fig. 2(a) and Fig. 3 ta>K, P
A P-type well 51 is formed on a part of the surface of a silicon substrate 50, and then a field oxide film 52 made of a thick silicon dioxide film is formed on a part of the surface by a normal selective oxidation method. A first insulating film 12 is provided to form a first gate insulating film and the like. Next, a first polycrystalline silicon layer 53 is formed and patterned using a vapor phase growth method or the like.

Next, as shown in FIGS. 2(b) and 3(b), a thin silicon oxide film 54 is formed by thermal oxidation, and a second polycrystalline silicon layer is formed by photolithography. The silicon oxide film 54 in the portions to be connected to the contact holes 55, 5 is removed.
6.57 shall be provided. 10 is a floating gate electrode of a PROM element, 13a is a partial region of a gate signal line, and 13b is a partial region of a drain signal line, all of which are formed of the first polycrystalline silicon layer.

Next, a second polycrystalline silicon layer 58 is formed (by a vapor phase growth method, etc.), and a thin silicon oxide film 59 is further formed by a thermal oxidation method.
form.

Next, as shown in FIGS. 2(C) and 3(C), a mask material 60 such as a photoresist that is difficult to be etched is selectively formed, and etching is performed using this as a mask. Next, as shown in FIGS. 2(d) and 3(d)K, the mask material 60 is removed, and a new mask material 61 is formed in the area where the first polycrystalline silicon layer is to be left. Remove patterning. At this time, in the area where the PROM element is to be formed, the silicon oxide film 59 serves as an etching-resistant mask, and the second polycrystalline silicon layer 58 is self-protected.
533 is patterned in alignment.

Next, as shown in FIG. 2(C) and FIG. 3(e), the mask material 61f (removed and thermally oxidized), the second insulating film 1
1. For example, arsenic ion implantation is performed to form a drain diffusion layer 7, a source diffusion layer 2, and an n-type impurity diffusion layer 2'.
form.

Next, as shown in FIG. 2(f) and FIG. 3(f), interlayer insulation 111I62 is formed, and contact holes 63a, 63b are formed.
.

After opening a hole and covering it with aluminum, patterning is performed to form a source electrode 4t.

FIG. 4(a) is a plan view of a semiconductor chip showing the main parts of the second embodiment of the present invention, and FIG. 4(b) is an A of FIG. 4(a).
-A' line sectional view.

80si, 80b, and 80c are portions (direct contacts) from which the oxide film is removed before forming the second polycrystalline silicon layer. As is clear from FIG. 4(b), in this embodiment, the train signal line 6. Since the cross-sectional area of the oxide film at the entrance and exit of the gate signal line 5 is further reduced, there is an advantage that the amount of incident ultraviolet rays can be further reduced. The reason is as follows.

Gate signal line5. Drain signal III! If there is an interlayer insulating film on top of 6 as in the conventional example, ultraviolet rays will easily enter, but if this is removed and a large contact hole is provided, the thin silicon oxide film on these signal lines will be exposed. Damage occurs and a short circuit occurs with the source electrode. However, if there is a short-circuit prevention film as in the present invention, there is no problem because the silicon oxide film mentioned above is protected when forming the contact hole.

This short-circuit prevention film is convenient because it does not allow ultraviolet rays to pass through.

It is clear from the above explanation that the present invention can be realized with the same number of processes as manufacturing a floating gate transistor. There are nine explanations for multiple PROs.
It is obvious that M elements may be provided without further detailed explanation.

〔Effect of the invention〕

As explained above, in the present invention 8A, the PROM element of the redundant circuit is surrounded by the source diffusion layer, and the drain signal line and the gate signal line are connected to the source diffusion layer by the first polycrystalline silicon layer. Pull it out across the impurity diffusion layer,
Further, in the traversing portion, the first polycrystalline silicon layer is covered with a second polycrystalline silicon layer through a thin oxide film, and the PROMi
By connecting the second fourth impurity diffusion layer and the metal layer so as to completely surround the element group or the P-BυM element group! ! >,
PROM element that can easily and stably reduce the cross-sectional area of the oxide film at the entrance and exit of the train signal line gate signal line and dramatically reduce the amount of incident ultraviolet rays, making it difficult to erase. This has the effect of improving the reliability of floating gate type nonvolatile semiconductor devices.

[Brief explanation of drawings]

FIG. 1 (al is a plan view of a semiconductor chip showing the main parts of the first embodiment of the present invention, FIG. 1 is a plan view of a semiconductor chip showing main parts of the first embodiment of the present invention, (C) shows cross section N along line BB' in Fig. 1(a), Fig. 2(a) to (f), and Fig. 3(
a) to (f) are process diagrams showing a vertical cross-sectional view and a cross-sectional view of a companion semiconductor chip, respectively, for explaining the manufacturing method of the first embodiment of the present invention, and FIG. FIG. 4(b) is a plan view of a semiconductor chip showing the main parts of the second embodiment.
is a sectional view taken along the line A-A' in Fig. 4(a), and Fig. 5(a) is
FIG. 5 is a plan view of a semiconductor chip showing the main parts of a conventional embodiment (bl is a cross-sectional view taken along the line AA' in FIG. 5(a). l... Control gate electrode, 2 ...Source diffusion no, 2'...N-type impurity diffusion layer, 3...
...Contact hole. 4...Source electrode, 5...Gate signal line, 6...Drain signal line, 7...Drain diffusion I, 8...・Contact, 9...
...First gate insulating film, °10...Floating gate electrode, 11...Second gate insulating film, 12
...First insulating film, 13a... Partial region of gate signal line, 13b... Partial region of drain signal line, 14... Second Insulating film% 15・
...Short circuit prevention film, 50...pffL/1
7=+N board, 51・old...pW Wael, 52...
...Field oxide film, 53a-53d...First polycrystalline silicon layer, 54...Silicon oxide film, 55-57...Contact hole, 58.
・Second polycrystalline silicon layer, 59...Thin silicon oxide [,60,61...Resist material, 62
・River.../M insulating film %63a, 63b...Contact hole. 13b Kuzu 3 figure 4th section, 5th figure

Claims (1)

[Claims] A floating gate type nonvolatile semiconductor in which a memory cell matrix consisting of a memory transistor having a floating gate electrode and a control gate electrode and a redundant circuit having a transistor of the same type as the memory transistor as a PROM element are integrated on a first conductivity type semiconductor substrate. In the storage device, the PROM element is surrounded by a missing part directly below the gate signal line and the drain signal line connected to the control gate electrode and the drain diffusion layer of the PROM element, respectively, and is connected to the source diffusion layer of the PROM element. a second conductivity type impurity diffusion layer provided in a connected manner, and a first insulating film having the same thickness as the first gate insulating film directly under the floating gate provided in the missing portion and its vicinity, respectively. , provided on the surface of each of the gate signal line partial region and the drain signal line partial region made of a first polycrystalline silicon layer having the same thickness as the floating gate electrode, and the control a second insulating film having the same thickness as the second gate insulating film directly under the gate electrode; and a second insulating film selectively provided to cover the first and second insulating films and formed at the same time as the control gate electrode. A short-circuit prevention film made of a second polycrystalline silicon layer and a contact hole of an interlayer insulating film provided in parallel with the second conductivity type impurity diffusion layer are connected to the second conductivity type impurity diffusion layer and the short circuit, respectively. A floating gate type nonvolatile semiconductor memory device, comprising a metal film connected to a prevention film and covering above the PROM element and its vicinity.