JPS63259896A - Memory cell and memory circuit - Google Patents

Abstract

PURPOSE:To read out plural addresses at one time by arranging plural transfer gates in parallel with each other and connecting different read address terminals to those transfer gates respectively. CONSTITUTION:A memory cell contains a read address terminal RA, a read data terminal RD, write data terminal the inverse of WD and WD, a write address terminal WA, a write enable terminal WE, inverters G11-G13, and the transfer gates Q11-Q15. In a data read state only the terminal RA is set at 'H' and the holding data on the terminal RD is outputted with inversion of bit. In a data write state the terminal WA is set at 'H' and one of both terminals the inverse of WD and WD is set at 'H' or 'L' together with the terminal WE set at 'H' respectively. Thus the data on the terminals the inverse of WD and WD are read. Then (n) pieces of such memory cells are gathered and a data writing circuit, a write address decoder and a read address decoder are provided in common to a group of said memory cells. Thus a memory circuit is formed.

Description

Detailed Description of the Invention [Field of Industrial Application] 5. The present invention relates to a memory cell and a memory circuit incorporating the memory cell.

[Conventional technology]

Conventionally, a memory cell of a memory circuit capable of simultaneous reading and writing has two inverters G31 . . . as shown in FIG. G
32 and four transfer gates Q31. Q32. G
33. G34, read ratio address terminal RA, write address terminal WA, read data terminals RD, π■, and write data terminals WD, WD. Also,
The memory circuit includes a plurality of memory cells R as shown in FIG.
M41. RM42. ~． RM4n and each memory cell RM
41. RM42. ~． RM4n read data terminal RD
, π■, respectively.
, RDL and read digit lines RDL, RDL, and has a precharge terminal PR.
and read circuit 42, memory cell RM41. R.M.
42, ~. A pair of write digit lines WDL, WDL connected to RM4n and write digit lines WDL, W
The write circuit 43 connected to DL and each memory cell RM
41, RM42, ~. A read address decoder 44 having read address outputs ARI, AR2, . . . , ARn connected to RM4n and write address outputs A, W1 . AW2, ~. It is composed of a write AT female decoder 45 having AWn.

In addition, the so-called 2 read/1 write RAM memory cell, which is a conventional memory circuit that can read two addresses at the same time and write to one address at the same time, has input/output in a closed loop as shown in Figure 10. Two constituent inverters G131 and G132 and these inverters G
Three each are provided on both sides of 131 and 0132.
(transfer network) Ql 31 to Q136.

Further, as shown in FIG. 11, a memory circuit using such memory cells includes a plurality of memory cells RMI 41"-RMI 4n as shown in FIG. 10, and a memory cell RM14.
two pairs of read-only digit lines RDIL, RDIL and RD2L, RD2L connected to 1 to RM14n;

Precharge circuit 1 connected to each of RD2L
48 and 149. Read circuits 142 and 143, a pair of write-only digit lines WDL and WDL connected to memory cells RMI41 to RMI4n, a write circuit 144 connected to these write-only digit lines WDL and WDL, and memory cell RMI41. ~RM1
A read address decoder circuit 45 corresponding to the first pair of read-only digit lines RD I L, RD I L and a read address decoder circuit 45 corresponding to the second pair of read-only digit lines RD2L, RD2L connected to It consists of a decoder circuit 146, a pair of write-only digit lines WDL, and a write address decoder circuit 147 corresponding to WDL.

[Problem that the invention seeks to solve]

The conventional memory cell described above and the memory circuit that can read and write at the same time using the same have a precharge circuit 4.
A memory circuit that requires 0 and can read from two addresses at the same time and write to one address at the same time also requires precharge circuits 148 and 149, and these precharge signals are generated in synchronization with the read address signal. There is a need. Further, during writing, it is necessary to apply an address enable signal AEN to the write address decoder 45.

Therefore, both in synchronous memory circuits in which these precharge signals are applied from outside the memory circuit, and in asynchronous memory circuits that have a precharge generation circuit inside the memory circuit, the timing margin of the precharge signals can be adjusted to the original value. The disadvantage is that the need to add to the memory access time increases the access time and limits high-speed operation of the memory circuit.

Furthermore, since it is necessary to apply an address enable signal to the write address decoder during the above-mentioned write operation, there is also the disadvantage that the circuit scale increases and the write time also increases.

[Means for solving problems]

The memory cell of the present invention has a read address terminal, a read data terminal, first and second write data terminals, a write address terminal, a write enable terminal, a first inverter, an input terminal, and an output terminal. a second inverter connected to the output end and the input end of the first inverter, respectively;
a third inverter having an input end connected to an output end of the first inverter; and a source having a source connected to an output end of the third inverter;
a first transfer gate whose drain is connected to the read data terminal and whose gate is connected to the read address terminal; a second transfer gate whose source is connected to the input terminal of the first inverter; a third transfer gate whose source is connected to the output terminal of the first inverter, whose drain is connected to the first write data terminal, and whose gate is connected to the output terminal of the first inverter;
, a fourth transfer gate connected to any one gate of the third transfer gate and the write address terminal, the source being connected to the drain of the fourth transfer gate, the drain being connected to the second write data terminal, the gate has a fifth transfer gate connected to the write enable terminal and the gate of any one of the second and third transfer gates to which the fourth transfer gate is not connected. Further, by using a plurality of transfer gates connected in parallel as the first transfer gate, it becomes possible to read a plurality of addresses at the same time.

The memory circuit of the present invention includes a read address terminal, a read data terminal, a second write data terminal, a write address terminal, a write enable terminal, a first inverter, an input terminal, and an output terminal. a second inverter connected to the output end and input end of the first inverter, respectively;
a third inverter having an input end connected to an output end of the first inverter; and a source having a source connected to an output end of the third inverter;
A first transfer gate whose drain is connected to the read data terminal and whose gate is connected to the read address terminal, a second transfer gate whose source is connected to the input terminal of the first inverter, and a second transfer gate whose source is connected to the input terminal of the first inverter. A third transfer gate whose drain is connected to the terminal connected to the first write terminal, and whose source is connected to the output terminal of the first inverter and whose gate is connected to the second terminal.
, a fourth transfer gate in which any of the third transfer gates is connected to one gate and a write address terminal, respectively, a source is connected to a drain of the fourth transfer gate, and a drain is connected to a second write data terminal,
A fifth transfer gate whose gate is connected to the write enable terminal and the gate of any one of the second and third transfer gates to which the fourth transfer gate is not connected.
a plurality of memory cells having transfer gates;
Read address information input to the read address input terminal, write address input terminal, read output terminal, write input terminal, write pulse terminal, and read address input terminal is decoded to determine the read address of any one memory cell. A read address decoder outputs a read address signal to a terminal, and a write address decoder decodes write address information input to a write address input terminal and outputs a write address signal to one of the write address terminal or write enable terminal of any one memory cell. a read digit line connected to the read data terminal of each memory cell, and a second write digit line connected to the first and second write data terminals of each memory cell, respectively. A write enable line connected to either one of the write enable terminals or write address terminals that do not input the write address signal of each memory cell, and a read digit line whose input end is connected to the read data terminal of each memory cell. a readout circuit whose output terminal is connected to the readout output terminal;
A first input terminal is connected to a write input terminal, an inverted output of write data input to the first input terminal is outputted to a first write digit line, and a non-inverted output is outputted to a second write digit line. , a write circuit whose second input terminal is connected to the write pulse terminal, and outputs the write pulse input to the write pulse terminal to the write enable line after the write address signal is output from the write address decoder. By using a plurality of transfer gates arranged in parallel as the first transfer gate and connecting different read address terminals to each gate, it becomes possible to read a plurality of addresses simultaneously.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of a memory cell according to the present invention.

In this embodiment, the read address terminal RA, the read data terminal RD, the first and second write data terminals WD, WD
, a write address terminal WA, a write enable terminal WE, a first inverter Gll, a second inverter G12 whose input terminal and output terminal are respectively connected to the output terminal and input terminal of the first inverter G11, a third inverter G13 whose input end is connected to the output end of the first inverter
-] 4-, a first transfer gate Q11 whose source is connected to the output terminal of the third inverter G13, whose drain is connected to the read data terminal RD, and whose gate is connected to the read address terminal RA; A second transfer gate Q12 connected to the input terminal of the inverter, and a third transfer gate Q13 whose source is connected to the second transfer gate Ql 20F drain and whose drain is connected to the first write data terminal WD. and a fourth transfer gate hQl whose source is connected to the output terminal of the first inverter Gll and whose gate is connected to the gate of the second transfer gate Ql2 and the write address terminal WA.
4 and a fifth transfer gate whose source is connected to the drain of the fourth transfer gate Q14, whose drain is connected to the second write data terminal WD, and whose gate is connected to the gate of the third transfer gate Q13 and the write enable terminal WE. (Age) Ql 5. Note that the transfer gate Ql of this embodiment 1. Ql 2. ....

Ql5 is an n-channel transistor.

The first and second inverters Gll and G12 hold data. The third inverter G13 is the read data terminal R
When the load on D is too large or when multiple memory cells are connected in parallel to the read digit line to which the first and second write data terminals WD and WD are connected, the read addresses of multiple memory cells may be changed at the same time. Terminal RA is at high level (
For example, the voltage is 5V), and it works so that the held data is not destroyed even if a so-called multi-select occurs. When reading data, when a high level is applied only to the read address terminal RA, the data held at the read data terminal RD is bit-checked and output. Furthermore, during data writing, the write address terminal WA becomes high level, and the eleventh second write data terminals WD, W
One of D becomes high level or low level, the other becomes the opposite level, and when the write enable terminal WE becomes high level, the first and second write data terminals WD
, WD data is read. In this manner, data is read from and written to the memory cell. Second
The figure is a configuration diagram showing a second embodiment of the memory cell of the present invention. In this embodiment, the gate of the fourth transfer gate Q14 of the first embodiment is transferred to the second transfer gate Ql.
The gate of the fifth transfer gate Q15 is connected to the gate of the third transfer gate Q13 instead of the gate of the second transfer gate Q13, and the gate of the fifth transfer gate Q15 is connected to the gate of the second transfer gate Q12. It is clear that it is the same.

In the first and second embodiments described above, the write address terminal WA and the write enable terminal WE have the same function, so the write address terminal WA is used as the write enable terminal WE, and the write enable terminal WE is used as the write address terminal WA. It is also clear that it can be used.

FIG. 3 is a block diagram showing a first embodiment of the memory cell circuit of the present invention.

This embodiment includes n memory cells shown in FIG.
These n memory cells RM21. RM22, -RM
an inverter G21 whose input terminal is connected to each of the read data terminals RD-17= and whose output terminal is connected to the read output terminal RDT, and an address input terminal RADO for reading read address information.

RAD1, -, RADm (tap n = 2m + 1), decoded and read address output terminals AR2, A
R2, -, ARn is set to high level, and memory cell RM21. A read address decoder 24 selects one of RM22゜..., RM2n, and a write address input terminal WADO, which inputs write address information.
WADI, ・.

It is input to WADm, decoded, and output to write address output terminals AWL, AW2 . . . , AWn is set to high level, and memory cells RM21°RM22 . ...
, RM2n, the input terminal is the write input terminal WDT, the output terminal is the first write data terminal WD of each memory cell,
Inverter G22 connected to each other via first write digit line WDL, and inverter G2 whose input end is
an inverter G23 whose output end is connected to the second write data terminal WD of each memory cell via the second write digit line WDL, and whose input end is connected to the write pulse terminal WP; Series-connected inverters G24 . . . , whose output ends are respectively connected to the write enable terminal WE of each memory cell. G25 and four inverters G22, G23. G24. Write circuit 23 consisting of G25
It is made up of. When reading data, the read address decoder 24 inputs the read address input terminal RAD.
O, RAD1. -, input the read address information to RADm, decode the input read address information and read the read address signal to the address output terminals ARI, AR2.
, . . . , ARn is output at a high level. Memory cells RMI, RM2 . . . . , RMn reads the held data and reads it out through the data terminal RD, read digit line RDL, and inverter G21 and outputs it to the read output terminal RDT.
Output to. At this time, since no write pulse is applied to the write pulse terminal WP, the write enable terminal W
E is at a low level, and memory cells RM21.E to which the write enable terminal WE is connected. RM22. -, RM2
4th and 5th transfer game of n)G14. Since G15 is open, the first and second write digit lines WDL, WDL are connected to memory cells RM21 .
RM22. -, the first and second inverters Gl of RM2n
l, separated from G12.

When writing data, the write address input terminals WADO, WAD1, ..., WA of the write address decoder 25
Write address information is input to Dm, the input write address information is decoded, and a write address signal is output to the write address output terminal AW1.

AW2. ..., Output at high level to one or more threads. In addition, the first and second write data terminals WD and WD of each memory cell include a write input terminal WD.
Based on the data input to T, a high level output is output to one side and a low level output is output to the other side via the first and second write digit lines WDL, WDL. After the high level output of the write address output terminals AWL, AW2, . G25. Write enable terminal WE via write enable line WEL
Outputs high level output. Therefore, the data on the first and second write data terminals WD, WD is transferred to the write address output terminal AWL at a high level at the write address terminal WA.
, AW2. . . , memory cell RM21 . . . to which the output of AWn is input. RM22. ....

First and second inverters Gl of RM2n 1. G12
is read and data writing is executed.

Therefore, the circuit configuration of this embodiment eliminates the need for a precharge circuit, and enables independent addressing for reading and writing, resulting in a high-speed asynchronous memory circuit that can perform reading and writing at the same time. I can actually say that. In addition, in this embodiment, the write address output terminal AW
L, AW2゜..., AWn, write enable WEL line to each memory cell RM21, RIv122, -,
Although they are connected to the write address terminal WA and write enable terminal WE of RM2n, respectively, it is clear that the connections may be reversed in each memory cell.

In the first embodiment of this memory circuit, an example is shown in which the number of words is n and the number of bits is 1.However, the number of words is n and the number of bits is 1. or more) read address output terminals ARI, AR2, . . . , ARn and write address output terminals AWL in parallel.

AW2. . . , AWn, it is clear that a memory circuit of n words×p bits can be constructed.

FIG. 4 is a circuit diagram of a memory cell according to a third embodiment of the present invention. This memory cell 111 includes first, second, and third inverters G111, G112, and G1]3, and first, second, third, fourth, fifth, sixth transfer gates Q111, G112 . G113. G1
14. Assume that it is made up of transistors G115 and G116 (n-channel MO8 for explanation). ), a first read data terminal RDI, a second read data terminal RD2, a first write data terminal WD, a second write data terminal WD, and a first read control terminal R.
AI, a second read control terminal RA2, a first write control terminal WE, and a second write control terminal WA. First and second inverter G11
1 and 0112 are data holding units. The third inverter G113 is activated when the load on the first read data terminal RDI and the second read data terminal RD2 is too large,
- Prevents the data held in the holding unit from being destroyed when a so-called address multi-select occurs in which the read control terminals of multiple memory cells connected to the same read digit line simultaneously reach a high level voltage (for example, 5V). This is a gate to prevent this. That is, since the cell according to this embodiment includes the third inverter G113, there is no need for precharging. First and second write control terminals WE and WA
are functionally equivalent, and when one is used as a write address terminal WA, the other is used as a write enable signal terminal WE. When the transfer gates Q111 to Q116 are made of n-channel MO8, if the gate electrode of each transfer gate Q111 to Q116 is at a high level voltage (for example, 5V), its source and drain are conductive, and when the gate electrode is at a low level voltage (for example, OV) If so, there will be no conduction.

FIG. 5 is a circuit diagram of a memory cell according to a fourth embodiment of the present invention. This memory cell 112 has first and second write control terminals WE and WA and a transfer gate Q.
The only difference is the connection relationship with the gates of Q113 to Q116, and the rest is the same as the memory cell according to the embodiment shown in FIG. 4, so a description thereof will be omitted.

FIG. 6 is a block diagram of a second embodiment of the memory circuit of the present invention. Memory cells RM121 to RM12n (n:
The number of memory words, 1, 2°..., n) is the fourth
This is the memory cell shown in the figure.

The first read data terminal RDI of each memory cell RM121 to RM12n is connected to the first read digit line RD.
It is connected to the readout circuit 122 via IT. The second read data terminal RD2 of each memory cell RM121 to RM12n is connected to the second read digit line RD2.
It is connected to the readout circuit 123 via L. Write data terminals WD and WD of each memory cell RMI21 to RM12n are connected to the first. Write circuit 1 via second write digit lines WDL and WDL.
24.

Further, the first write control terminal WE of each memory cell RMI 21 to RMI 2 n is connected to a write enable line W.
It is connected to the write circuit 124 via EL. Address decoding is performed by a well-known address decoder circuit 125,
126 and 127, the explanation of their logical operations will be omitted.

The address decoder circuit 125 is a first read address decoder circuit, and has first read address input terminals RI AD 1 to RI ADm (m is the number of address bits, and the number of memory words n mentioned above is n=2 The first read address output IARI decoded by inputting the first read address from
Output IARn (n: number of memory words). The decoded output IAR1 is connected to the first read control terminal RAI of the memory cell RM121, and the outputs IAR2 to IARn are sequentially connected to the memory cells RM122 to RM1.
2n RAI terminals, respectively.

The address decoder circuit 126 is a second read address decoder circuit, and the address decoder circuit 126 is a second read address decoder circuit.
Similarly, the second read address input terminal R2AD1
-Second read address output 2AR1-2 decoded by inputting the second read address from R2ADm
Output ARn (here n=2m). The decoded output 2ARI is connected to the second read control terminal RA2 of the memory cell RM121, and the output 2ARI is similarly connected to the second read control terminal RA2 of the memory cell RM121.
2-2 A Rn is memory cell RM122-RM12n
are connected to the RA2 terminals of each.

The address decoder circuit 127 is a write address decoder circuit, and is a write address input terminal WAD1.
~WADm (Similar to 125 and 126, m is the number of address bits and has a relationship of n-2'' with the number of memory words n), and the decoded write address outputs AW1 to AWn are input. (n: number of memory words).The decoded output AWL is output from the second write control terminal WA of the memory cell RM121.
The outputs WA2 to WAn are connected to the terminals, and the outputs WA2 to WAn
are connected to WA of memory cells RMI 22 to RMI 2 n, respectively.

Read circuits 122 and 123 are comprised of inverters in this embodiment, the outputs of which are connected to memory circuit read data terminals RDTI and RDT2, respectively.

The write circuit 124 includes four inverters 0123 to 0123G.
126, the memory circuit write data terminal WDT
The inputs of inverter G123 and G123 are connected, the output of inverter G123 is connected to the input of inverter G124 and the first write digit line WDL, and the output of inverter G124 is connected to the second write digit line WDL. Write pulse terminal WP is connected to the input of inverter G125, the output of inverter G125 is connected to the input of inverter 0126, and the output of inverter 0126 is connected to the second write digit line WEL. The operation will be explained as follows assuming that transfer gates Q111 to Q116 are n-channel MOS transistors. A read operation is always possible independently of a write operation, and the data held in the memory cell corresponding to the first address signal input to the first address input terminals RIADI to RIADm is connected to the first read digit line RDIL. The data is output to the memory circuit read data terminal RDT1 via the memory circuit.

Further, independently of the first address, the data held in the memory cell corresponding to the second address signal input to the second address input terminals R2AD1 to R2ADm is transmitted to the memory circuit via the second read digit line RD2L. It is output to the read data terminal RDT2.

In the memory circuit using the memory cell of the present invention, even if the first address and the second address address the same memory cell at the same time, no conflict or malfunction will occur.

Further, the write operation can be performed at any time independently of the two read operations, and the write address terminals WAD1 to
The data held in the memory cell corresponding to the address signal input to W A D m is rewritten to the data applied to the write data terminal WDT by applying a high level voltage (for example, 5V) to the write pulse terminal WP. However, the timing to apply a high level voltage to the write pulse terminal WP is based on the write address output AW1-AW.
It is necessary to apply it after the output voltage level of n is determined. Otherwise, data in memory cells that are not targeted for writing may be destroyed.

In this embodiment, the number of words is up to n words, but the number of bits is only 1 bit. However, by arranging the parts excluding the two read decoder circuits and the write 9 and decoder circuits in β pieces (ff=1°2.3...; number of memory bits), the result is the same as in the case of 1 bit. Needless to say, by connecting in parallel to the first read address outputs IARI to IARn, the second read address outputs 2AR1 to 2ARn, and the write address outputs AWL to AWn, an arbitrary memory circuit of n words x β bits can be constructed. stomach.

With the circuit configuration shown in this embodiment, a precharge circuit is not required in the memory circuit, and reading to two addresses and writing to one address can be performed independently, so a 2 read/1 write high speed asynchronous RAM can be used. It can be achieved.

FIG. 7 shows a memory circuit according to a third embodiment of the present invention,
Memory cells RMI21 to RM12n are the memory cells shown in FIG.

In this embodiment, except for using the memory cells shown in FIG. 5 for the memory cells RM121 to RM12n, the circuit configuration and circuit operation are otherwise exactly the same as the embodiment shown in FIG. The explanation will be omitted.

〔Effect of the invention〕

As explained above, the present invention has the effect that it is not affected by the wide read digit line by connecting the output terminal of the memory cell to the read data terminal via the inverter and not connecting it to the read digit line. , are connected to the first and second write data terminals through two series-connected transfer gates, and the gate of one of the two series-connected transfer gates is connected to the write address terminal, By connecting the gates of the other transfer gates to the write enable terminals, it is possible to realize a memory cell that can be read and written at the same time as required by Hong Kong Blinky.

The present invention also provides a plurality of memory cells and a read address decoder whose output terminals are connected to respective read and write address terminals of the memory cells and which respectively select memory cells corresponding to input read and write address information. By configuring a write address decoder, a write circuit that writes data to a memory cell, and a read circuit that connects a read data terminal to a read output terminal, the read circuit becomes simple and can be an inverter. This has the effect of realizing an asynchronous memory circuit with high-speed access time without performing a charging operation.

Furthermore, the present invention reduces the number of read digit lines to half of the conventional one by adding an inverter to the read section in addition to the memory cell holding section, and providing two read control signals and two write control signals. , 2 read/1 write (2 read/1 write) RA required for virtual cine
By realizing a memory cell for M and using that memory cell, it is possible to realize an asynchronous 2-read/1-write memory circuit with high-speed access time.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of a memory cell of the present invention. FIG. 2 is a circuit diagram showing a second embodiment of the memory cell of the present invention. FIG. 3 is a block diagram showing a first embodiment of the memory circuit of the present invention. FIG. 4 is a circuit diagram showing a third embodiment of the memory cell of the present invention. FIG. 5 is a circuit diagram showing a fourth embodiment of the memory cell of the present invention. FIG. 6 is a block diagram showing a second embodiment of the memory circuit of the present invention. FIG. 7 is a block diagram showing a third embodiment of the memory circuit of the present invention. FIG. 8 is a circuit diagram showing an example of a conventional memory cell. FIG. 9 is a block diagram showing an example of a conventional memory circuit. FIG. 10 is a circuit diagram showing another example of a conventional memory cell. FIG. 11 is a block diagram showing another example of a conventional memory circuit. RA...Read address terminal, RD...
Read data terminal, WD...first write data terminal, WD...second write data terminal, WA...
...Write address terminal, WE...Write enable terminal, 011-G15, 021-G25. Gl
11~G113.0121~G126. G131. G
132, G143. G144...Inverter circuit, Qll to Q15. Qllll~Ql 16. Q1
31~Q136. Q141-Q145...Transfer gate, RM21-RM2 n, RMl 21
~RM12n, RMI41~RM14n. 111.112,131...Memory cell, RD
T...Read output terminal, WDT...Write input terminal, WP...Write pulse terminal, 23
,124°144...Writing circuit, 122,1
23゜142.143... Readout circuit, 24
゜125.126,145,146...Read address decoder, 25,127,147...
・Write address decoder, RAD O, RAD 1・
.... RADm, RIAD1~RIADm, R2ADI~R2
ADm...Read address input terminal, ARl,
AR2,-, ARn, IAR1~IARn, 2AR1~
2ARn...Read address output terminal, WADO
, WADl, -, WADm- write address input terminal, AWI, AW2. .... AWn...Write address output terminal, WDL. WD, L...Write digit line, WEL...
...Write enable line, RDL...Read digit line.

Claims (4)

[Claims] (1) A read address terminal, a read data terminal, first and second write data terminals, a write address terminal, a write enable terminal, a first inverter, and an input terminal and an output terminal that are connected to the first inverter. a second inverter whose input terminal is connected to the output terminal of the first inverter, a third inverter whose input terminal is connected to the output terminal of the first inverter, and whose source is connected to the output terminal of the third inverter and whose drain is connected to the output terminal of the third inverter. a first transfer gate whose gate is connected to the read data terminal, a first transfer gate whose gate is connected to the read address terminal, and a source which is connected to the first transfer gate;
a second transfer gate whose source is connected to the input terminal of the inverter; a third transfer gate whose source is connected to the drain of the second transfer gate; a third transfer gate whose source is connected to the first write data terminal; A fourth transfer gate whose gate is connected to the output terminal of the first inverter and the write address terminal and the gate of one of the second and third transfer gates, and whose source is connected to the drain of the fourth transfer gate. a fifth transfer gate whose drain is connected to the second write data terminal and whose gate is connected to the write enable terminal and to the gate of any one of the second and third transfer gates to which the fourth transfer gate is not connected; A memory cell characterized in that it has a transfer gate. (2) The memory cell according to claim 1, wherein gates of the second and third transfer gates are connected to gates of the fourth and fifth transfer gates, respectively. (3) The memory cell according to claim 1, wherein the gates of the second and third transfer gates are connected to the gates of the fifth and fourth transfer gates, respectively. (4) The read address terminal, the read data terminal and the first
, a second write data terminal, a write address terminal,
a write enable terminal, a first inverter, an input end, and a second inverter whose output end is connected to the output end and input end of the first inverter, respectively, and whose input end is connected to the output end of the first inverter. a third inverter, whose source is connected to the output terminal of the third inverter, whose drain is connected to the read data terminal, and whose gate is connected to the read address terminal, and whose source is connected to the output terminal of the third inverter; a second transfer gate connected to the input terminal, a third transfer gate whose source is connected to the drain of the second transfer gate, a third transfer gate whose drain is connected to the first write data terminal, and a source connected to the first inverter. a fourth transfer gate whose gate is connected to the output terminal of the second transfer gate and the write address terminal, respectively;
The source is connected to the drain of the fourth transfer gate, the drain is connected to the second write data terminal, and the gate is connected to one of the second and third transfer gates to which the fourth transfer gate is not connected and write enable. a plurality of memory cells each having a fifth transfer gate connected to a terminal, a read address input terminal, a write address input terminal, a read output terminal, a write input terminal, a write pulse terminal, and a read address; A read address decoder decodes read address information input to an input terminal and outputs a read address signal to the read address terminal of any one memory cell, and a read address decoder decodes write address information input to a write address input terminal and outputs a read address signal to the read address terminal of any one memory cell. A write address decoder outputs a write address signal to either one of the write address terminal or write enable terminal of one memory cell, a read digit line connected to the read data terminal of each memory cell, and a read digit line connected to the read data terminal of each memory cell. 1. The first and second write digit lines are respectively connected to the second write data terminal, and the write enable terminal or write address terminal of each memory cell which does not input the write address signal is connected to the first and second write digit lines. a write enable line; a read circuit having an input end connected to the read data terminal of each memory cell via a read digit line; an output end connected to the read output terminal; and a first input end connected to the write input terminal. outputs the inverted output of the writing data input to the first input terminal to the first write digit line, outputs the non-inverted output to the second write digit line, and the second input terminal A memory circuit comprising a write circuit connected to a write pulse terminal and outputting a write pulse input to the write pulse terminal to a write enable line after a write address signal is output from a write address decoder.