JPS63259748A - Hierarchical storage control system - Google Patents

Abstract

PURPOSE:To lower the frequency of block cancellation without changing the decision system of block cancellation by means of flag by making a line length integer-times of a block length and preparing flags in WAA in such a number as equal to the number of blocks constituting the line. CONSTITUTION:A line which is the data transmission unit between an MS (main storage) 101 and a WS (intermediate storage) 102 is constituted of plural pieces of block that is the data transmission unit between the WS and a BS (buffer storage) 104. A flag showing to which CPU's BS the block in the line in the WS is being transmitted is provided for each one of the entries of the WAA (directory) 103. In the case of rewriting the data in the WS by means of a store request from the BS, the block in the BS represented by a flag is nullified. As a result, a line length can be made sufficiently long in comparison to a block length, therefore, the error rate of the WS can be lowered, and the degrading of performance due to block cancellation can be minimized.

Description

[Detailed description of the invention] [Industrial application field] The present invention provides a WS that stores a copy of an MS;

Directory that registers the main memory address of the copy.

It relates to a hierarchical storage device having a WAA that is a WS, and a BS that stores a copy of the WS, in particular a WS that is
This invention relates to a hierarchical storage control method that shares the following information. .

[Conventional technology]

A conventional device is disclosed in, for example, Japanese Patent Application Laid-Open No. 54-47531.

As described in BS (buffer memory) and WS.

The transfer units (blocks) between (intermediate buffer memory) and between WS and MS (main memory) are the same size,
The flag for each entry in WAA (directory) is W
All you need is the number of CPUs connected to S. (Figure 2 of the above-mentioned publication) In addition, the data requested by the CPU does not exist in the BS (hereinafter referred to as NlB5), and the WS
(hereinafter referred to as NIWS), data is transferred from the MS to the WS (hereinafter referred to as LT).
Data is transferred from S to BS (hereinafter referred to as BT).

Or, data exists in BS and WS.

When writing to the BS, writing is also performed to the WS using store-through. At this time, since the contents of WS and BS match, the flag of the WAA entry is set.

Examine the bits and correspond to flag bits that are "1".

A block cancellation request is sent to the BS of the CPU.

vinegar. (However, for the CPU that stores the BS.

will not be canceled) while this request is being processed.

Raikou's CPU has guaranteed data on programming.

Therefore, serialization must be performed.

I have to interrupt the pipeline process.

stomach. Therefore, in order not to degrade performance, it is necessary to use a professional.

It is necessary to reduce the frequency of tsukucancellation requests. .

For that purpose, NIWS for NlB5.

The probability must be reduced. cache memo.

Regarding the correlation between the error rate and block length of
As discussed on pages 540 to 541, when the capacity is held constant and the block length is increased, there is a point at which the miss rate becomes the lowest. WSO has a larger capacity than general KBS, and as mentioned above.

The paper states that this processor has the lowest error rate because it can increase N (number of blocks).

The length can be increased. However, as mentioned above.

In the known example, both the BS and WS have long registration units.

Since the lock length and line length are made equal, the W5S miss rate is not optimized.

HLTACM is another conventional technique that guarantees correspondence with a BS when a WS is shared by multiple CPUs.

F A A (Front
Addrgsz.

There is an Array) method. This is a copy of BAA, which is a directory of addresses registered with B51y.

It has FAA as a memory control unit and other CPUs.

Not WAA for writes from I/O devices.

Access the FAA and determine block cancellation.

It is something to do. If this method is used, there is no need for the 15 data in the BS to always be in the WS.
Even if a transfer of data to S) occurs, block cancellation does not occur. However, there is a drawback that the amount of materials increased by the FAA is significant.

[Problem that the invention seeks to solve]

, 3.

The above conventional technology has a low block cancellation frequency.

Arrangements for block lengths of BS and WS for reduction.

No consideration was given to the block length (line) of the WS.

length) is made larger than the block length of the BS.

There was a problem that the NIWS rate was higher than that of the previous version, and that the performance of other CPUs was degraded due to the block scan. Book.

The purpose of the invention is to improve the performance of conventional WAA flags.

6WS without changing the tough cancel judgment method
of block cancellation.

The purpose is to provide a means to reduce the frequency. 1. .

[Means for solving problems] In the present invention, the line length is an integral multiple of the block length.

If the block length (line length) is expanded to minimize the miss rate relative to the capacity of the WS.

Both of these can be achieved by preparing flags indicating that the data has been transferred to the BS within the WAA for the number of blocks constituting the line.

[Effect]

The line length, which is the registration unit of WS, is 2 of the BS professional 9 length.
When doubled, according to the prior art paper, 4.

For example, the WS miss rate is approximately 1/2. At this time, one line consists of two blocks, and the number of bits of the flag indicating whether or not a block is to be transferred to each CPU in the WAA entry is 2X the number of CPUs. N.

The data that became IBS was 5°N as a result of WAA access.
If it is determined to be IWS, W is replaced.

The WAA flag bit corresponding to the S entry is:

It corresponds to a block that divides the line into upper and lower parts.

Check whether the 2 pictograms shown are 0 and 1 stands.

issue a block cancellation request. As stated above.

As shown above, the number of bits in WAA- is multiplied by the number of blocks, but the frequency of block cancellation is 1/V.

bawl.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. Each C
If the instruction or data does not exist in the BS 104 when the PU (CPUo, 1...rL) accesses the instruction or data (in the case of NI BS), a request to transfer the block containing the data is issued to the WS. . The transfer request is accompanied by the address of the data and is accessed by the WAA 105 car. If WAA does not have an address (N.

(In the case of IWS) A request is made to MSlol to transfer a line containing a block containing data. line.

Data W read from the MS by transfer (■, T).

The determination of which row of S to register is made by the replacement array WRA115iC of the WS. this.

In the I,RU method, the row containing the oldest data is scanned.

This is a pointer array that is selected as a target for Watsuzu. .

There are cases where WS data is replaced by LT.

If the BS data is rewritten and stored, Il1
Since it is a formula, the corresponding data in WS must also be rewritten.

There may be cases where the data is rewritten.

Examine the flag bits in the WAA entry and check the flag bits.

Proc cache for BS whose lag bit is 1.

issue a cancel request. FIG. 2 shows the contents of WAA entry 0. The WAA entry consists of an intra-WAA address that is higher than the line address registered in the LT, other control information 110, and a flag bit 112 indicating whether or not a block is to be transferred to the BS. In the example shown in FIG.
Transferred to S, Upper Near'.

That lock 106 has been transferred to CPU n's BS.

It shows. At this time, as shown in Figure 2, the CPU is 0°1,
Flag bits 112, 113 and corresponding to n.

114c, corresponding to lower block and upper block.

and is set. Here, the construction shown in Figure 2 of WS.

The line registered in the entry is selected for swap.

WAA entry for this line.

The flag bits of CPUo,1,n are examined and the bits of
.

A lock cancellation request is issued. Also from WS.

Overwriting in the BS when a block transfer is performed to the BS.

of the WAA entry corresponding to the block being written.

The flag is reset from 1 to 0.

Figure 3 shows the WAA search and Hi T determination circuit.
are doing. 601 is an address (real address) associated with a line transfer request from the WS, 302 is a WS replacement array (WRA), WAA, WSO column address, 3Ω3 is a block select pin indicating whether the block is upper or lower on the line) , 3047.

- is WS replacement array (WftA), 30
5 is the WAA entry flag bit, 606 is WEL
・Low that decodes and replaces the output of A304・
A decoder 507 determines the flag bit corresponding to the block in the line as a block select period.

The selector 506 selects, and the selector 308 selects the real address.

A connection between the upper address and the WAA address.

509 is the address within WAA of the WAA entry.

This is a selector that selects the bits and flags. W.

When writing a line with 5KLT, the upper address 3Q1 and WAA of the data transfer request address from the BS.

The internal addresses are compared by a comparator 308. W.

FLA is accessed using the same column address as WAA.

The row containing the oldest data in the BS is decoded.

- output by da. If even one of the comparator outputs has a matching output, it is determined that a bit has been generated.

The circuit 510 makes the determination. WA if there is no matching output.

The 40-minute intra-WAA address read from A.

The selector 309 selects the row selected by the WRA decoding result from among the flags. Was chosen. .

, 8.

Address within WAA and power when accessing WAA.

RAM address, as well as block select bits.

and its lower 1 bit is a block cancellation request.

This is the address of the time. Selected flag bit.

A process request signal is issued to the CPU corresponding to the bit set to 1.

〔Effect of the invention〕

According to the invention, line length to block length.

WS's mistake because it can be made large enough.

WS, which occurs when swapping WS, can reduce the rate.

and block cancellation to guarantee BS matching.

This has the effect of reducing performance deterioration caused by

[Brief explanation of drawings]

FIG. 1 is a diagram showing an outline of an embodiment of the present invention. Figure 2 shows the WAA end of the WS directory. FIG. 3 is a diagram illustrating the WAA search and HLT determination circuit. 104...Buffer memory, 102...Intermediate memory, 1
03゜305...Intermediate storage address array, 112
, 504... intermediate storage replacement array, 10
1... Main memory. 111, 305,...flag bit, 11o...
WAA address, 109, 302...column address, 3o6..., deco. - da, 307, 309... selector, 308...
・Con Valley. the law of nature. 11゜Meru Qνl CF/J7 Cr
U7 in February

Claims (1)

[Claims] 1. A plurality of BSs (buffer memories) and an MS (main memory) provided corresponding to a plurality of CPUs (central processing units);
In a hierarchical storage control device that has a WS (intermediate storage) provided between these, and a directory (WAA) in which the main storage address of data is registered when writing a copy of the MS to the WS, A line, which is a unit of data transfer, is configured to consist of a plurality of blocks between a WS and a BS, and a flag indicating which CPU's BS a block in a line in the WS is transferred to is transferred to the WAA. 1. A hierarchical storage control system, wherein each entry has a flag bit, and when data in the WS is rewritten by a store request from a BS, a block in the BS in which the flag bit is set is invalidated.