JPS63257468A - Inverter abnormality indication circuit - Google Patents

Inverter abnormality indication circuit

Info

Publication number
JPS63257468A
JPS63257468A JP62087971A JP8797187A JPS63257468A JP S63257468 A JPS63257468 A JP S63257468A JP 62087971 A JP62087971 A JP 62087971A JP 8797187 A JP8797187 A JP 8797187A JP S63257468 A JPS63257468 A JP S63257468A
Authority
JP
Japan
Prior art keywords
circuit
inverter
abnormality
contents
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62087971A
Other languages
Japanese (ja)
Inventor
Hiromi Saito
斎藤 浩美
Masahiko Iwasaki
岩崎 政彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62087971A priority Critical patent/JPS63257468A/en
Publication of JPS63257468A publication Critical patent/JPS63257468A/en
Pending legal-status Critical Current

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  • Power Conversion In General (AREA)
  • Inverter Devices (AREA)

Abstract

PURPOSE:To subject the contents of abnormality to hysteresis treatment by incorporating said contents of abnormality in a writable, erasable and preservable storage means and by indicating them with an indicating means. CONSTITUTION:An inverter apparatus drives a load motor 4 from AC power via a converter circuit 2 and an inverter circuit 3. This abnormality indication circuit is composed of an over-voltage detection circuit 5, a base driving circuit 6, an overcurrent detection circuit 7, and a control circuit 101 by an arithmetic circuit 8 and others. Also, said indication circuit is equipped with a paging system 13 and a storage element 14, and said paging system 13 has display units 22, 23 of figures and the like with light-emitting elements to indicate arbitrary contents other than command operation frequencies by said light- emitting elements. Further, said storage element 14 preserves contents written in the arithmetic circuit 8 even after an inverter power has disappeared by the breaking of a switch 1A and reads out said contents after the recovery of power. Thus, it is made possible to determine the abnormalities of said inverter occurring in the past.

Description

【発明の詳細な説明】 〔趣粟上の利用分野〕 この発明は、インバータの異常時にその異常を示す表示
回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application] The present invention relates to a display circuit that indicates an abnormality when an inverter is abnormal.

〔従来の技術〕[Conventional technology]

従来の異常表示回路の′Ps成を第5図1で示す。図に
おいて、(1)は父流W源、(I人月j操作スイ・・・
チ(コンタクタの接点)、(2)は交流を血流Cζ変換
スるコンバータに路(順変m器)、(3)はインバータ
回路、(4)はインバータの負荷であるモータ、(5)
は過電圧検出回路、(6)はペース駆動回路、(7A月
J市流検出器、(7)は過電流検出回路、(8)は演算
回路、(9)は運転指令装置、QGは過電圧異常発生を
示す発光素子、αυは過電流異常発生を示す発光素子?
ある。以上(5)〜圓をまとめて制御回路Cl0L)と
して示している。ま1こ、■は制御回路用の電源である
The 'Ps configuration of a conventional abnormality display circuit is shown in FIG. In the figure, (1) is the father's flow W source, (I person month j operation switch...
(2) is a converter that converts alternating current into blood flow (Cζ), (3) is an inverter circuit, (4) is a motor that is the load of the inverter, (5)
is overvoltage detection circuit, (6) is pace drive circuit, (7A month J market flow detector, (7) is overcurrent detection circuit, (8) is arithmetic circuit, (9) is operation command device, QG is overvoltage abnormality Is αυ the light emitting element that indicates the occurrence of an overcurrent abnormality?
be. The above (5) to circle are collectively shown as a control circuit Cl0L). 1 and 2 are power supplies for the control circuit.

6′に動作について説明する。The operation will be explained in 6'.

(1)の市酋はコンバータ(2)により血流に変換され
1こ後、運転指令装fi!(9)により出力周波数指令
か設定されると、演算回路(3)は、この周波数指令の
設定になめらかに追従するべく、インバータ出力周波数
を計算しこの周波数を満1こす各スイ・リチング素子(
3)のオン、オフ信号を作り出す。この信号はベース駆
動回路(6)を通して、インバータ回路(3)の各スイ
ー’Jチング素子lζ送られオン、オフ動作によりコン
バータ[回路(2)の整流Cζより作られr、:血流力
)ら新1こな交流を作り出し負荷(4)fζ供給する。
The blood flow in (1) is converted into blood flow by the converter (2), and after that, the driving command device fi! When the output frequency command is set by (9), the arithmetic circuit (3) calculates the inverter output frequency in order to smoothly follow the setting of this frequency command, and each switching element (
3) Generate on/off signals. This signal is sent to each sweeping element lζ of the inverter circuit (3) through the base drive circuit (6), and is turned on and off by the converter [reduced by the rectification Cζ of circuit (2): blood flow force]. A new alternating current is created and a load (4) fζ is supplied.

次1ζ異常が表示される過程を説明する。Next, the process by which the 1ζ anomaly is displayed will be explained.

例えば、インバータが動作中に、負荷の増大により出力
電流が多くなりrことする。出カシ流は電流検出器(7
AJによr′17g時検出しており、上記の如く出力電
流が所定値以上6ζなると過電圧検出回路(7)が動作
する。この信号を受けて演算回路(3)は、運転指令を
無視しインバータ回路(3)の各スイ・ツチング素子の
出力を停止し、インバータ回路(3)のスイ・リチング
素子が破壊に至るのを防ぐと共ζζ発光素子α1)を点
灯し過電流異常があったことをユーザーに対し示すよう
にしている。l′i¥1様にして、インバー タ44t
x中に負m(4)からの回主により、コンバータ回路(
2)−インバータ回路(3)間の直流電圧が所定値以上
になりrコ場合には過電圧検出回路(5)が動作して、
演算回路(3)はインバータ回路(3)の各スイ、リチ
ング素子のオン、オフ信号を停止し、素子破壊に至るの
を防ぐと共に過電圧異常発生を示す発光素子GOを点灯
し過電圧異常P#Eを示すようにしている。ま1こ、演
算回路(8)からは上記異常発生と共に出力される信号
を操作スイ、ツチ(7A)へ接続し、異常発生時にスイ
ー・チ(IA)を開くようにしてコンバータ回路(2)
〜インバータ回路(3)がHIMfるのを防ぐようにし
ている8、 〔発明がm決しようとする問題点〕 従来の異常を示す表示回路は、以上のように構成されて
いるので、インバータの市#をオフし1ことき、および
異常を解除し1こときの後は異常内容の記録が残らず、
過去に発圧し1こ異常については知ることができない。
For example, while an inverter is operating, the output current increases due to an increase in load. The output current is measured by a current detector (7
AJ detects when r'17g, and as mentioned above, when the output current exceeds a predetermined value 6ζ, the overvoltage detection circuit (7) operates. Upon receiving this signal, the arithmetic circuit (3) ignores the operation command and stops the output of each switching element of the inverter circuit (3) to prevent the switching element of the inverter circuit (3) from being destroyed. If this is prevented, the ζζ light emitting element α1) is turned on to indicate to the user that an overcurrent abnormality has occurred. l'i ¥1, inverter 44t
The converter circuit (
2) If the DC voltage between the inverter circuit (3) and the inverter circuit (3) exceeds a predetermined value, the overvoltage detection circuit (5) operates,
The arithmetic circuit (3) stops the ON and OFF signals of each switch and recessing element of the inverter circuit (3) to prevent element destruction and turns on the light emitting element GO which indicates the occurrence of an overvoltage abnormality P#E. I am trying to show this. First, the signal outputted from the arithmetic circuit (8) when the above abnormality occurs is connected to the operation switch (7A), and the switch (IA) is opened when an abnormality occurs, thereby converting the converter circuit (2).
~ Trying to prevent the inverter circuit (3) from becoming HIMf8. [Problems that the invention attempts to resolve] The conventional display circuit for indicating an abnormality is configured as described above, so that the inverter circuit (3) After turning off the city number and canceling the error, no record of the abnormality will be left.
It is not possible to know about abnormalities caused by pressure generation in the past.

まTこ、第5図のように異常発生と同時にスイ・Iチ(
IA)ケ開くようなシーケンスの場合には、スイー・チ
オフと共に表示が消失するので、異常になつfこ原因を
知ることができないという問題があっrこ。
As shown in Figure 5, when an abnormality occurs, the switch (
IA) In the case of a sequence that opens, the display disappears with the switch-off, so there is a problem in that it is impossible to know the cause of the abnormality.

この発明は上記のような不具合を解消する1こめになさ
れ1こもので、過去に発生じたインバータの異常を知る
ことのできるインバータの異常表示装fitを得ること
を目的とする。
The present invention is an all-in-one effort to eliminate the above-mentioned problems, and an object of the present invention is to provide an inverter abnormality display device that allows users to know about inverter abnormalities that have occurred in the past.

〔問題点を解決する1こめの手段〕 この発明に係るインバータの異常表示回路は、インバー
タの異常を記憶する、書き込み消去が可能で力)つイン
バータへの電力しゃ断時1ども記憶内容を保持する記憶
手段と、この記憶手段に記憶され1こ内容を表示する記
憶手段と、この記憶手段に記憶され1こ内容を表示する
手段を設け1こものである。
[First Means to Solve the Problem] The inverter abnormality display circuit according to the present invention stores the inverter abnormality, is writeable and erasable, and retains the stored contents even when the power to the inverter is cut off. The apparatus comprises a storage means, a storage means for displaying the contents stored in the storage means, and a means for displaying the contents stored in the storage means.

〔作用〕[Effect]

この発明におけるインバータの異常表示回路は、異常の
内容が記憶手段に格納されているので、市fIA遍断し
、異常を解除【、1コ後も記憶手段に格納され1こ異常
の内容は消去されず、必要に応じて過去の異常を読み出
し表示することができる。
In the inverter abnormality display circuit according to the present invention, since the contents of the abnormality are stored in the storage means, the contents of the abnormality are stored in the storage means even after 1 time, and the contents of the abnormality are erased. If necessary, past abnormalities can be read out and displayed.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例を第1図〜第4図を用いて説
明する。第1図において、(1)〜(81,a2は第5
図と同一のものである。(至)は、運転指令装置で、第
5図の運転指令装f!i (9)と同一の役割を果1こ
すほかに発光素子による数字、および文字の表示装置(
イ)翰も合わせ持っている。従って制御回路用市flA
a2より、指令する運転周波数の他に任意の内容を発光
素子を用いて表示することができる。Q41は記憶素子
で、電気的に書き込み消去が自由にできかつ、保持1[
1を必要とせずに、内容を保存することができる記憶素
子、即ちEEP−1tUM(E−11ectrical
ly Eraseahlp  kLend  only
Memory)により構成されている。従ってインバー
タが動作中に演算回路(8)より書き込まれ1こ内容は
、スイーIチ(IA)のしゃ断によりインバータの市酋
が消失した後でも保存されており、復電後演算回路(8
)を通し、内容を読み出すことができる。
An embodiment of the present invention will be described below with reference to FIGS. 1 to 4. In FIG. 1, (1) to (81, a2 are the fifth
It is the same as the figure. (To) is a driving command device, and the driving command device f! of FIG. In addition to playing the same role as i (9), it is also a device for displaying numbers and letters using light emitting elements (
b) He also has a sword. Therefore, the city flA for the control circuit
From a2, any content other than the commanded operating frequency can be displayed using the light emitting element. Q41 is a memory element that can be electrically written and erased freely and has a storage capacity of 1[
A memory element that can store contents without the need for an EEP-1tUM (E-11 electrical
ly Eraseahlp kLend only
Memory). Therefore, the contents written by the arithmetic circuit (8) while the inverter is operating are saved even after the inverter's power is lost due to switching off of the switch (IA), and after the power is restored, the contents of the arithmetic circuit (8) are saved.
), the contents can be read out.

動作について説明する。(1)〜(3)の回路動作の後
、運転指令装置1lto3のキー人力にまり周e数設定
かなされて、演算回路(8)、ベース駆動回路(6)の
回路を通しインバータ回路(3)の素子のオン、オフζ
どよりパワーがインバータ(4)へ供給される過程は従
来回路と同一なので、説明は省略する。ここでは異常が
発生し、その内容を、記憶素子α4へ記憶する方法を説
明する。第5図のものと同様に9荷の増大により出力筆
圧か大きくなり1ことする。電流が所定値を超えZ・と
過電流検出回路(7]が動作し、演算回路(8)へ異常
出力信号を伝達する。演算回路(8)は伝達されγこ信
号より異常の内容を判別し、記憶素子α4へ記号(一般
的には数字)として瞬時に格納する。記憶素子側は才気
的に書き込み消去が可能で、かつ保持電力がなくても記
憶内容は保持可能な1こめ図に示すようlζ漬算回路(
8)力)らの異常発生信号出力にまり異常と同時に、コ
ンタクタ(IA)を開放しM制御Wtlflμsがなく
なるような場合Cζおいても、記、憶素子u4の内容は
保持用npである。従って寧#を再投入の後に運転指令
装置o3へ、記憶素子α4の内容を表示できろようにし
てあり、その結果、前回の異常を知ることかできる。ま
Tこ、異常の内容を異常発生順に複数イ1記憶するよう
にしておくことによりほぼ同時に起こつ1こ異常の発生
順をはっきり知ることができ、起こりやすい異常の内容
も知ることができる。牙1こ、電気的に消去が可能であ
ることにより、運転指令装置a3のキー人力によりその
内容を消去することが可能であり、ま1こ起こつ1こ異
常を発生順に記憶素子α1ζ記憶させる場合、複数個記
憶し1こ後その数を一定に保つよう、自動的に消去、書
き込みを行ならことかできる。
The operation will be explained. After the circuit operations in (1) to (3), the number of laps is set using the manual key of the operation command device 1lto3, and the circuit is passed through the arithmetic circuit (8) and the base drive circuit (6) to the inverter circuit (3). ) element on/off ζ
The process by which power is supplied to the inverter (4) is the same as in the conventional circuit, so a description thereof will be omitted. Here, a method will be described in which an abnormality occurs and its contents are stored in the storage element α4. As in the case of FIG. 5, the output writing pressure increases due to the increase in the number of factors. When the current exceeds a predetermined value, the overcurrent detection circuit (7) operates and transmits an abnormal output signal to the arithmetic circuit (8).The arithmetic circuit (8) determines the content of the abnormality from the transmitted γ signal. and instantaneously stores it in the memory element α4 as a symbol (generally a number).The memory element side can be cleverly written and erased, and the memory content can be retained even without power. The lζ subtraction circuit (
8) In the case Cζ where the contactor (IA) is opened at the same time as an abnormality occurs due to the output of the abnormality occurrence signal from the above, and the M control Wtlflμs disappears, the contents of the storage element u4 are the holding np. Therefore, after the power is turned on again, the contents of the memory element α4 can be displayed on the operation command device o3, and as a result, the previous abnormality can be known. By storing the contents of a plurality of abnormalities in the order in which they occur, it is possible to clearly know the order in which abnormalities that occur almost simultaneously occur, and the contents of abnormalities that are likely to occur can also be known. Since it can be erased electrically, it is possible to erase the contents manually by pressing the key of the operation command device a3, and the memory element α1ζ memorizes every abnormality that occurs in the order in which it occurs. In this case, it is possible to store multiple items and automatically erase and write them so that the number remains constant.

次に、異常時における異常検出から異常書き込みまでの
演算回路(8)の動作をプログラムフローチャートによ
n第2図に示す。ますステーIブ(至)で過菫圧異常の
有無を判断する。ステ−・ブαQで過電流異常の有無を
判断し、少なくとも1万存在の場合ニ、ステー、フαη
で異常信号出力する。次にステー・ブ(至)で異常内容
を判別し記号化する。ステー・ブa9ではステ・・・ブ
(至)で判定した記号を記憶素子へ記録する。上記is
を異常発生時に瞬時で行なう。
Next, the operation of the arithmetic circuit (8) from abnormality detection to abnormality writing in the event of an abnormality is shown in FIG. 2 using a program flowchart. The presence or absence of excessive violet pressure abnormality is determined at the first stage I (to). The presence or absence of an overcurrent abnormality is determined by the stay and valve αQ, and if there is at least 10,000, the stay and valve αη are
Outputs an abnormal signal. Next, the content of the abnormality is determined and symbolized at stage V. In step a9, the symbol determined in step (to) is recorded in the memory element. The above is
This is done instantly when an abnormality occurs.

第3図では異常内容の記号の読み出しのフローチャート
を示す。まずステー・ブ■で異常内容の記号の読み出し
円′gを判定する。ステーIブQ′Dではその内容を表
示装置へ出力し、例えばm4図に示すように表示する。
FIG. 3 shows a flowchart for reading symbols indicating abnormality contents. First, the reading circle 'g of the symbol indicating the abnormal content is determined in the stage B. The stave I Q'D outputs the contents to a display device and displays them, for example, as shown in figure m4.

なお亀4図(&)は、加速中に過電圧が検出され1こ時
の表示装置の表示例を、又第4図(b)は過電圧の場合
の表示例ケ夫々示す。以上の動作により、異常書き込み
、読み出しを行なう。
Note that FIG. 4 (&) shows an example of the display on the display device when overvoltage is detected during acceleration, and FIG. 4(b) shows an example of the display in the case of overvoltage. The above operations perform abnormal writing and reading.

なお、上記実施例では異常内容としτ過を庄。In addition, in the above embodiment, the abnormal content is defined as the τ error.

過電流のみを示したが、異常内容に前記以外のものを設
けでもよい。
Although only overcurrent is shown, abnormality contents other than those described above may be provided.

例えば、瞬間的に停電し1こ場合にインバータを保護す
る瞬時停電、ま1こ過負荷状態が長くつづいテインバー
タ負荷が異常過熱になっ1こ場合に保護するサーマル動
作などがある、 〔発明の効果〕 り上のように、この発明に、よれば書き込み消去可能、
w@I遮断時記憶内容の保存可能な記憶手段に異常内容
を格納すると共に、この記憶内容を表示手段に適宜表示
するようCζ構成し1こので、電源断および異常の解除
にまり過去の異常内容か消えることなく、再度市酢投人
後内容を知ることができる。ま1こ、異常内容の履歴を
とることができ、また発生しやすい異常の傾向を知るこ
とができる効果がある。
For example, there are instantaneous power outages that protect the inverter in the event of a momentary power outage, and thermal operations that protect the inverter load when the inverter load abnormally overheats due to a prolonged overload condition. Effects] As described above, according to the present invention, writing and erasing are possible.
W@I is configured to store the abnormality contents in a storage means that can save the memory contents when the power is cut off, and to display the stored contents on the display means as appropriate. The contents will not disappear and you can see the contents again after throwing the city vinegar. First, it is possible to keep a history of abnormalities and to know the tendency of abnormalities that are likely to occur.

【図面の簡単な説明】[Brief explanation of drawings]

第1(′21はこの発明の一実施例による、インバー・
りの異常表示回路を示す図で、第2図、第3図はその動
作を示すフローチャート、第4図は異常表示装置の表示
の一例を示す図、第5因は従来のインバータの異常表示
回路を示す図である。 図にgLNで、(1)ハ交流?Jr#、(IA)は操作
スイッチ、(2)は交流を自流に変換するコンバータ回
路(RAK換’14 ) 、(3)はインバータ回路、
(4)はインバタ負荷″r′あるモータ、(5)は過電
流検出回路、(6)はベース駆ν回路、(7A)は四訛
検出器、(7)は過電流検出回路、(8)は演算回路、
(9)は運転指令装置、αGは過電圧異常発liFを示
す発光素子、αυは過電流異常を示す発光素子、叫は制
御回路用型−10は運転指令装置、α・υは記憶素子、
幌は加速中に過電流か検出されTコ時の表示装置の表示
の一例、■は過電圧の表示装置の表示の一例である。 なお、各図中同一符号は同一ま1こは相当部分を示す。
The first ('21) is an invar according to an embodiment of the present invention.
Figures 2 and 3 are flowcharts showing its operation, Figure 4 is a diagram showing an example of the display of the error display device, and the fifth cause is the error display circuit of a conventional inverter. FIG. In the figure, with gLN, (1) C AC? Jr#, (IA) is the operation switch, (2) is the converter circuit that converts alternating current to free current (RAK conversion '14), (3) is the inverter circuit,
(4) is a motor with an inverter load "r", (5) is an overcurrent detection circuit, (6) is a base drive ν circuit, (7A) is a four-accent detector, (7) is an overcurrent detection circuit, (8) ) is an arithmetic circuit,
(9) is a driving command device, αG is a light-emitting element that indicates overvoltage abnormality generation liF, αυ is a light-emitting element that indicates overcurrent abnormality, 电 is for control circuit type-10 is a driving command device, α・υ is a memory element,
The hood is an example of a display on the display device when an overcurrent is detected during acceleration, and ■ is an example of a display on the display device when an overvoltage occurs. Note that the same reference numerals in each figure indicate corresponding parts.

Claims (2)

【特許請求の範囲】[Claims] (1)交流電源を整流回路にて一たん直流に変換し、ス
イッチング素子により可変電圧、可変周波数の新たな交
流を作り出すインバータにおいて、インバータの異常を
検出する異常検出回路と、該検出回路の出力内容を異常
発生順に記憶する、常時読み書き自由でかつインバータ
の電力しゃ断時にも記憶内容を保持する記憶手段と、該
記憶手段の内容を表示する手段とを備えてなるインバー
タの異常表示回路。
(1) In an inverter that converts AC power into DC using a rectifier circuit and creates new AC with variable voltage and variable frequency using switching elements, there is an abnormality detection circuit that detects an abnormality in the inverter, and the output of the detection circuit. An abnormality display circuit for an inverter, comprising a storage means that stores contents in the order of abnormality occurrence, can be freely read and written at any time, and retains the stored contents even when power to the inverter is cut off, and means for displaying the contents of the storage means.
(2)記憶手段として、電気的に書き込み消去可能でか
つ保持電力がなくても記憶内容が保存可能な素子EEP
−ROMを用いたことを特徴とする特許請求の範囲第1
項記載のインバータの異常表示回路。
(2) As a storage means, an element EEP that is electrically writable and erasable and capable of preserving memory contents even without holding power
-Claim 1 characterized in that a ROM is used.
Inverter abnormality display circuit described in section.
JP62087971A 1987-04-10 1987-04-10 Inverter abnormality indication circuit Pending JPS63257468A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62087971A JPS63257468A (en) 1987-04-10 1987-04-10 Inverter abnormality indication circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62087971A JPS63257468A (en) 1987-04-10 1987-04-10 Inverter abnormality indication circuit

Publications (1)

Publication Number Publication Date
JPS63257468A true JPS63257468A (en) 1988-10-25

Family

ID=13929731

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62087971A Pending JPS63257468A (en) 1987-04-10 1987-04-10 Inverter abnormality indication circuit

Country Status (1)

Country Link
JP (1) JPS63257468A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0387837A (en) * 1989-08-31 1991-04-12 Fuji Photo Film Co Ltd Device for processing photosensitive material
KR100652233B1 (en) 2004-12-07 2006-12-01 엘에스산전 주식회사 Method for monitoring inverter
WO2008047439A1 (en) * 2006-10-19 2008-04-24 Mitsubishi Electric Corporation Power converter
WO2023187863A1 (en) * 2022-03-28 2023-10-05 日立Astemo株式会社 Driving circuit and control method for driving circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0387837A (en) * 1989-08-31 1991-04-12 Fuji Photo Film Co Ltd Device for processing photosensitive material
KR100652233B1 (en) 2004-12-07 2006-12-01 엘에스산전 주식회사 Method for monitoring inverter
WO2008047439A1 (en) * 2006-10-19 2008-04-24 Mitsubishi Electric Corporation Power converter
JPWO2008047439A1 (en) * 2006-10-19 2010-02-18 三菱電機株式会社 Power converter
US8049455B2 (en) 2006-10-19 2011-11-01 Mitsubishi Electric Corporation Electric power converter
WO2023187863A1 (en) * 2022-03-28 2023-10-05 日立Astemo株式会社 Driving circuit and control method for driving circuit

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