JPS63251854A - Multi-port memory controller - Google Patents

Abstract

PURPOSE:To reduce the overhead time needed for arbitration control by using plural control means wet at each port and a circuit abnormality monitoring means and performs the sampling of an application request without using a fixed clock. CONSTITUTION:When an application requesting line 1a is set at a low level after an access is applied to a common memory against an application request, a pulse restart F/F 5a is set at the edge of the line 1a. Then a pulse circulation F/F 4a is set. Thus an application requesting sample F/F 3b of the next stage is started for restart of the pulse circulation. When the circulation pulse extinguishes by some reason while the application requesting line groups 1a-1d are all kept at low levels, an abnormality occurrence monitor up-counter 8 is not reset any more. Thus an overflow is produced and the circulation of the pulse is started by the same operation as that carried out when a power supply is applied. In such a way, the arbitration control is performed at high speed for a multi-port memory with circulation of the priority.

Description

[Detailed description of the invention] [Industrial application field] This invention is a multiport memory controller.

In particular, the present invention relates to a multiport memory controller for controlling access to common memory in a multiprocessor system.

[Prior Art] Figures 3 and 4 show the polling selection method used in line control, etc., described in, for example, Iwao Hosaka, "Introduction to Data Communication Systems", published by Ohmsha, p. 118, etc. in a multi-port memory. 1 is a block diagram of a conventional multiport memory controller used for arbitration control.

FIG. 3 is a block diagram showing an example of the configuration of a multi-CPU system showing the positioning of a multi-port memory controller. In FIG. 6, (1) is a CPU group,
CPU + , CPU 2 , ..., CPU.

Consists of. (2) is a multi-port memory controller whose input side and output side are respectively connected to the CPU group (1) via a use request signal line group (5) and a use approval signal line group (6). (3) is a common memory, which is interconnected with the CPU group (1) via a shared bus (4).

Figure 4 is a block diagram of a multi-port memory controller in the case of 4 ports using the conventional polling method. In Figure 6, (5a) to (5d) are use request signal lines input from each CPU, (6a) to (6d) is a usage approval signal line to each CPU, (7) is an oscillation circuit that generates basic timing to test whether there is a usage request from the CPU, (8)
) is a gate circuit for turning on/off the basic timing signal.

Its input side is connected to the output side of the oscillation circuit (7). (9) is a timing generation circuit.

Its input side is connected to the output side of the gate circuit (8), and generates the timing for sequentially testing whether there is a use request from the CPU. (10) is a latch circuit, one input side of which is connected to the timing circuit (9), and the other input side connected to use request signal lines (5a) to (5d), respectively.

It latches the usage request status and outputs it to the CPU as a usage approval signal. (11) is an OR circuit.

The input side is the use approval signal ff1 (6a) to <6d).

The output side thereof is connected to the gate circuit (8), and during the output of the use approval signal, the gate circuit (8) is notified that the basic timing generation is turned off.

The conventional multi-port memory controller is configured as described above, and when it becomes necessary to use the memory (3), the CPU sends a use request to the multi-port memory controller (2) through the use request signal line (5). will be held. In contrast, if the multiport memory controller (2) is not approved for use, the gate circuit (8) and the timing circuit (9) control each timing signal line (21), (22), (23) at a certain timing. ), (24
) through CPU U + , CPU 2 , ・
” A test is being conducted to see if there is a use request signal for the CPU n, and if the latch circuit (10) detects the presence of a use request signal, it will immediately output a corresponding use approval signal to the use approval signal line (6). The OR circuit (11) and gate circuit (8) suspend the test for the presence or absence of the secondary use request signal until the use request signal is turned off on the CPU side.C.
When access is completed at pu(Il) and the use request signal is turned off, the latch circuit (10) turns off the corresponding use approval signal, and the OR circuit (11) and gate circuit (8)
Then, the test for the presence or absence of the use request signal is restarted through the timing circuit (9).

[Problems to be Solved by the Invention] In the conventional multi-port memory controller as described above, a certain amount of check time is required for each CPU to check whether there is a usage request from each CPU, and memory access In addition to time, there is a problem in that the overhead time for control becomes large and the throughput as a memory apparently decreases.

The present invention was made to solve this problem, and an object of the present invention is to provide a multiport memory controller that reduces overhead time for arbitration control for accesses from each CPU.

[Means for Solving the Problems] A multiport memory controller according to the present invention includes a plurality of control means provided for each port.

The circuit is equipped with circuit abnormality monitoring means.

[Operation] In this invention, when checking the presence or absence of a usage request from each CPU, the check timing is not shifted by a clock, but is generated by a circulating pulse made using the gate delay time of a flip-flop. , reduce the overhead time for arbitration control.

[Embodiment] FIG. 1 is a block diagram showing an embodiment of a multi-port memory controller for 4 ports according to the present invention. In FIG. 0, (la) to (1d) are a group of memory use request lines;
(2a) to (2d) are memory use approval line groups, (3a) to
(3d) is a usage request sample flip-flop (hereinafter referred to as
The flip-flop is abbreviated as F/F), and each data input terminal (D) is used for the east line group (1a) to (1d).
) are connected to each other.

(4a) to (4d) are pulse circulation F/Fs, each data input terminal (D) receives an inverted signal of the usage request, and each clock input terminal (C) receives the output from the previous stage. It has been entered. (5a) to (5d) are pulse restart F/Fs, each of which receives an inverted use request signal at its data input terminal (D).

Each sono output terminal (Q) is Hull X wirMF/F
It is connected to each set terminal (S) of (4a) to (4d), respectively.

(6a) to (6d) are NOR circuits, each input of which is connected to each output of the usage request sample F/F (3a) to (3d) and the pulse circulation F/F (4a) to (4d), and Each output is a usage request sample F of the previous stage.
/F (3m) ~ (3d), pulse circulation F/F
(4a) (4d), pulse restart F/F (5
They are connected to the reset terminals a) to (5d), respectively. (7) is a constant clock, (8) is a clock (7
), the up counter (9) is a NOR circuit, and its input is the water used L! Line group (2a) to (2d
) and output (Q) of pulse circulation F/F (4m)
and.

Its output is the reset terminal (R) of the up counter (8)
are connected to each other. (21a) is the port (a
), which is a control means provided in the use request sample F.
/F (3a), pulse circulation F/F (4a
) and pulse restart F/F (5a). Hereinafter, the control means (
21b) to (21d) are provided, respectively.

FIG. 2 is an operation timing chart of the embodiment shown in FIG. 1.

In the multi-port memory controller configured as above, the use request line group (1a) to (1d) and the use approval line group (2a) to (2d) are set to positive logic, and first, when the power is turned on, each F/F Assuming that is in the reset state, the up counter (8) is incremented by the clock (7) and overflows.

As shown in Fig. 2(a), its output terminal (Q) is “
Outputs “high”.This causes the pulse circulation F/F
(4m) is set, and its output terminal (Q) outputs "high" as shown in Figure 2(b), thereby resetting the up counter (8) and requesting the use of the primary stage. A rising edge is input to the clock inputs of the sample F/F (3b) and the pulse circulation F/F (4b). At this time, if the usage request line (1b) is "low", the pulse circulation F/F (4b)
Since "high" is output to the output terminal (Q) of the F/F of the previous stage (3a), (4a), (5a)
is reset, the output terminal of the pulse circulation F/F (Q
> outputs a pulse. Below, use request line group (1a) ~
(1d) is all "low", each block performs the same operation, and each block's usage request sample F/F (3
It is sequentially input to the clock terminals a) to (3d).

Here, as shown in FIG. 2(f), the use request line (1
When “high” is input to a), it is latched to the use request sample F/F (3a) by the 5th order circulation pulse,
Since the use approval line (2a) becomes "high" (see FIG. 2(g)) and the data input of the pulse circulation F/F (4a) becomes "low", the pulse stops.

After accessing common memory for this usage request.

When the use request line (1a) goes low, the pulse restart F/F (5a) is set at this edge, and the pulse circulation F/F (4a) is subsequently set.

The pulses begin to circulate again with the next stage usage request sample F/F (3b) as the star I. Next, if the circulating pulse disappears for some reason while the usage request line group (1a) to (1d) are all "low", the pulse will no longer circulate forever. An up counter (8) is provided for this purpose, and is normally reset by a circulating pulse or use approval line group (2a) to (2d). Now, if such a situation occurs, the up counter (8) will not be reset, so it will overflow, and pulse circulation will begin in the same manner as when the power is turned on.

Through the above operations, multiport memory arbitration control is performed at high speed while cycling priorities.

In the above embodiment, a pulse restart F/F was used to restart the pulse at the end of the usage request, but it may also be realized using a chopper circuit using a capacitor (C), a resistor (R), and a NAND circuit. .

[Effects of the Invention] As explained above, the present invention includes a plurality of control means and a single circuit abnormality monitoring means provided for each port, and is capable of sampling usage requests without using a fixed clock. Therefore, it is possible to obtain a multiport memory controller with less overhead time for arbitration control.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the invention, FIG. 2 is an operation timing chart of the invention, and FIG. 3 is a diagram showing an example of a multiprocessor system. FIG. 4 is a block diagram of a conventional multiport memory controller. In the figure, (la) to (1d) . . . usage request line group. (2a) to (2d)...use approval line group, (3a) to (
3b)...Use request sample F/F, (4a) to (4
d)...Pulse circulation F/F, (5a) to (5d)...
・Pulse restart F/F, (6a) ~ (6d
)・”Noah circuit, (7)...clock, (8)...
Up counter, (9)...NOR circuit, (21a)...
...It is a control means. Note that the same reference numerals in each figure indicate the same or corresponding parts. 9 g 2 3 ↓ ; 3 ε Procedural amendment September 11, 1986

Claims (3)

[Claims] (1) In arbitration control of a common memory in a multiprocessor system, by providing a plurality of control means provided for each port and a circuit abnormality monitoring means, and connecting each of the plurality of control means in a loop, A multi-port memory controller that performs arbitration control at high speed without being influenced by a specific clock speed, and is configured to self-recover even in the event of an abnormality using the circuit abnormality monitoring means. . (2) The control means is a use request sample flip-flop;
2. A multiport memory controller as claimed in claim 1, comprising a pulse cyclic flip-flop and a pulse restart flip-flop. (3) The multiport memory controller according to claim 1, wherein the circuit abnormality monitoring means is an up counter.