JPS6324716A - Excess current protection circuit - Google Patents
Excess current protection circuitInfo
- Publication number
- JPS6324716A JPS6324716A JP61168640A JP16864086A JPS6324716A JP S6324716 A JPS6324716 A JP S6324716A JP 61168640 A JP61168640 A JP 61168640A JP 16864086 A JP16864086 A JP 16864086A JP S6324716 A JPS6324716 A JP S6324716A
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- current
- constant current
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 20
- 230000005856 abnormality Effects 0.000 claims abstract description 11
- 238000001514 detection method Methods 0.000 claims description 8
- 230000007423 decrease Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 238000007599 discharging Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明に過電流保護回路に関し、特に大電流を出力する
集積回路の過電流保護回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an overcurrent protection circuit, and particularly to an overcurrent protection circuit for an integrated circuit that outputs a large current.
従来この種の過電流保護回路は、出力トランジスタの出
力電流を検出していて異常と判断すると出力トランジス
タをオフさせる様になっている。Conventionally, this type of overcurrent protection circuit detects the output current of the output transistor and turns off the output transistor when it is determined that there is an abnormality.
第４図に従来回路の一例を示す。FIG. 4 shows an example of a conventional circuit.
第４図に示す従来回路において、１に入力回路、３に出
力トランジスタＱ１に駆動するドライバー回路、４は出
力トランジスタＱ１の出力電流？検出しその値に比例し
た電流あるいに電圧全出力する電流検出回路、５は電流
検出回路４の出力に工ってハイ−ロウの信号金量す制御
回路、２は入力回路１の出力と制御回路５の出力の論理
和？出力する論理回路である。ここで制御回路５は、出
力トランジスタＱ１の出力電流がある電流値１５以上と
なった時にその出力レベルが反転し、出力トランジスタ
Ｑｌ をオフ略せる信号が出る様に構成さ几でいる。In the conventional circuit shown in FIG. 4, 1 is an input circuit, 3 is a driver circuit that drives the output transistor Q1, and 4 is an output current of the output transistor Q1? A current detection circuit detects and outputs the entire current or voltage proportional to the detected value; 5 is a control circuit that uses the output of the current detection circuit 4 to measure a high-low signal; 2 is the output of the input circuit 1; Logical OR of the output of control circuit 5? This is a logic circuit that outputs. Here, the control circuit 5 is constructed so that when the output current of the output transistor Q1 reaches a certain current value of 15 or more, its output level is inverted and a signal is output to turn off the output transistor Ql.
また端子Ａは入力端子、端子Ｂμ電源端子、端子Ｃは出
力端子、几りに負荷である。Further, terminal A is an input terminal, terminal Bμ is a power supply terminal, and terminal C is an output terminal, and thus a load.
〔８明が解決し二つとする問題点〕
がかる構成において、負荷に異常（たとえば負荷が小さ
くなったり負荷ショート）が生じて出力電流がＩａエク
大きくなると、制御回路５エク出力トランジスタＱｔ’
Ｔｈオフさせる信号が出て、出力トランジスタＱｉｈオ
フする。[Problems solved and divided into two by 8 Ming] In such a configuration, if an abnormality occurs in the load (for example, the load becomes small or a load short-circuit) and the output current Ia increases, the control circuit 5 output transistor Qt'
A signal to turn off Th is output, and output transistor Qih is turned off.
このため出力を流に減少し、Ｉｓエク小さくなると制御
回路５から出力トランジスタＱ１ｔ−オンぜせる信号が
出るために、再び出力トランジスタＱｌはオンする。そ
うすると再び出力電流ぼ増加し、結果的に上記の動作が
繰り返ｊｎる。この状態は負荷の異常が解除されるまで
継続する。For this reason, the output decreases rapidly, and when the Is error becomes smaller, a signal is output from the control circuit 5 to turn on the output transistor Q1t, so that the output transistor Q1 is turned on again. Then, the output current increases again, and as a result, the above operation is repeated. This state continues until the load abnormality is resolved.
上述の繰り返しの周期及び出力トランジスタＱ１のオン
時間φオフ時間は系の遅れやループゲインで決まり、任
意の値に設定することにできない。The above-mentioned repetition period and the on time φ off time of the output transistor Q1 are determined by the delay of the system and the loop gain, and cannot be set to arbitrary values.
したがってオン時間の長さ及びオン時間／オフ時間の値
にＬつでは出力トランジスタが破壊する場合がある。Therefore, if the length of the on time and the value of the on time/off time are L, the output transistor may be destroyed.
本発明はこの様な間ｆｆｌ金解決した過電流保護回路を
提供することを目的とする。An object of the present invention is to provide an overcurrent protection circuit that solves this problem.
し問題点を解決するための手段〕
本発明の過電流保護回路は、電流検出回路の出力ＩＣＣ
エフハイロウの信号を出すシュミット回路と、このシュ
ミット回路の出力にエフで一定の電流を流し出す様に制
御される第１の定電流回路と、この第１の定電流回路の
出力端子に接続さｔ′１．友コンデンサと、このコンデ
ンサに並列に接読されて前記シュミット回路の出力に工
って一定の電流？吸い込む様に制御される第２の定電流
回路と、ヒステリシスを持ち前記コンデンサの端子電圧
と基準電圧を比較して前記出力トランジスタのオン時間
・オフ時間を制御する比較回路？有している。[Means for Solving the Problems] The overcurrent protection circuit of the present invention has an output ICC of a current detection circuit.
A Schmitt circuit that outputs a F high low signal, a first constant current circuit that is controlled to flow a constant current to the output of this Schmitt circuit, and a circuit connected to the output terminal of this first constant current circuit. '1. Is there a constant current connected to the friend capacitor and the output of the Schmitt circuit that is connected in parallel to this capacitor? A second constant current circuit that is controlled to draw in current, and a comparison circuit that has hysteresis and compares the terminal voltage of the capacitor with a reference voltage to control the on-time and off-time of the output transistor? have.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示すものであり、第 図と
同じ番号、記号は同一のもの七示す。第１図において％
６に電流検出回路４の出力にエフハイ・ロウの信号を出
すシュミット回路、７はシュミット回路６の出力に工っ
て一定の電流を流し出す様に制御される定電流回路、８
はシーミツト回路６の出力ｖｃ工って一定の電流を吸い
込む様に制御ざｎる定１！流回路、９に充放電用のコン
デンサ、１０μヒステリシスを持つ比較回路でコンデン
サ９の端子電圧としきい値を比較する。ここでシュミッ
ト回路６に出力電流のゆらぎや振動に対して誤動作しな
い様に設けら几でおり、出力電流に換算してＩＳＩ、
Ｉｓｚ （ただしＩ ｓｔ ＞Ｉ ８２）のしきい値を
持っている。一方定電流回路７及び８は、出力電流がＩ
Ｓ１以下の時に７がオフで８がオンであり、出力電流が
ＩＳＩの時の時［７がオンで８がオフとなる様に構成さ
几ている。また比較回路１０ｏｔ、ｓいｔｔｉ、ＶＴｉ
ｎ 、 ＶＴｍｏ （タタＬ ＶＴｕｎ ＞ＶＴ＋（υ
）に設定されている。FIG. 1 shows one embodiment of the present invention, and the same numbers and symbols as in FIG. 1 indicate the same elements. In Figure 1, %
6 is a Schmitt circuit that outputs an F-high/low signal to the output of the current detection circuit 4, 7 is a constant current circuit that is controlled to flow a constant current by modifying the output of the Schmitt circuit 6, and 8
The output VC of the seamit circuit 6 is controlled so that it draws a constant current. A current circuit, a charging/discharging capacitor 9, and a comparison circuit with 10 μ hysteresis compare the terminal voltage of the capacitor 9 and the threshold value. Here, the Schmitt circuit 6 is equipped with a mechanism to prevent malfunction due to fluctuations or vibrations in the output current, and the ISI is calculated as the output current.
It has a threshold of Isz (I st >I 82). On the other hand, constant current circuits 7 and 8 have an output current of I
When the output current is less than S1, 7 is off and 8 is on, and when the output current is ISI, 7 is on and 8 is off. In addition, comparison circuits 10ot, stti, VTi
n, VTmo (TataL VTun > VT+(υ
) is set.
図１の実施例における各部のタイミングチャートを第２
図に示す、出力電流が正常な時、即ち出力電流がＩＳ１
以下の時（ｔｏ 以前）、定電流回路７がオフ、定電流
回路８がオンであるからコンデンサ９の端子電圧に接地
電位となり、比較回路１０の出力からに出力トランジス
タＱｒｔオンさせる信号が出ている。次にｔｏ におい
て負荷に異常が −生じて出力電流がＩＳ１以上とな
ると、シュミット回路６の出力が反転して定′ＷＬ流回
路７がオン、８がオフとなる。したがってコンデンサ９
への充電が開始されてコンデンサ９の端子電圧に上昇を
始め、時間ｔ１ｉＣおいて比較回路１ｏのしきい値■〒
圏に達する。すると比較回路１０の出力は反転し、出力
トランジスタＱ１にオフさせる信号を出す。The timing chart of each part in the embodiment of FIG.
As shown in the figure, when the output current is normal, that is, the output current is IS1
At the following time (before to), the constant current circuit 7 is off and the constant current circuit 8 is on, so the terminal voltage of the capacitor 9 becomes the ground potential, and a signal to turn on the output transistor Qrt is output from the output of the comparator circuit 10. There is. Next, when an abnormality occurs in the load at to and the output current exceeds IS1, the output of the Schmitt circuit 6 is reversed, and the constant WL flow circuit 7 is turned on and the constant WL flow circuit 8 is turned off. Therefore capacitor 9
The terminal voltage of the capacitor 9 begins to rise, and at time t1iC, the threshold voltage of the comparator circuit 1o is reached.
reach the sphere. Then, the output of the comparator circuit 10 is inverted, and a signal is output to turn off the output transistor Q1.
この定めに出力トランジスタＱｌがオフして出力電流に
減少し％ 工Ｓ２エク小さくなるとシュミット回路６の
出力が反転して定電流回路７がオフ、８がオンとなる。At this time, the output transistor Ql is turned off and the output current decreases, and when the output current becomes smaller, the output of the Schmitt circuit 6 is reversed, and the constant current circuit 7 is turned off and the constant current circuit 8 is turned on.
したがってコンデンサ９に放！Ｔｈ開始し、コンデンサ
９の端子電圧を始め時間ｔ２において比較回路１０のし
きい値ＶＴｍｔ＞に達する。Therefore, discharge to capacitor 9! Th starts, and the terminal voltage of the capacitor 9 reaches the threshold value VTmt of the comparator circuit 10 at time t2.
すると比較回路１０の出力は再び反転し、出力トランジ
スタＱｌｋオンさせる信号ケ出す。このために出力トラ
ンジスタＱ１がオンして出力室ＲＩｒＸ−増加する。こ
の時出力電流がＩｓ１エク大きいと、シュミット回路６
の出力は再び反転して定電流回路７がオン、８がオフと
なり、コンデンサ９の端子電圧げ上昇を始め時間ｔ３に
おいてＶＴＲ（ロ）に達する、すると１１ における動
作と同様に出力トランジスタＱ＋ ｉオフし、コンデン
サ９の端子電圧に減少して時間ｔ４ｖｃおいてＶＴ）（
（りに達し、比較回路１０の出力は反転して出力トラン
ジスタＱｌ全オンさせる信号？出す。この九めに出力ト
ランジスタＱ１がオンして出力電流に再び増加する。Then, the output of the comparison circuit 10 is inverted again and a signal is generated to turn on the output transistor Qlk. Therefore, the output transistor Q1 is turned on and the output chamber RIrX- increases. At this time, if the output current is large by Is1, the Schmitt circuit 6
The output of is inverted again, constant current circuit 7 is turned on and constant current circuit 8 is turned off, and the terminal voltage of capacitor 9 starts to rise and reaches VTR (b) at time t3.Then, similarly to the operation at 11, output transistor Q+i is turned off. VT)(
(The output of the comparator circuit 10 is inverted and a signal that turns on all the output transistors Q1 is output.) At this ninth point, the output transistor Q1 is turned on and the output current increases again.
こ几らの一連の動作に負荷に異常がある限り継続される
。しかし図２のｔｚに示す様に出力を流がＩＳＩまで達
しない場合、すなわち負荷の異常がなくなっｔ場合ＶＣ
に、定電流回路７がオフ、８がオンの′！マであるため
コンデンサ９の端子電圧に接地電位でで減少し、出力ト
ランジスタＱ１１ｄ入力信号に応じて動作する様になる
。This series of operations will continue as long as there is an abnormality in the load. However, as shown in tz in Fig. 2, if the output current does not reach ISI, that is, if the load abnormality disappears and t, VC
, constant current circuit 7 is off and constant current circuit 8 is on!'! Since the terminal voltage of the capacitor 9 is lowered by the ground potential, the output transistor Q11d operates according to the input signal.
ここで時間（ｔｚ １１）及び（ｔ３−ｔ２）？それ
ぞ几オフ時間ＴＯＦＦ、オン時間ＴＯＮ と呼ぶ。こ
れらのオン時間及びオフ時間に、定電流回路７゜８の電
流値とコンデンサ９の各量須及び比較回路１０のしきい
値ｖＴＨ，，ｖｉ色にエフ任意に設定できる。Here time (tz 11) and (t3-t2)? They are called off time TOFF and on time TON, respectively. During these on-times and off-times, the current value of the constant current circuit 7.8, each quantity of the capacitor 9, and the threshold values vTH, .
しかしオン時間に出力トランジスタＱ１の安全動作領域
より出力電流の異常Ｍを考慮して設定する必要があり５
本実施例の様に約７ＡＩ７：１出力ｉｔ流が流ｎる場合
に１００μｓ８度にしなけ几ばならない。一方オフ時間
は出力トランジスタＱｌの消費電力金抑える様にオン時
間／オフ時間エク決めなければならない。また回路上の
面からに、集積回路におけるコンデンサ９の容量値や定
’ｆｌｌｆＮ、回路７及び８の設定値の実現性の問題と
、比較回路のしきい値ＶＴＨ６＃ 、 ＬｒＨ（＋Ｊ
にエフ制約？受ける。However, it is necessary to set the on-time by considering the abnormality M of the output current from the safe operating area of the output transistor Q15.
When a current of approximately 7AI7:1 output is flowing as in this embodiment, it is necessary to keep the current at 8 degrees for 100 μs. On the other hand, the off time must be determined in such a way as to reduce the power consumption of the output transistor Ql. In addition, from a circuit perspective, there are problems with the capacitance value of capacitor 9 in the integrated circuit, constant 'fllfN, feasibility of setting values of circuits 7 and 8, and threshold values VTH6#, LrH(+J
F constraint? receive.
以上：り本実施例でに、コンデンサ９の容量値ＣＩ ”
６０ ｐＦ＋ 定電流回路７の設定値工、＝１．８
７７へ定’ＦＩＮ回路８の設定値Ｉａ＝０．３μＡ、
Ｖ７Ｈ９＝３．Ｑｙ。Above: In this embodiment, the capacitance value CI of the capacitor 9 is
60 pF+ Setting value of constant current circuit 7, = 1.8
Set value Ia of FIN circuit 8 to 77 = 0.3μA,
V7H9=3. Qy.
Ｖ〒桓！Ｊ＝１．０ｖであり、オン時間ＴＯＮ及びオフ
時間ＴＯＦＦは
の関係工ｒ）ＴｏＮ中７０ Ａｓ、 ’Ｉ’ＯＦＦ中４
００μｓ に設定している。こｔｌＶＣニジ消費電力
に、従来例でオン時間＝オフ時間とした時の消費電力に
対して約３０％に減少する。V〒Han! J = 1.0v, and the on time TON and off time TOFF are related to r) ToN 70 As, 'I' OFF 4
It is set to 00μs. This tlVC power consumption is reduced to about 30% of the power consumption when on time = off time in the conventional example.
次に第３図に本発明の別の実施例？示す。第１図と同じ
番号、記号は同一のものを示す。第３図において点線内
の４は電流検出回路であり、抵抗Ｒ１，Ｒ１２，Ｒ３，
ダイオードＤＩ、トランジスタＱ２．及び定電流源工１
によｔ）構成ざ九でいる。電源端子Ｂと出力トランジ
スタＱ工の間に設けた抵抗几ｌによって出力電流？検出
し、そのＲ１の両端電圧に比例した重圧を抵抗Ｒ３の両
端に発生させている。Next, FIG. 3 shows another embodiment of the present invention. show. The same numbers and symbols as in FIG. 1 indicate the same things. In FIG. 3, 4 inside the dotted line is a current detection circuit, and resistors R1, R12, R3,
Diode DI, transistor Q2. and constant current source work 1
t) The structure is the same. The output current is determined by the resistor installed between the power supply terminal B and the output transistor Q. A heavy pressure proportional to the voltage across the resistor R1 is generated across the resistor R3.
第３図に示す回路の動作に、第１図の実施例で説明した
動作と全く同じである。The operation of the circuit shown in FIG. 3 is exactly the same as that described in the embodiment of FIG.
し発明の効果〕
以上説明した様に本発明の過電流保護回路に：ｎげ、負
荷に異常が生じて出力電流が異常に増加した時の出力ト
ランジスタのオン時間及びオフ時間ケ適切な値に設定す
ることができるａ＝つて出力トランジスタ全安全動作領
域の範囲内で動作させると共に消費電力？抑えることが
でき、出力トランジスタの破壊金防ぐことができる効果
がある。[Effects of the Invention] As explained above, the overcurrent protection circuit of the present invention has the ability to set the on time and off time of the output transistor to appropriate values when an abnormality occurs in the load and the output current increases abnormally. Can you set a = power consumption while operating the output transistor within the entire safe operating area? This has the effect of preventing damage to the output transistor.
第１図は本発明の一実施例を示す回路図、第２図は第１
図の回路における各部のタイミングチャート図、第３図
は本発明の別の実施例全示す回路図である。第４図は従
来例を示す図である。
１・・・・・・入力回路、２・・・・・・論理回路、３
・・・・・・ドライバー回路、４・・・・・・１！流検
出回路、５・・・・・・制御回路、６・・・・−・シュ
ミット回路、７・・・・・・定電流回路、８・・・・・
・定電流回路、９・・・・・−コンデンサ、１０・・・
・・・比較回路、Ｑ１〜Ｑ２・・・−・トランジスタ、
Ｄｌ ・・・・・・ダイオード、Ｒ１−Ｒ３・・・・・
・抵抗、ＲＬ・・・・・負荷、工１・・・・・・定電流
源、Ａ・・・−・−入力端子、Ｂ・・・・・・電源端子
、Ｃ・・・・−・出力端子。Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 3 is a timing chart diagram of each part of the circuit shown in the figure, and FIG. 3 is a circuit diagram showing another embodiment of the present invention. FIG. 4 is a diagram showing a conventional example. 1...Input circuit, 2...Logic circuit, 3
...Driver circuit, 4...1! Current detection circuit, 5... Control circuit, 6... Schmitt circuit, 7... Constant current circuit, 8...
・Constant current circuit, 9...-capacitor, 10...
...comparison circuit, Q1-Q2...-transistor,
Dl...Diode, R1-R3...
・Resistance, RL...Load, Engineering 1...Constant current source, A...--Input terminal, B...Power terminal, C...- Output terminal.
Claims (1)
流検出回路と、この電流検出回路の出力によりハイ、ロ
ウの信号を出すシュミット回路と、このシュミット回路
の出力によって一定の電流を流し出す様に制御される第
１の定電流回路と、この第１の定電流回路の出力端子に
接続されたコンデンサと、このコンデンサに並列に接続
されて前記シュミット回路の出力によって一足の電流を
吸い込む様に制御される第２の定電流回路と、ヒステリ
シスを持ち前記コンデンサの端子電圧と基準電圧を比較
して前記出力トランジスタのオン時間・オフ時間を制御
する比較回路とを備えたことを特徴とする過電流保護回
路。There is a current detection circuit that detects abnormalities in the output current flowing to the output transistor, a Schmitt circuit that outputs high and low signals based on the output of this current detection circuit, and a Schmitt circuit that is controlled so that a constant current flows out by the output of this Schmitt circuit. a first constant current circuit; a capacitor connected to the output terminal of the first constant current circuit; An overcurrent protection circuit comprising: a second constant current circuit; and a comparison circuit having hysteresis and controlling the on time and off time of the output transistor by comparing the terminal voltage of the capacitor with a reference voltage. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61168640A JPH073943B2 (en) | 1986-07-16 | 1986-07-16 | Overcurrent protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61168640A JPH073943B2 (en) | 1986-07-16 | 1986-07-16 | Overcurrent protection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6324716A true JPS6324716A (en) | 1988-02-02 |
| JPH073943B2 JPH073943B2 (en) | 1995-01-18 |
Family
ID=15871786
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61168640A Expired - Lifetime JPH073943B2 (en) | 1986-07-16 | 1986-07-16 | Overcurrent protection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH073943B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02106179U (en) * | 1989-02-07 | 1990-08-23 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57210727A (en) * | 1981-06-01 | 1982-12-24 | Siemens Ag | Power switch unit using field effect transistor |
-
1986
- 1986-07-16 JP JP61168640A patent/JPH073943B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57210727A (en) * | 1981-06-01 | 1982-12-24 | Siemens Ag | Power switch unit using field effect transistor |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02106179U (en) * | 1989-02-07 | 1990-08-23 | ||
| JPH0418551Y2 (en) * | 1989-02-07 | 1992-04-24 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH073943B2 (en) | 1995-01-18 |
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