JPS6324598B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an initial inhibition method for memory read signals, and more specifically, a method for initially inhibiting a memory read signal. The present invention relates to an initial inhibiting method for a read signal from a line control memory in a system in which line control is performed by sequentially and repeatedly reading and transmitting the read signals to a line corresponding section.

In a storage program controlled electronic exchange, especially in a time division exchange, when controlling subscriber lines or trunk lines to select, send, stop signals, etc., the subscriber circuits or trunks receive line control signals from the signal distribution device, respectively. receive. This line control signal is applied in a time-division manner while the line to be controlled is under constant control, for example, while a calling signal is being sent out.

In such a case, it is recommended to temporarily store the line control signal sent from the signal distribution device in the line control memory, read it out sequentially, and give it to the line handling section (the subscriber circuit or trunk of the line handling section). For example, by writing a certain control signal into the memory, the signal distribution device repeatedly sends the control signal from the memory to the line side, eliminating the need to repeatedly send the control signal from the signal distribution device, and When changing line control, for example, stopping the ringing signal being sent to a subscriber's line, the signal distribution device simply rewrites the contents of the address corresponding to the line to be controlled in the memory. This is advantageous because the processing load on the signal distribution device during line control can be reduced.

In the above method, when the electronic exchange is started for the first time or after a power outage, the contents of the line control memory are unstable when the power is turned on. Control may cause problems.
In other words, if the state of the line and the line control signal stored in the memory do not correspond, a ringing signal is sent to a line that is in a talking state where a ringing signal should not be sent (such as when a response is received during a power outage). There is a possibility that such inconvenience may occur.

In the method described above, in which the line control signal sent from the signal distribution device is temporarily stored in the line control memory and then sequentially read out repeatedly to control the line, the line control signal is not operated normally when the power is turned on. Some means of initiating the operation is required.

The present invention provides a system in which a line control signal is temporarily stored in a line control memory as described above, and then sequentially and repeatedly read out to perform line control. The purpose is to enable normal startup automatically when the power is turned on.

Next, an embodiment of the present invention will be described with reference to the drawings. The figure is a block diagram of one embodiment of the present invention.
In the figure, SP is a line corresponding part of an electronic exchange, which includes a register REG and subscriber circuits LC ₁ to LC _o , and is configured as a line shelf, for example.
CP is a control unit, SPR is a signal processor and is also used as a signal distribution device, SDM is line control memory, A.SEL is an address selector, T-
CTR is a time slot counter, and ST is a starting means provided according to the present invention, which includes a flip-flop FF and an AND gate AG.
Note that the figure shows only the parts of the electronic exchange that are necessary for understanding the present invention.

Now, assume that the electronic exchange shown in the figure is powered on. When the power is turned on, the power supply voltage _Vcc rises.
In the starting means ST, the flip-flop FF has three input terminals C, D, R and one output terminal Q, and if there is no reset input to the reset signal input terminal R, the flip-flop FF is reset by the input of the clock input terminal C. is set, and the output terminal Q holds the signal ("1" or "0") that was input to the data input terminal D at that time. When a reset signal is applied to input terminal R, flip-flop FF is reset and the output at output terminal Q is kept at "0".

Suppose now that the power is turned on and the power supply voltage _Vcc rises. The voltage V _cc is input “1” through the resistor r ₂
as data input terminal D of flip-flop FF
Enter. Next, the voltage _Vcc passes through the resistor _r1 and is input to the clock input terminal C as a signal " ₁ " with a slight delay due to the capacitor C0. Therefore, since "1" has already been input to the data input terminal D at this time, when the flip-flop FF is set by the input "1" of the clock input terminal C, the output of the output terminal Q becomes "1". ” is fixed. The output "1" from the output terminal Q is input to the negative input terminal of the AND gate AG, thereby rendering the AND gate AG non-conductive. This allows the memory read signal to be inhibited when the power is turned on.

On the other hand, when the power is turned on, the electronic exchange starts operating, and the line status (subscriber circuit, trunk status) is scanned by the operation of a scanning device (not shown), and the information is sent to the main processor via the signal receiving device. and is processed here to create control information for controlling the line according to its state. This control information is provided by the signal processor SPR shown in the diagram.
sent to.

The signal processor SPR creates a line control signal SD based on the above control information, sends it to the line control memory SDM along with the write address information (WA) corresponding to the line, and also sends it to the line control memory SDM. Send (WE).

In a write cycle, the address selector
A.SEL selects the above write address information (WA) and writes it to the address input terminal AD of the line control memory SDM.
send to

The line control memory SDM receives the write signal (WE) and writes the control signal (SD) corresponding to the line sent to the information input terminal D _in to the address corresponding to the line.

The time slot counter T-CTR counts pulses synchronized with the time slot for controlling the communication path of the relevant electronic exchange, and sends the counting result as a read address to the line control memory SDM, which is then read out from the line control memory. This is a circular counter that returns to 0 when it counts the number corresponding to the total number of SDM addresses. The count output of this time slot counter T-CTR is used as a read address (RW) and is input to the address selector during a read cycle.
A.SEL is selected and input to the address input terminal AD of the line control memory SDM, and the contents of the address are read to the information output terminal _Dput .

In this way, the line control memory SDM is repeatedly read out sequentially (in address order), and the read line control signal is output from the information output terminal _Dput .

However, when the power is turned on, as mentioned above, the AND gate AG is non-conductive, so the line control information output from the information output terminal D _put is blocked and is not sent to the line corresponding part SP, and is sent to each line. is not under any control and is not connected.

As processing in the main processor progresses and control signals for all lines are written to the line control memory SDM, the signal processor SPR detects this and sends the reset signal (RES) to the flip-flop FF.
Send it to the reset signal input terminal R of. As a result, the flip-flop FF is reset and the output of the output terminal Q is fixed at "0".
Since its negative input becomes "0", AG becomes conductive, and the line control signal output from the output terminal D _put of the line control memory SDM is sent to the line correspondence section SP.

The time slot counter T-CTR sends out a timing signal (TS) when sending out address (RA) information in a read cycle.
Read from line control memory SDM, output terminal
The line control signal sent from D _put is sent to the line corresponding section.
The timing signal (TS) is sent to the register REG of the SP, and the timing signal (TS) is sent to the core register REG, which controls it and stores the line control signal sent at that time. Register REG contains line control memory SDM
Since the line control signals read out as described above are sequentially stored, they are sequentially sent to the corresponding lines (subscriber circuits LC ₁ to _{LC o} in the figure) to perform necessary control.

Although one embodiment of the present invention has been described above,
The present invention is not limited to the above-mentioned embodiments, and various modifications can be made within the technical scope thereof.

In the starting means ST, it is possible to use means other than those shown to set the flip-flop FF when the power is turned on.
Although subscriber circuits LC ₁ -LC _o are shown in , the same implementation can be applied to trunks (including speech trunks and non-call trunks such as signaling trunks).

As explained above, according to the present invention, in a storage program controlled electronic switching system, particularly in a time division switching system, line control signals sent from a signal distribution device are temporarily stored in a line control memory, and then read out repeatedly in a sequential manner. When the information is sent to the line handling section to perform line control, there is an advantage that the line control can be automatically and normally activated by a simple means when the power is turned on.

[Brief explanation of the drawing]

The figure is a block diagram showing the connection configuration of one embodiment of the present invention. SP...Line support section, LC ₁ to LC _o ...Subscriber circuit, REG...Register, CP...Control section, SPR...
…Signal processor, SDM…Line control memory, A.SEL…Address selector, T-
CTR……Time slot counter, ST……
Starting means, FF... flip-flop, AG...
and gate.

Claims (1)

[Claims] 1 In a system in which the line control signal sent from the signal distribution device of the storage program controlled electronic exchange is temporarily stored in the line control memory, and is read out repeatedly in sequence and sent to the line corresponding section to perform line control, the above line control There is an AND gate for controlling the conduction of the read signal from the memory, and an AND gate that is set when the power is turned on, and its output controls the AND gate.
A flip-flop is provided which makes the gate non-conductive and is reset when the line control signal for all lines is written in the line control memory, and makes the AND gate conductive by its output, and when the power is turned on, the flip-flop is reset to make the AND gate conductive. An initial inhibiting method for a memory read signal, characterized in that an unstable initial line control signal read from a memory is inhibited.