JPS63241599A - Voice synthesizer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Field of Industrial Application The present invention relates to a speech synthesis device, and in particular to a speech synthesis device that saves memory capacity for storing word data and shortens the program for reading word data from memory. Regarding a synthesis device.

(2) Conventional technology Various methods have been proposed as speech synthesis methods. Various words and phrases prepared in advance are stored in a memory, and necessary word data are sequentially selected and read from the memory during speech synthesis.
The method of concatenating read phrase data to generate synthesized speech is relatively simple and has been widely adopted.

In order to save memory capacity, it is preferable to encode word data and store it in the memory.

To encode the audio waveform, a differential PCM (diNeren-tial
The quantization width can be adjusted to the level of the input signal by using the CM: DPCM) method or the phenomenon that the sampling frequency is high enough for amplitude changes and the sample value changes relatively slowly, such as in audio waveforms. Adaptive quantization (ad
An aptive quantization method can be considered as the information compression means. In order to achieve greater information compression, the adaptive difference P CM (adapt
ive DP CM) is used.

(3) Problems to be Solved by the Invention Conventionally, the above-mentioned speech synthesis control operation has often been performed by a processor running a program. In this case, a part of the data area of the memory, that is, an area where word data necessary for synthesis is stored, is selected and scanned. However, in the case of a method that generates synthesized speech by continuously connecting multiple word data, the length of the control program to perform such operations becomes long, and the throughput of the main program also becomes long. Furthermore, in such a method, the length of the connection between the word data of the synthesized speech and the word data tends to become long, and it is difficult to shorten this length.

The present invention has been made in view of the above, and provides an audio system that maintains the saving of memory capacity, shortens the program length for reading word data, shortens the main program length, and shortens the length of the word data connection section. The present invention provides a synthesis device.

(4) Means for Solving the Problems In order to achieve the above object, the present invention provides a speech synthesis device that sequentially selects and reads out speech data stored in a memory according to a designated signal, connects them, and outputs them as synthesized speech. The designation signal is composed of a plurality of bit signals, and the other bit signal is configured to indicate the start address data of the audio data or its length data according to the state of at least one specific bit among the plurality of bit signals, The audio data corresponding to the start address data is read from the memory and output by referring to the length data determined according to the state of the specific bit.

(5) Effect As described above, in the present invention, necessary audio data is efficiently selectively read out from the memory by using the remaining bit signals as start address data and length data depending on the state of a specific bit among the multiple bit signals. ing.

(6) Embodiment Next, one embodiment of the present invention will be described in detail with reference to the drawings.

In FIG. 1, a data bus of a microcomputer (not shown) with system control functions is connected to an input terminal of an input port l. The input boat l is
For example, an 8-bit D-flip-flop circuit (D-F
F), which can use an I10 or memory configuration, and is assigned to a predetermined address. For ease of explanation, the following explanation will be given assuming that the boat is assigned to address CflBsH, for example.

The input port l is an 8-bit port, into which l word units of voice data (phrase data) are loaded. This one word data is defined as shown in FIG.

In the present invention, data S/L (S
The abbreviation for TART/LENGTH) has a special meaning as described below. That is, when the S/L signal is (1) “H”, the lower 7 bits (BD, ~BD
ρ indicates start address data.

(2) After this bit 7 (S/L) signal rises from “L11” to “H”, the data of the lower bit is determined when a predetermined time tpdsec has elapsed.In other words, the trigger signal for timing pulse generation It has the function of

(3) When “L”, lower 7 bits) (BD6 to BD1)
Indicates that is length data.

(4) After falling from “H” to “L”, a predetermined time t
The lower bit data is determined after pd sec has elapsed.

That is, like (2), it has a function as a trigger signal for timing pulse generation.

Bits 6 to 0 shown in FIG. 2 are audio data B D4.
~B D, and this bit configuration allows 128
Specify the data as per (OOH to 7FH). here,
The upper start address data does not indicate the address itself, but the data of the upper 7 bits of the start address, and similarly, the length data does not indicate the length as is, but the data of the upper 7 bits of the length from the start of the address to stop i. Showing data.

The edge detection & timing pulse generation circuit 2 detects the rise and fall (knee, j) of the S/L signal of bit 7 of the l word unit data shown in FIG. 2, and presets the trigger signal (LD). It is sent to a double up (UP) counter 3 and a presettable down (DOWN) counter 4. The presettable up counter 3 and the presettable down counter 4 each have a start address pointer and a length counter function, and are aJ& so as to be preset by a trigger signal from the edge detection & timing pulse generation circuit 2. Therefore, it is possible to operate the device simply by loading the two words of the start address and length data into C007Htr#l in association with each other as shown in FIG. In this case, timing control using the trigger signal alone is sufficient for the operation of the present device, and other timing control and interrupt control using so-called CTC are not required.

Lower bits (BD
6 to BD,) are supplied to a presettable up counter 3 and a presettable down counter 4, which perform start address control according to the state of the S/L signal and output a word length signal.

The output of the presettable down counter 4 is input to the timing circuit 7 via the gate circuit 5 when the S/L signal is in the "L" state and length data indicated by the lower bit is present.

In this manner, a predetermined audio data generation clock CK is output in accordance with the signal supplied via the gate circuit 5. Therefore, the audio data is output in synchronization with the clock generated from the timing circuit 7 in response to loading the length data into the counter 4. That is, the timing circuit 7 outputs the L of the presettable down counter 4.
This signal changes to L when data is loaded into the length counter, and returns to H when the length counter reaches 0. The timing circuit 7 synchronizes the clock with the falling edge of this signal and sends the clock to the presettable up counter 3. The presettable down counter 4 counts down using the output of the 8th bit from the top of the presettable amplifier counter 3 as a clock. When the output of the presettable down counter 4 becomes OH, the clock is stopped.

Therefore, the timing circuit 7 automatically operates according to a change in the state of the presettable down counter 4. The presettable counter 3 sequentially increments addresses from the start address by the clock from the timing circuit 7, and the audio data corresponding to the output is read from the data memory (ROM) 6. Data ROM8 contains pre-prepared speech data necessary for ADPCM.
Encoded data obtained through processing is stored in correspondence with addresses. This address is input terminal A of data ROM6.
, A, . . . This address is specified by the output of presettable up counter 3,
The audio data selected and read out in this way is supplied to the data selector 8 from the output terminal DD as 8-bit audio data. In response to the timing signal from the timing circuit 7, the data selector 8 takes out the input 8-bit audio data in the order of upper 4 bits and lower 4 bits, and sends them to the audio synthesis circuit 9 as a 4-bit data string. The speech synthesis circuit 9 uses a timing control signal from the timing circuit 7 based on the input digital data to create an analog speech signal using a well-known method, and outputs it as synthesized speech.

An example of the configuration of the data ROM 6 is shown in FIG. In FIG. 4, eight ROMs are used and the RO
An example of the relationship between the address of M and the start address is shown. Also.

Figure 5 shows an example of the contents of voice data (phrases). 1. The contents of synthesized voice, the start address and word length for reading this voice data.
The relationship between

As described above, in the present invention, by combining a 1-bit sign bit, a simple gate circuit that detects its edge, and a length counter, start address data and length data are sent to the same input port by 17-word data (
continuous? By simply loading the program (word only), a certain section of the ROM area is automatically scanned.

(7) Effects of the Invention As described above, in the present invention, the state of one specific bit of the output bit data from the input port selects the other bits, indicating the start address of the read word or its word length. Because it is set like this,
There is no need to selectively scan word memory areas as in the past, and the program length and the length between connected words can be significantly shortened with a simple configuration compared to the past.

[Brief explanation of drawings]

Figure ii is a block diagram showing an example of the configuration of a speech synthesis device according to the present invention, Figure 2 is a diagram showing an example of an l-word data arrangement, and Figure 3 is a diagram showing an example of words for start address data and length data. Figure 4 is a diagram showing an example of the relationship between the ROM address and the start address, and Figure 5 is a diagram showing an example of the relationship between the ROM address and the start address.
FIG. 3 is a diagram showing the contents of audio data (phrases) stored in OM along with a start address and word length. 1... Input port 2... Edge detection & timing pulse generation circuit 3...
・Presettable up counter 4...Presettable down counter 5...Gate circuit 6...Data ROM 7...Timing circuit 8...Data selector 9...Speech synthesis circuit

Claims (9)

[Claims] (1) In a speech synthesis device that sequentially selects and reads out audio data stored in a memory according to a designated signal, concatenates them, and outputs them as synthesized speech, the designated signal is composed of a plurality of bit signals, and at least one of the plurality of bit signals is The other bit signal is configured to indicate the start address data of the audio data or the length data thereof depending on the state of one specific bit, and the start address data is determined based on the length data determined depending on the state of the specific bit. A speech synthesis device characterized in that speech data corresponding to address data is read from the memory and outputted. (2) The speech synthesis device according to claim (1), wherein the specific bit is the most significant bit. (3) The speech synthesis device according to claim (1), further comprising detection means for detecting the state of the specific bit. (4) The speech synthesis device according to claim (3), wherein the detection means is means for detecting rising and falling edges of the specific bit. (5) The speech synthesis device according to claim (1), wherein when the specific bit is "H", the remaining bits are configured to indicate the start address data. (6) The speech synthesis device according to claim (1), wherein when the specific bit is "L", the remaining bits are configured to indicate the length data. (7) Claim (4) provides means for outputting a trigger signal indicating that the start address data or length data has been determined after a predetermined period of time has elapsed after a change in the rising or falling edge of the specific bit. A speech synthesis device comprising: (8) In claim (1), upon receiving the start address data, the reading means of the memory performs a preset operation depending on the state of the specific bit, and upon receiving the designated signal, reads the memory using a clock of a predetermined frequency. A speech synthesis device characterized by being a presettable up counter that counts up. (9) In claim (1), the means for receiving the length data and outputting a signal corresponding to the length of the audio data is preset operated according to the state of the specific bit, and is clocked at a predetermined frequency. A speech synthesis device characterized by being a presettable down counter that counts down.