JPS63240374A - Voltage multiplying circuit for capacitor diode - Google Patents

Voltage multiplying circuit for capacitor diode

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Publication number
JPS63240374A
JPS63240374A JP6950187A JP6950187A JPS63240374A JP S63240374 A JPS63240374 A JP S63240374A JP 6950187 A JP6950187 A JP 6950187A JP 6950187 A JP6950187 A JP 6950187A JP S63240374 A JPS63240374 A JP S63240374A
Authority
JP
Japan
Prior art keywords
voltage
diode
circuit
capacitor
diodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6950187A
Other languages
Japanese (ja)
Inventor
Yoshio Takamura
高村 芳雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP6950187A priority Critical patent/JPS63240374A/en
Publication of JPS63240374A publication Critical patent/JPS63240374A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To reduce rush current and make the title circuit highly efficient, by connecting a diode to a capacitor to be connected to the diode through a resistor. CONSTITUTION:In a Cockcroft-Walton type voltage multiplying circuit having 4 multiplying stages, the connecting points b'-j' of diodes D1-D8 and the connecting points b-j of capacitors C1-C8 are connected through respective resistors R1-R9 (the value of resistance of all resistors is same). According to this constitution, an overcurrent (rush current) upon alternating an input voltage may be suppressed perfectly and, further, the regulation of an output voltage may be effected in some degree by the selection of the value of resistance. Currents flowing through the diodes D1-D8 are minimized; therefore, a comparatively inexpensive diode allowable current is small may be employed.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) この発明は?!2数個のコンデンサ及びダイオードのf
f11合わせにより交流入力電圧から直流高電圧を1q
るコンデンサ・ダイオード電圧逓倍回路に係り、特に交
流入力電圧が矩形波であるときのラッシュ電流の軽減と
1効率化に関する。
[Detailed description of the invention] [Object of the invention] (Field of industrial application) What is this invention? ! f of two or more capacitors and diodes
By adjusting f11, the DC high voltage is reduced by 1q from the AC input voltage.
The present invention relates to a capacitor/diode voltage multiplier circuit, and particularly relates to reducing rush current and increasing efficiency when the AC input voltage is a rectangular wave.

(従来の技術) 周知のように、コンデンサ・ダイオード電圧逓18回路
には種々のものが開発されているが、最も基本的な回路
としてコツククロフト・つ4ルトン型雷圧逓イ8回路が
ある。この回路は、例えば第10図に逓倍段数4段のも
のを示して説明すると、複数個(ここでは4個)のコン
デンサC1〜C4を直列接続した第1のコンデンサ回路
と、これと同数のコンデンサC5〜C8を直列接続した
第2のコンデンサ回路を有する。コンデンサ01〜C4
の各出力端c、e、g、i、はそれぞれダイオードD2
.D4.D6.D8を介してコン“デン勺C5〜C8の
各出力端d、f、h、jに接続され、コンデンサ05〜
C8の各入力端す、d、f。
(Prior Art) As is well known, various types of capacitor-diode voltage distribution circuits have been developed, but the most basic circuit is the Cottcroft-Luton type lightning voltage distribution circuit. For example, this circuit is explained by showing a four-stage multiplication circuit in FIG. It has a second capacitor circuit in which C5 to C8 are connected in series. Capacitor 01~C4
Each output terminal c, e, g, i, is connected to a diode D2.
.. D4. D6. It is connected to each output terminal d, f, h, j of the capacitors C5 to C8 through D8, and the capacitors 05 to 05
Each input terminal S, d, f of C8.

hはそれぞれダイオードI)1.D3.D5.D7を介
してコンデンサC1〜C4の各出力端c、e。
h are respective diodes I)1. D3. D5. Each output c, e of the capacitors C1-C4 via D7.

q、iに接続されている。各ダイオードD1〜D8はそ
れぞれ整流の向きが同じになるようにして、第2のコン
デンサ回路の入出力端す、1間に直列接続されている。
q, connected to i. The diodes D1 to D8 are connected in series between the input and output terminals 1 and 1 of the second capacitor circuit so that their rectifying directions are the same.

第1及び第2のコンデンサ回路の入力端a、b間には矩
形波交流電源Pcが接続され、第2のコンデンサ回路の
入力端すは接地され、第2のコンデンサ回路の入出力端
す、 3間には負荷抵抗RLが接続されている。
A rectangular wave AC power supply Pc is connected between input terminals a and b of the first and second capacitor circuits, the input terminal of the second capacitor circuit is grounded, and the input and output terminals of the second capacitor circuit are grounded. A load resistor RL is connected between the terminals 3 and 3.

つまり、この電圧逓倍回路はダイオードD1〜D8によ
り交流電源Pcの出力が反転する毎にコンデンサの充電
経路を変えてCI、C5,C2゜・・・の順に充電して
いくようにしたものである。このとき各コンデンサの充
電予は、交流電源PCの出力電圧を土EtcV!とヴる
と、最終的にC1がHHv3、c2〜C8が2E[V)
となるので、この回路の出力電圧は8Ei[V]となる
。つまり、この回路の出力電圧は交流入力電圧に逓倍段
数の2倍を乗じたものとなる。
In other words, this voltage multiplier circuit uses diodes D1 to D8 to charge the capacitors in the order of CI, C5, C2°, etc. by changing the charging path of the capacitor every time the output of the AC power supply PC is reversed. . At this time, each capacitor is charged using the output voltage of the AC power supply PC (EtcV!). Finally, C1 becomes HHv3, and c2 to C8 become 2E[V]
Therefore, the output voltage of this circuit is 8Ei [V]. In other words, the output voltage of this circuit is the AC input voltage multiplied by twice the number of multiplication stages.

上記コツククロフト・つηルトン型に代表される電圧逓
18回路は開発当初(1932年)から主として正弦波
入力が用いられてきた。この場合、入力゛電源系及び各
ダイオードに流れる電流は比較的偲やかであるため、問
題は少なかった。ところが、近年になってコンバータ技
術が光達じ、コンバーク回路が入力電源に用いられるこ
とが「劇的に多くなってきている。この場合、電源出力
波形は一般的に矩形波となる。このように入力電圧が矩
形波である場合、電圧交番の瞬間に各コンデンサ間に過
大に電流(ラッシュ電流)が生ずることになる。このこ
とはz Bとなるコンバータ回路系にも種々の問題を光
生させる。また、入力電圧の立上がりの過渡時には電圧
交番の瞬間電流が極めて大きくなるのでダイオードを破
損してしまうこともあり、比較的許容電流値の大きいダ
イオードを用いる必要がある。このため従来では、電源
系に波形をなまらせる手段を講じたり、回路入力端に最
も近いダイオードのみ出力電圧に影響のない程度の抵抗
を直列に付加する等の方法によって過大電流を制限して
いる。
Since its development in 1932, the voltage converter circuit represented by the Kotscroft-Truton type has mainly used a sine wave input. In this case, there were few problems because the current flowing through the input power supply system and each diode was relatively slow. However, in recent years, converter technology has taken off, and the number of converter circuits being used for input power supplies has dramatically increased.In this case, the power supply output waveform is generally a rectangular wave. If the input voltage is a rectangular wave, an excessive current (rush current) will be generated between each capacitor at the moment of voltage alternation.This will also cause various problems in the converter circuit system that becomes zB. In addition, during the transient rise of the input voltage, the instantaneous current of the voltage alternation becomes extremely large, which may damage the diode, so it is necessary to use a diode with a relatively large allowable current value.For this reason, in the past, the power supply Excessive current is limited by methods such as taking measures to round the waveform in the system or adding a resistor in series with only the diode closest to the circuit input terminal to a degree that does not affect the output voltage.

しかしながら、上記のように電源出力波形をなまらせる
手段は電源回路の複雑化を(11き、さらには効率を低
下させる問題が生じる。また、ダイオードを保護するた
めにダイオードに抵抗を直列に接続する方法もあるが、
抵抗による損失に対する配慮から数Ω乃至数十Ωの範囲
の低抵抗が使用されでいたが、さして有効な効果は得ら
れなかった。
However, the method of blunting the power supply output waveform as described above causes the problem of complicating the power supply circuit (11) and further reducing the efficiency.Also, in order to protect the diode, a resistor is connected in series with the diode. There are ways, but
Low resistances in the range of several ohms to several tens of ohms have been used in consideration of loss due to resistance, but very effective effects have not been obtained.

(発明が解決しようとする問題点) この発明は、従来では交流入力が矩形波電圧である場合
、電圧交番時に発生するラッシュ電流に対する有効な手
段がなかったことを考慮してなされたもので、交流入力
が矩形波電圧であっても簡単な4か成でラッシュ電流を
充分低減させることができ、許容電流値の小さなダイオ
ードを使用することができ、しかも高効率なコンデンサ
・ダイオード電圧逓倍回路を提供することを目的とする
(Problems to be Solved by the Invention) This invention was made in consideration of the fact that in the past, when the AC input was a rectangular wave voltage, there was no effective means for dealing with the rush current that occurs during voltage alternation. Even if the AC input is a square wave voltage, the rush current can be sufficiently reduced with a simple 4-component configuration, allowing the use of diodes with a small allowable current value, and a highly efficient capacitor-diode voltage multiplier circuit. The purpose is to provide.

〔発明の構成] (問題点を解決づ−るための手段) この発明に係るコンデンサ・ダイオード電圧層イ8回路
は、ダイオードとこれに接続ささるべきコンデンサとを
抵抗を介して接続することを特徴とするものである。
[Structure of the Invention] (Means for Solving the Problems) The capacitor/diode voltage layer A8 circuit according to the present invention connects a diode and a capacitor to be connected to the diode through a resistor. This is a characteristic feature.

〈作 用) 上記構成によるコンデンサ・ダイオード電圧:、1倍回
路は、ダイオードに直列接続した抵抗により、ダイオー
ドに流れる電流を極めて小さくすることができ、入力電
圧交番時の過大電流を完全に抑圧することができ、さら
には電源回路の簡素化及び高効率化を図ることができる
(Function) The capacitor/diode voltage:1 multiplier circuit with the above configuration can extremely reduce the current flowing through the diode by using a resistor connected in series with the diode, completely suppressing excessive current when the input voltage is alternating. Furthermore, it is possible to simplify the power supply circuit and improve its efficiency.

(実施例) 以下、′iS1図及び第2図を参照してこの発明の一実
施例を説明する。但し、第1図において第10図と同一
部分には同一符号を付して示し、ここでは異なる部分に
ついてのみ述べる。
(Embodiment) Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 and 2. However, in FIG. 1, the same parts as in FIG. 10 are denoted by the same reference numerals, and only the different parts will be described here.

第1図は第5図に示した逓イB段数4段のコツククロフ
ト・つ4ルトン型電圧逓侶回路にこの発明を適用した場
合の構成を示すものである。この回路は、前記ダイオー
ドD1〜D8の接続点す−〜」−とコンデンサC1〜C
8の接続点b−jとをそれぞれ抵抗R1〜R9(抵抗値
は全て同じ)を介して接続したものである。
FIG. 1 shows a configuration in which the present invention is applied to the Cotscroft-Luton type voltage switching circuit having four stages of multiplication circuit B shown in FIG. This circuit consists of the connecting points of the diodes D1 to D8 and the capacitors C1 to C.
8 connection points b-j are connected via resistors R1 to R9 (all have the same resistance value).

すなわち、第5図に示した回路の全てのダイオードD1
〜D8とコンデンサC1〜C8との間を抵抗を介して接
続することは必ずしも出力電圧の低下を生じせしめず、
抵抗1nがある程度大きくなるとむしろ出力電圧は増大
し、しかも抵抗値によつて出力電圧が変化することが実
験によって明らかにされた。
That is, all the diodes D1 in the circuit shown in FIG.
~ Connecting D8 and capacitors C1 to C8 via resistors does not necessarily cause a decrease in output voltage;
Experiments have revealed that when the resistance 1n increases to a certain extent, the output voltage actually increases, and that the output voltage changes depending on the resistance value.

上記実験結果を第2図に示す。第2図は、コンデンサ0
1〜C8の容色を0.1[μ「]、負荷抵抗RLを10
[MΩ]、矩形波交流入力電圧の波高1a1000[V
]、周波数を50[Hz](周期20 [mS] ) 
、立上がり及び立下がり時間を0.2[mslとしたと
きの抵抗R1〜R7の抵抗値変化に対する出力電圧の変
化を示す特性図である。この場合、出力電圧は抵抗値が
IQO[Ω]程度から急速に増大し、1.8[kΩ]付
近で最大1直となる。そして、抵抗値の大きい方の有効
範囲は1少めで広<、50 [kΩ]でし通常の出力よ
り大凸な出力電圧が1qられる。
The above experimental results are shown in FIG. Figure 2 shows capacitor 0
The color of 1 to C8 is 0.1 [μ''], and the load resistance RL is 10.
[MΩ], wave height of square wave AC input voltage 1a1000[V
], the frequency is 50 [Hz] (period 20 [mS])
, is a characteristic diagram showing changes in output voltage with respect to changes in resistance values of resistors R1 to R7 when rise and fall times are set to 0.2 [msl]. In this case, the output voltage increases rapidly from a resistance value of about IQO [Ω], and reaches a maximum of 1 voltage around 1.8 [kΩ]. The effective range of the larger resistance value is 1 less and wider than 50 [kΩ], and an output voltage 1q larger than the normal output is produced.

さらに実験及び動作解析を行なった結果、0段コツクク
ロフト・ウオルトン型電圧逓イB回路の出力電圧を最大
にするには次式を満足させればよいことが明らかとなっ
た。
Furthermore, as a result of experiments and operational analysis, it has become clear that the output voltage of the 0-stage Cotscroft-Walton type voltage multiplier B circuit can be maximized by satisfying the following equation.

r=anb <n+1)etr/2Ei−=(1)但し
、では構成コンデンサの容色とダイオードに直列接続さ
れる抵抗値との積で定まる時定数、a。
r=anb <n+1) etr/2Ei-=(1) However, the time constant, a, is determined by the product of the capacitance of the component capacitor and the resistance value connected in series with the diode.

bは実験によって求められた定数で、 a=3×10′2〜5×10呟、 b=2.7〜3.3、 e=I10−f’(Iは負荷電流、Cはコンデンサ8吊
、fは入力電圧周波数)、Eiは入力電圧、し「は入力
電圧[iの立上がり時間、nは逓倍段数でダイオードの
個数の半分である。n、a、bそれぞれについて実験し
たが、いずれの場合も有効範囲は極めて広く、τは10
[μS]から入力電圧[iの周期の半分程度までの範囲
に及ぶことが明らかとなった。但し口が1の場合は電圧
上背の効果が得られなかった。
b is a constant determined by experiment, a = 3 x 10'2 to 5 x 10 m, b = 2.7 to 3.3, e = I10 - f' (I is load current, C is 8 capacitors) , f is the input voltage frequency), Ei is the input voltage, is the rise time of the input voltage [i, and n is the number of multiplication stages, which is half the number of diodes. The effective range is also extremely wide, and τ is 10
It has become clear that the range ranges from [μS] to about half the period of the input voltage [i. However, when the number of ports was 1, the effect of increasing the voltage was not obtained.

以上のことから、上記のように全てのダイオードに直列
に抵抗を挿入接続したコツククロフト・ウオルトン型電
圧逓倍回路は、入力電圧交番時の過大電流、つまりラッ
シュ電流を完全に抑圧することができ、さらには抵抗値
の選択により成る程度の出力電圧の調整も可能である。
From the above, the Kotscroft-Walton voltage multiplier circuit in which resistors are inserted and connected in series with all diodes as described above can completely suppress excessive current, that is, rush current, when the input voltage is alternated. It is also possible to adjust the output voltage by selecting the resistance value.

そして、ダイオードに流れる電流が惨めで小さくなるの
で、比較的安価な許容電流値の小さいダイオードを使用
することができる。さらに、電源側から見た場合、この
電圧逓倍回路はほぼ純抵抗とみなせるので、電源回路に
ラッシュ電流出力防止用の手段を講じる必要がない。こ
のため、電源回路を簡素化することができ、矩形波をそ
のまま入力することができるので極めて高効率となる。
Since the current flowing through the diode becomes miserable and small, a relatively inexpensive diode with a small allowable current value can be used. Furthermore, when viewed from the power supply side, this voltage multiplier circuit can be regarded as almost a pure resistance, so there is no need to provide the power supply circuit with any means for preventing rush current output. Therefore, the power supply circuit can be simplified and the rectangular wave can be input as is, resulting in extremely high efficiency.

そして、従来より出力電圧が」け大するので、負荷電流
が一定であるとずれば電圧降下が少なくなる。このこと
は出力インピーダンスが低くなったことを意味する。
Furthermore, since the output voltage is higher than in the conventional case, if the load current is constant, the voltage drop will be reduced. This means that the output impedance has become lower.

尚、電源出力が正弦波の場合、出力電圧上昇はほとんど
認められなかったが、出力電圧が同一であってもダイオ
ードに流れる電流を大幅に軽減できるという効果は1g
られる。
Furthermore, when the power supply output was a sine wave, almost no increase in the output voltage was observed, but even if the output voltage was the same, the effect of significantly reducing the current flowing through the diode was 1 g.
It will be done.

さらに、この発明は上記実施例に限定されるものではな
く、例えば第3図及び第4図に示すように他のコンデン
サ・ダイオード電圧3%倍回路についても同様に実施可
能である。
Furthermore, the present invention is not limited to the above-mentioned embodiment, and can be similarly implemented with other capacitor/diode voltage 3% multiplier circuits as shown in FIGS. 3 and 4, for example.

づなわら、第3図に示す電圧”>’14倍回路は、ダイ
オードD11〜D19を直列接続し、その接続点b−i
にそれぞれコンデンサ011〜C19の一方端を接続し
、CI 1,014.C17を直列接続し、C12,C
15,C18を直列接続し、C13,CI6,019を
直列接続し、接続点aを接地し、a、1間に負荷抵抗R
Lを接快し、コン1ンサC12の他端及び接地間に第1
の交流電源Pc 1を接続し、コンデンサC11の他端
及び接Jlj1間に第2の交流電源P。2を接続した電
圧逓倍回路に対し、各ダイオードとコンデンサとの接続
点を切りはなしコンデンサ側の各点a〜hとダイオード
側の各点a−〜h−との間に抵抗R11〜R19を接続
したものである。尚、第1及び第2の矩形波交流電源P
c 1 、 Pc 2は同位相出力であり、例えば1個
の交流電源にトランスを接続しその2次巻線に中間タッ
プを設け、これを接地覆ることにより構成することがで
きる。この場合の電圧上?効果は第1図の場合と同様で
あり、出力電圧を最大にするにはn=(無負荷出力電圧
)/2Eiとして、(1)式を満足させるようにすれば
よい。
In other words, the voltage ">'14 multiplier circuit shown in FIG. 3 connects diodes D11 to D19 in series, and
Connect one end of capacitors 011 to C19 to CI 1,014. Connect C17 in series, C12, C
15, C18 are connected in series, C13, CI6, 019 are connected in series, connection point a is grounded, and a load resistance R is connected between a and 1.
Connect the first capacitor C12 between the other end of the capacitor C12 and the ground.
A second AC power source P is connected between the other end of the capacitor C11 and the contact Jlj1. For the voltage multiplier circuit with 2 connected, disconnect the connection points between each diode and capacitor, and connect resistors R11 to R19 between each point a to h on the capacitor side and each point a to h- on the diode side. This is what I did. In addition, the first and second rectangular wave AC power supplies P
c 1 and Pc 2 are outputs in the same phase, and can be configured, for example, by connecting a transformer to one AC power source, providing an intermediate tap in its secondary winding, and covering this with ground. On voltage in this case? The effect is the same as in the case of FIG. 1, and in order to maximize the output voltage, n=(no-load output voltage)/2Ei, and formula (1) is satisfied.

第4図は両波整流型コツククロフト・ウオルトン回路と
称される回路にこの発明を適用した場合の偶成を示すも
のである。この回路はそれぞれコンデンサC21,C2
2,C23,C24゜C25,026,C27,C28
,C29からなる第1乃至第3のコンデンサ直列回路と
、それぞれダイオードD21〜D26、D27〜D32
よりなる第1及び第2のダイオード直列回路を有しいて
いる。ぞして、第1及び第2のコンデンサ直列回路と第
1のダイオード直列回路で第1の交流電源Pc1を入力
電源とする正性性側のコツククロフト・つ4ルトン回路
を溝成し、第1及び第3のコンデンサ直列回路と第2の
ダイオード直列回路で第2の交流電源Pc 2を入力電
源とする負極四側のコツククロフト・つ4ルトン回路を
構成した両波整流コツククロフト・ウオルトン回路の各
ダイオードの接続点と各コンデンサの接続点とをそれぞ
れ抵抗R21〜R34を介して接続するようにしたもの
である。この回路の出力電圧を最大にする条件式は、n
=<JiW会荷出荷出力電圧2「1とすれば(1)式に
一致するが、定数aを0.7x10’2〜1゜3X10
−2とした方がより正確に求められることが実験及び動
作解析によって確められた。
FIG. 4 shows a conjunctive state when the present invention is applied to a circuit called a double-wave rectifier Cockcroft-Walton circuit. This circuit consists of capacitors C21 and C2, respectively.
2, C23, C24°C25,026, C27, C28
, C29, and diodes D21-D26, D27-D32, respectively.
It has a first and second diode series circuit consisting of. Then, the first and second capacitor series circuits and the first diode series circuit form a positive-side Kotscroft-Two Luton circuit using the first AC power source Pc1 as an input power source. and each diode of a double-wave rectifier Cockcroft-Walton circuit, which is configured with a third capacitor series circuit and a second diode series circuit to form a Cockcroft-Walton circuit on the four negative pole sides using the second AC power source Pc2 as an input power source. The connection point of the capacitor and the connection point of each capacitor are connected through resistors R21 to R34, respectively. The conditional expression that maximizes the output voltage of this circuit is n
=<JiW shipping output voltage 2 If it is set to 1, it will match equation (1), but if the constant a is 0.7x10'2~1°3x10
It has been confirmed through experiments and operation analysis that −2 can be determined more accurately.

第6図は第1図の片側だけに適用した場合である。同図
において第1図と同一部分には同一符号を付して示す。
FIG. 6 shows a case where the method shown in FIG. 1 is applied only to one side. In this figure, the same parts as in FIG. 1 are designated by the same reference numerals.

この場合も充分な効果が得られる。In this case as well, sufficient effects can be obtained.

コ(7) PA合(1)式のaは6×101〜10×1
0″2にすれば実験式として成立する。
(7) PA In equation (1), a is 6×101 to 10×1
If it is set to 0″2, it will hold true as an experimental formula.

第7図も第3図の一部だけに適用したものである。同図
において第3図と同一部分には同一符号を付して示す。
FIG. 7 is also applied to only a part of FIG. 3. In this figure, the same parts as in FIG. 3 are designated by the same reference numerals.

この場合も充分な効果が得られる。In this case as well, sufficient effects can be obtained.

(1)式もn=(無負荷出力電圧)/2Eiで考えれば
a=6×10′2〜10X10″2で成立する。
Equation (1) also holds if n=(no-load output voltage)/2Ei, a=6×10′2 to 10×10″2.

第8図は第4図の一部だけに適用したものである。同図
において第4図と同一部分には同一符号を付して示す。
FIG. 8 is applied only to a part of FIG. 4. In this figure, the same parts as in FIG. 4 are designated by the same reference numerals.

この場合も充分な効果が得られる。In this case as well, sufficient effects can be obtained.

この場合も(1)式はn=(無負荷出ツノ電圧)/2E
 iT′a=1.5 x10゛2〜2.5 X104で
成立する。
In this case as well, equation (1) is n = (no-load output horn voltage)/2E
iT'a=1.5x10゛2~2.5X104.

第9図、第10図はそれぞれ第6図、第7図の回路につ
いて更に適用範囲を狭め、抵抗接続を2箇所とした実施
1りjである。第9図、第10図において、第6図、第
7図と同一部分には同一符号を付して示1゜この場合も
一応の出力電圧の上昇と成る程度のラッシュ電流軽減が
期待できる。
FIGS. 9 and 10 are the first embodiment of the circuits shown in FIGS. 6 and 7, respectively, in which the scope of application is further narrowed and the resistance connections are made at two locations. In FIGS. 9 and 10, the same parts as in FIGS. 6 and 7 are denoted by the same reference numerals.In this case as well, it can be expected that the rush current will be reduced to the extent that the output voltage will rise to some extent.

なお適用を1ケ所のみとした場合、効果はほとんど期待
できない。
However, if it is applied to only one place, little effect can be expected.

以上のことから、この発明は種々のコンテン1ノ・グイ
オード電圧逓倍回路において有効であるものと考えられ
る。
From the above, it is believed that the present invention is effective in various content-1-Giode voltage multiplier circuits.

[発明の効果1 以上のようにこの発明によれば、交流入力が矩形波電圧
であっても簡?トな構成でラッシュ電流を充分低減させ
ることかてき、許容電流値の小さなりイオードを使用す
ることができ、しかも高効率なコンデンサ・グイオード
電圧逓倍回路を提供すろことができる。
[Effect of the Invention 1 As described above, according to the present invention, even if the AC input is a rectangular wave voltage, it is easy to use. The rush current can be sufficiently reduced with a simple configuration, a diode with a small permissible current value can be used, and a highly efficient capacitor/guiode voltage multiplier circuit can be provided.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明に係るコンデンサ・グイオード電圧源
18回路の一実施例を示す回路構成図、?lS2図(よ
同実施例の実験結果を示す特性図、第3図乃至第9図は
それぞれこの発明に係る他の実施例を示す回路構成図、
第10図は従来のコンデンサ・グイオード電圧逓倍回路
として代表的なコツククロフト・・り4ルトン型回路の
構成を示す回路図である。 C1〜C8,C11〜C19,C21〜G29・・・コ
ンデンサ、D1〜D8.D11〜D19゜021〜D3
2・・・ダイオード、R1−R8゜R11〜R19,R
21〜R32・−・抵抗、PClPc 1 、 Pc 
2・・・矩形波交流電源、RL・・・負荷抵抗。 出願人代理人 弁理士 鈴江武ル 第2図括抗値 第4図 第5図 第6図 第9図
FIG. 1 is a circuit configuration diagram showing an embodiment of an 18 capacitor/guiode voltage source circuit according to the present invention. Figure 1S2 (characteristic diagram showing the experimental results of the same example; Figures 3 to 9 are circuit configuration diagrams showing other examples according to the present invention, respectively;
FIG. 10 is a circuit diagram showing the configuration of a typical Kotscroft-Rilton type circuit as a conventional capacitor/guiode voltage multiplier circuit. C1-C8, C11-C19, C21-G29... Capacitor, D1-D8. D11~D19゜021~D3
2...Diode, R1-R8°R11-R19,R
21~R32---Resistance, PClPc1, Pc
2...Square wave AC power supply, RL...Load resistance. Applicant's representative Patent attorney Takeru Suzue Figure 2 Summary of resistance values Figure 4 Figure 5 Figure 6 Figure 9

Claims (1)

【特許請求の範囲】[Claims] 複数個のコンデンサ及びダイオードを組合わせ接続して
交流入力電圧から直流逓倍電圧を生成するコンデンサ・
ダイオード電圧逓倍回路において、前記ダイオードとこ
れに接続すべき前記コンデンサとを少くも2ヶ所抵抗を
介して接続したことを特徴とするコンデンサ・ダイオー
ド電圧逓倍回路
A capacitor that generates DC multiplied voltage from AC input voltage by connecting multiple capacitors and diodes in combination.
A capacitor/diode voltage multiplier circuit, characterized in that the diode and the capacitor to be connected to the diode are connected via resistors at at least two places.
JP6950187A 1987-03-24 1987-03-24 Voltage multiplying circuit for capacitor diode Pending JPS63240374A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6950187A JPS63240374A (en) 1987-03-24 1987-03-24 Voltage multiplying circuit for capacitor diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6950187A JPS63240374A (en) 1987-03-24 1987-03-24 Voltage multiplying circuit for capacitor diode

Publications (1)

Publication Number Publication Date
JPS63240374A true JPS63240374A (en) 1988-10-06

Family

ID=13404535

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6950187A Pending JPS63240374A (en) 1987-03-24 1987-03-24 Voltage multiplying circuit for capacitor diode

Country Status (1)

Country Link
JP (1) JPS63240374A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101238633A (en) * 2005-08-08 2008-08-06 皇家飞利浦电子股份有限公司 Voltage multiplier with improved power efficiency and apparatus provided with such voltage multiplier
CN103595272A (en) * 2013-10-18 2014-02-19 上海交通大学 Thyristor phase-controlled direct-current circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101238633A (en) * 2005-08-08 2008-08-06 皇家飞利浦电子股份有限公司 Voltage multiplier with improved power efficiency and apparatus provided with such voltage multiplier
JP2009505617A (en) * 2005-08-08 2009-02-05 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Voltage multiplier circuit with improved power efficiency and equipment provided with such a voltage multiplier circuit
US7944719B2 (en) * 2005-08-08 2011-05-17 Koninklijke Philips Electronics N.V. Voltage multiplier with improved power efficiency and apparatus provided with such voltage multiplier
CN103595272A (en) * 2013-10-18 2014-02-19 上海交通大学 Thyristor phase-controlled direct-current circuit

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