JPS63238681A - Data taking-in circuit - Google Patents

Abstract

PURPOSE:To process data at a high speed by taking data into a FIFO only at the time of discriminating this data to be required data by a data discriminating means and storing the data taken into this FIFO in a memory. CONSTITUTION:Data is taken into FIFOs 11 and 12 only when this data is judged to be required data by a data discriminating means 9, and data taken into FIFOs 11 and 12 is stored in a memory 21. Consequently, it is unnecessary to equalize data processing speeds of a circuit system before data taking-in of FIFOs 11 and 12 and that after data taking-in of FIFOs 11 and 12 because FIFOs 11 an 12 function as buffers where data is temporarily stored, and the data processing is sufficiently performed even if the processing speed of the circuit system before data taking-in of FIFOs 11 and 12 is increased and that of the circuit system after data taking-in of FIFOs 11 and 12 is reduced. Thus, the data processing is performed at a high speed as the whole.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data acquisition circuit that stores data for analysis of data obtained from various measuring devices, for example.

[Summary of the Invention] The present invention provides a data acquisition circuit that stores data in a memory, and only when the data determining means determines that the data is necessary data, the data is imported into the FIFO, and the data imported into the FIFO is processed. By storing data in memory, unnecessary data is not stored in memory, which saves memory space, and data processing speeds can be made different between the circuit system up to the FIFO data acquisition and the circuit system after that. This has the effect of facilitating circuit design, etc., and providing high-precision, high-speed data processing.

[Prior Art] In FIG. 2, an analog data signal, which is a measurement result, is manually input to an input terminal 30, and this data signal is output to an A/D converter 'a31. This A/D converter 31 converts an analog data signal into a digital data signal based on a sampling clock, and this digital data signal is sent to a computer 32. This computer 32
A/I) stores the digital data signal from the converter 3I in the RAM 33 based on the old clock signal.

The data stored in this RAM 33 is then read out later for data analysis.

[Problems to be Solved by the Invention] However, in the above configuration, all data entered manually from the input terminal 30 is stored in the RAM 33, so the R
It was necessary to prepare an AM33 with a storage capacity corresponding to the amount of input data.

However, even in cases where it is not necessary to capture all data, such as in a measuring device that measures the number of scratches on a product, the data capture circuit has the disadvantage that it is very uneconomical because it stores all data in the RAM 33. there were.

In addition, in the above configuration, it is necessary to synchronize the sampling clock of the A/D converter 31 and the write clock of the RAM 33, so the circuit design and design should take this into consideration.
It is necessary to perform software design, etc.

And in terms of data processing speed, computer 3
The drive speed is limited to 2. Therefore, in order to ensure data processing speed, it is necessary to lower the frequency of the sampling clock, but lowering the frequency reduces data accuracy. Furthermore, since the processing speed decreases when data accuracy is improved, there is a drawback that it is not possible to satisfy both data accuracy and processing speed.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a data acquisition circuit that eliminates the above-mentioned drawbacks.

[Means for Solving the Problems] The configuration of the present invention to achieve the above object includes a data discrimination means for discriminating whether data is necessary data or unnecessary data, and a data discrimination means for discriminating necessary data. It consists of a FIFO that takes in data only when it is determined that this is the case, and a memory that stores the data that has been taken into the FIFO.

[Operation] Therefore, unnecessary data is not taken into the FIFO, only necessary data is taken in, and only necessary data is stored in the memory. Also, since the FIFO takes in only the necessary data and acts as a buffer to temporarily store the data, it is necessary to make the data processing speed of the circuit system up to and after the FIFO data the same as that of the circuit system after it. Even if you increase the speed of the circuit up to the F I F O data acquisition and slow down the speed of the circuit after that, data processing can be performed sufficiently, so data processing as a whole can be performed at high speed. It will be done.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

This embodiment shows a case where the data acquisition circuit is applied to a laser disk scratch detection device.

In FIG. 1, a drive shaft 2 of a motor 1 is fixed at the center of a rotary table 3, and the rotary table 3 is rotated by the driving force of the motor I.

A laser disk 4, which is an object to be measured, is attached to the upper surface of the rotary table 3, and above the laser disk 4, a laser source 5 and a reflecting mirror 6 are provided. The laser source 5 and the reflection mirror 6 are provided movably in the radial direction of the rotary table 3, and the laser beam reflected by the surface of the laser disk 4 is reflected again by the reflection mirror 6 and enters the laser detector 7.

This laser detector 7 detects a change in the amplitude of the incident laser light and outputs a voltage proportional to the amount of change in amplitude to the amplifier 8. Therefore, the output of this laser detector 7 indicates information on the degree of scratches. The amplifier 8 amplifies the input voltage and transmits it to the comparator 9 and the A/D converter! Output each to 0.

In this embodiment, the comparator 9 is configured as data discrimination means, and the output voltage V of the amplifier 8 is led to one input terminal, and the reference voltage v0 is led to one input terminal.

Then, the output voltage V and the reference voltage ■. When the output voltage V is larger than the reference voltage
Output each to 2. By varying the reference voltage, the degree of scratches captured as data can be varied.

The A/D converter 10 converts the output voltage (analog data) of the amplifier 8 into 9-bit digital data using a clock signal sent from the PLL 15 described below as a sampling clock, and converts this digital data (information on the extent of scratches) into 9-bit digital data. Output to the first FI Foll.

On the other hand, the frequency generator 13 consists of a rotating part 13a fixed to the drive shaft 2 of the motor 1 and a sensor part 13b disposed at a position facing the rotating part 13a.
A frequency signal corresponding to the rotational speed of is outputted to the PLL 15 via the amplifier 14.

The pulse generator I6 consists of a detection section 16a provided on the drive shaft 2 of the motor 1 and a sensor section +6b provided at a position opposite to the detection section 16a, and generates -pulses per rotation of the drive shaft 2 to the amplifier 16. It is output to the counter 17 via.

The PLL (phase-locked loop circuit) 15 compensates for frequency fluctuations caused by mechanical precision errors of the frequency generator I3, and A/D converts a stable lock signal (average IMHz) corresponding to the rotational speed of the rotary table 3. device IO, counter 17
, output to the first FIPOll and the second PIFOI2.

The counter 17 counts the number of clocks from the PLL 15, and this count is sent to the second FIFO 12 as a 9-bit digital signal. This counter 17 is reset by a pulse from the pulse generator 16, and the data of the counter 17 indicates rotation angle information.

The -th and second F'1FOs (first-in, first-out memories) 11 and 12 temporarily store input data in their built-in memories and output the stored data in the order of input. is the output of comparator 9, and the write control clock terminal is the PL
The outputs of L15 are respectively led. First FIF
The output of the A/D converter IO is input to the data input terminal of OII, and the output of counter 1 is input to the data input terminal of the second PIFO12.
The outputs of 7 and 7 are respectively derived. Then, only when ten voltages are applied to the light control terminal, the first F
'1FOII and 20)PIFOI2 write data from the A/D converter 10 and the counter 17 into the memory, respectively. In addition, a read signal from the computer 18 is led to the read control terminals of the - and second FIPO II, 12, a clock signal from the computer 18 is led to the read control clock terminal, and each data output terminal is computer 18
It is connected to the common terminal of 11022.

That is, writing to the first and second FMFO IIs 12 is performed using a clock corresponding to the rotational speed of the turntable 3, and reading is performed by the computer! 8 clock, and writes and reads asynchronously.

The computer 18 includes a CPU 19, a ROM 20, and (7) a RAM 21 and 11022 for data storage. The CPU 19 has the first and second FIFO II, 1
The data stored in the RAM 21 is read out and the read data is controlled to be stored in the RAM 21. That is, the first FIl? 011 and the second FIFO 12, and the scratch degree information and its rotational position information are alternately stored in the RAM 21.

Here, the processing speed up to the data acquisition of the first and second FIFO II, 12 is determined by the clock frequency of the PLL 15, and the second and second FIFO II?12 processing speed is determined by the clock frequency of the PLL 15. IP”0
The processing speed after data acquisition in 11 and 12 is determined by the read clock frequency of the computer I8,
The rotational speed of the motor 1 is determined so that the clock frequency of the PLL 15 is faster than the readout clock frequency of the computer 18.

The operation of the above configuration will be explained below.

When the motor 1 is driven, the laser disk 4 rotates together with the rotating table 3. The laser source 5 moves in a straight line from the outer periphery of the laser disk 4 toward the center without emitting a laser beam, and the laser beam is reflected by the surface of the laser disk 4 and then reflected again by the reflection mirror 6 and enters the laser detector 7. Shine. If there is a scratch on the surface of the laser disk 4, an amplitude change occurs in the incident light, and the laser detector 7 outputs a voltage (information on the extent of the scratch) corresponding to this amplitude change. This output voltage is converted into a digital signal by the A/D converter 10, and the scratch degree information converted into a digital signal is sent to the first FI.
Output to FOll.

On the other hand, the frequency generator 13 outputs a frequency corresponding to the rotational speed of the rotating table 3, and this is stabilized by the PLL 15.

The counter I7 is rotated by the output clock of the PLL 15, and the counter 17 indicates rotational position information, which is output to the second PIFO 12. Said P L L
At the output clock of I5, in addition to the counter 17, the A/
Since the D converter 10 is activated, the scratch degree information and the rotational position information have a corresponding relationship.

Here, if there is no scratch on the surface of the laser disk 4 or there is a slight scratch, the voltage ■ input to the comparator 9 is the reference voltage ■. smaller than the first and second FIFO II, 1
2 becomes deaf and cannot write the digital signal from the A/D converter 10 (information on the degree of scratches) and the digital signal from the counter 17 (rotational position information). On the other hand, if there are more than a certain number of scratches on the surface of the laser disk 4, the voltage V input to the comparator 9 becomes larger than the reference voltage v0, and the first and second FIFOs II and 12 enter the write state. And the first F'1F011 has A
A digital signal (information on the extent of scratches) from the /D converter IO and a digital signal (rotational position information) from the counter 17 are written into the second FIPO 12 based on the write control clock. Therefore, only information regarding scratches exceeding a certain level is input to the first and second PIF'011 and 12.

On the other hand, the computer 18 alternately outputs a read control signal to the first FIFO 12 and the second PIFO 12.

The scratch degree information and the rotational position information of the scratch stored in the RAM 21 are read out in this order and written to the RAM 21 based on the read control clock. Therefore, only information regarding scratches exceeding a certain level is stored in this RAM 21 manually.

Also, although the processing speed up to data capture of the second and second FIFO II and 12 is faster than the processing speed after data capture 4, the amount of processing up to data capture and the amount of processing after data capture are significantly different. Therefore, it will not become impossible to process. Therefore, the processing speed up to data acquisition of the FIFOll and 12 can be determined without being limited by the processing speed of the computer 18, and therefore, highly accurate and high speed data processing is possible. Later, R.A.
The data stored in the M21 is retrieved and the size and distribution of scratches are analyzed by a microcomputer, for example, to determine whether the laser disk 4 is defective. In this example, the case where normal data is unnecessary data and abnormal data is necessary data has been explained, but the opposite may be used, or only data in a certain area may be considered necessary data. Data in other areas may be treated as unnecessary data, and whether data is necessary or unnecessary is appropriately determined on a case-by-case basis.

[Effects of the Invention] As described above, according to the present invention, data discriminating means is provided, and data is imported into the FIFO only when the data discriminating means determines that the data is necessary. Since the data is stored in the memory, unnecessary data is not stored in the memory, resulting in an effect of saving memory. Also, since F I F O was used, FIF
The speeds of the circuit system up to data acquisition of O and the circuit system after that can be made different, which facilitates circuit design and has the effect of providing high precision and high speed data processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a laser disk scratch detection device showing an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional data acquisition circuit. 9... Comparator (data discrimination means), l! ...
First FIFO1I2...Second PIF'0121.
...IZAM (memory).

Claims (1)

[Claims] A data discriminating means for discriminating whether data is necessary or unnecessary data, a FIFO that takes in data only when the data discriminating means discriminates that the data is necessary, and this FIFO.
1. A data acquisition circuit comprising: a memory for storing data acquired in an O.