JPS63237150A - Interruption process system for data communication - Google Patents

Interruption process system for data communication

Info

Publication number
JPS63237150A
JPS63237150A JP7202687A JP7202687A JPS63237150A JP S63237150 A JPS63237150 A JP S63237150A JP 7202687 A JP7202687 A JP 7202687A JP 7202687 A JP7202687 A JP 7202687A JP S63237150 A JPS63237150 A JP S63237150A
Authority
JP
Japan
Prior art keywords
computer
communication
interrupted
data communication
priority
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7202687A
Other languages
Japanese (ja)
Inventor
Osamu Noda
修 野田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7202687A priority Critical patent/JPS63237150A/en
Publication of JPS63237150A publication Critical patent/JPS63237150A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24Handling requests for interconnection or transfer for access to input/output bus using interrupt

Abstract

PURPOSE:To effectively execute communication by interrupting from a computer whose priority is high to a computer whose use frequency is high so as to execute data communication and resetting the data communication released by the interruption after completing the communication. CONSTITUTION:When a computer terminal (DTB) 102 interrupts a computer terminal (DTA) 101 and the computer (COM) 103 which are under communication by dialing a special number in order to execute an emergent communication, the CPU 104 transmits an interruption message to the DTA 101 and the COM 103, when the priority of the DTA 102 is higher than that of the DTB 101, and forcedly releases the data communication between them, after that it connects a link between the COM 103 and the DTB 102 so as to start the communication. After completing the communication, the communicating state between the DTA 101 and the COM 103 returns.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はデータ通信割込み処理方式に関し、特にコンピ
ュータ又はコンピュータ端末間のデータ通信可能な蓄積
プログラム制御式交換機(以下SPCと記す)において
通信中のコンピュータ又はコンピュータ端末に対して他
コンピュータ又はコンピュータ端末から割込みを行う際
のデータ通信割込み処理方式に間する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data communication interrupt processing system, and particularly to a data communication interrupt processing system that is used to process data during communication in a storage program controlled switch (hereinafter referred to as SPC) capable of data communication between computers or computer terminals. This invention describes a data communication interrupt processing method when interrupting a computer or computer terminal from another computer or computer terminal.

〔従来の技術〕[Conventional technology]

従来、この種の割込み処理方式では、割込みをかけたコ
ンピュータ又はコンピュータ端末に対して話中表示又は
話中指示を送出するだけとなっていた。
Conventionally, this type of interrupt processing method has only sent a busy display or busy instruction to the computer or computer terminal that has issued the interrupt.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の割込み処理方式は、通信希望のコンピュ
ータ又はコンピュータ端末が他コンピュータ又はコンピ
ュータ端末と通信中であれば、話中表示又は話中指示を
送出するだけなので、その通信が終了するまで待たなけ
ればならなかった。
The conventional interrupt processing method described above only sends out a busy display or busy instruction if the computer or computer terminal with which you wish to communicate is in communication with another computer or computer terminal, so you have to wait until the communication ends. I had to.

従って使用頻度の高いコンピュータ又はコンピュータ端
末に対しては、ダイヤルする度に話中に遭遇することが
あり、緊急の用件が発生しても通信できないという欠点
がある。
Therefore, frequently used computers or computer terminals have the drawback that each time you dial, you may encounter a busy call, and even if an urgent matter arises, you cannot communicate.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のデータ通信割込み処理方式は、SPCに接続さ
れているコンピュータ又はコンピュータ端末の優先度を
記憶している優先度メモリと、被割込みコンピュータ又
はコンピュータ端末の有無および割込みが有った時の被
割込みコンピュータ又はコンピュータ端末の収容位置を
記憶している被割込みメモリとを各端末毎に有している
The data communication interrupt processing method of the present invention uses a priority memory that stores the priorities of computers or computer terminals connected to the SPC, the presence or absence of an interrupted computer or computer terminal, and the priority memory when an interrupt occurs. Each terminal has an interrupt computer or an interrupt target memory that stores the storage location of the computer terminal.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明のデータ通信割込み処理方式の一実施例
を示すブロック図、第2図は第1図における動作を説明
するためのフローチャートである。第1図において、S
PCのネットワーク(以下NW)100には、コンピュ
ータ端末(以下DTA、DTB)101.102と、コ
ンピュータ(以下COM)103が収容されており、中
央演算装置(以下CPU)104はSPC内の接続処理
を司る。CPU104には優先度メモリ(以下PM)1
05が各コンピュータ又は端末毎に4ピツI・用意され
、それぞれの端末優先度(以下P)は保守用ターミナル
(以下MAT)110から一般に知られている方法で書
き込まれる。また、CPU104には、被割込みメモリ
(以下工M)106が各端末対応に用意されており、I
M106は割込みにより強制復旧されたコンピュータ又
は端末の有無を示す被割込み判別ビット(以下JB)1
07とその収容位置を示す被割込み収容位置メモリ(以
下EN)108から構成されている。
FIG. 1 is a block diagram showing an embodiment of the data communication interrupt processing method of the present invention, and FIG. 2 is a flowchart for explaining the operation in FIG. 1. In Figure 1, S
A PC network (hereinafter referred to as NW) 100 accommodates computer terminals (hereinafter referred to as DTA, DTB) 101 and 102 and a computer (hereinafter referred to as COM) 103, and a central processing unit (hereinafter referred to as CPU) 104 handles connection processing within the SPC. in charge of The CPU 104 has a priority memory (PM) 1
05 is prepared for each computer or terminal, and the terminal priority (hereinafter referred to as P) of each terminal is written from the maintenance terminal (hereinafter referred to as MAT) 110 using a generally known method. In addition, the CPU 104 is provided with an interruptible memory (hereinafter referred to as M) 106 for each terminal.
M106 is an interrupt determination bit (hereinafter referred to as JB) 1 that indicates the presence or absence of a computer or terminal that has been forcibly restored by an interrupt.
07 and an interrupt storage location memory (hereinafter referred to as EN) 108 indicating the storage location thereof.

続いて本実施例の動作について第2図を併用して説明す
る。
Next, the operation of this embodiment will be explained with reference to FIG. 2.

例えば、DTA 101がNWlooを介してC0M1
03とデータ通信を実行中とする。この状態テDTB 
102がC0M103とデータ通信を実行すべくC0M
103の番号をダイヤルする。この時、NWlooの実
線図示のリンクを介してDTAlolとCOM 103
が通信中のため、DTB102には話中表示が送出され
る。
For example, DTA 101 connects C0M1 via NWloo.
Data communication with 03 is in progress. This state Te DTB
C0M 102 to perform data communication with C0M103
Dial the 103 number. At this time, DTAlol and COM 103 are connected via the solid line link of NWloo.
is in communication, a busy indication is sent to the DTB 102.

ここでDTB 102が緊急の通信を行うため特番をダ
イヤルして通信中のDTA 101とC0M103に割
込みをかけると、CPU104はDTAlolとDTB
 102のP2O3をPM105から読み出して比較し
、DTA 101のP2O3よりもDTB102のP2
O3が高い優先度のときはDTAIOIとC0M103
に割込みメツセージを送ってその間のデータ通信を強制
復旧させた後、C0M103とDTB102間のリンク
(第1図のNWlooに破線図示)を接続し通信を開始
させる0次いでCPU104はC0M103のIM10
6のJB107に“1”を設定し、EN108にDTA
 101の収容位置を書き込む。
When the DTB 102 dials a special number to make an emergency communication and interrupts the communicating DTA 101 and C0M 103, the CPU 104 calls DTAlol and DTB.
102's P2O3 is read from PM105 and compared, P2 of DTB102 is higher than P2O3 of DTA 101.
DTAIOI and C0M103 when O3 has high priority
After forcibly restoring data communication by sending an interrupt message to , connect the link between C0M103 and DTB102 (shown with a broken line at NWloo in Figure 1) and start communication.
Set “1” to JB107 of 6, and set DTA to EN108.
Write the accommodation position of 101.

DTB102とC0M103間のデータ通信が終了した
ときCPU 104はC0M103のIM106を読み
出し、JB107に“1″が立てられているときは割込
みによってC0M103との通信を強制復旧されたコン
ピュータ又はコンピュータ端末有りと判断してEN10
8からDTAlolの収容位置を読み出し、C0M10
3が空きであれば再発呼し、割込み前の状態、つまりD
TAl、01とC0M103との通信状態に戻る。
When data communication between DTB102 and C0M103 is completed, CPU 104 reads IM106 of C0M103, and when JB107 is set to "1", it is determined that there is a computer or computer terminal whose communication with C0M103 has been forcibly restored by an interrupt. and EN10
Read the storage position of DTAlol from 8 and set it to C0M10.
If 3 is empty, it will be called again and the state before the interruption, that is, D
The communication status between TAL, 01 and C0M103 is returned.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、中央演算装置にSPCに
接続されているコンピュータ又はコンピュータ端末の優
先度を示す優先度メモリと、割り込まれ強制復旧された
コンピュータ又はコンピュータ端末の収容位置を記憶す
る被割込みメモリを有することにより、使用頻度の高い
コンピュータ又はコンピュータ端末に対し優先度の高い
コンピュータ又はコンピュータ端末から割込みをかけて
そのデータ通信を実行し、通信終了後は割込みにより復
旧させられたデータ通信を再設定するので、緊急時に待
つことなしに、また復旧された側も一々ダイヤルしてデ
ータ通信を再設定することなしに、通信が効率良く行わ
れる効果がある。
As explained above, the present invention provides a central processing unit with a priority memory that indicates the priority of computers or computer terminals connected to an SPC, and a memory that stores the accommodation positions of computers or computer terminals that have been interrupted and forcibly restored. By having an interrupt memory, a frequently used computer or computer terminal can be interrupted by a computer or computer terminal with a high priority to execute the data communication, and after the communication is completed, the data communication restored by the interrupt can be resumed. Since the settings are reset, there is an effect that communication can be carried out efficiently without waiting in case of an emergency, and without the need for the restored side to dial and reset data communication one by one.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明のデータ通信割込み処理方式の一実施例
を示すブロック図、第2図は第1図における動作を説明
するためのフローチャートである。 100・・・ネットワーク(NW)、101.102・
・・コンピュータ端末(DTA、DTB)、103・・
・コンピュータ(COM) 、104・・・中央演算装
置(CPU)、105・・・優先度メモリ(PM)、1
06・・・被割込みメモリ(IM)、107・・・被割
込み判別ビット(JB)、108・・・被割込み端末収
容位置メモリ(EN)、109・・・端末纂1図 貞ぢ2凶(イ91) 第2図(イの2) C:コンと−一タ×t@44ミ
FIG. 1 is a block diagram showing an embodiment of the data communication interrupt processing method of the present invention, and FIG. 2 is a flowchart for explaining the operation in FIG. 1. 100...Network (NW), 101.102.
...Computer terminal (DTA, DTB), 103...
- Computer (COM), 104... Central processing unit (CPU), 105... Priority memory (PM), 1
06...Interrupted memory (IM), 107...Interrupted determination bit (JB), 108...Interrupted terminal storage location memory (EN), 109...Terminal collection 1 diagram 2) A91) Figure 2 (A-2) C: Con and -1ta x t@44mi

Claims (1)

【特許請求の範囲】[Claims] コンピュータによるデータ通信が可能な蓄積プログラム
制御式の交換機において、前記交換機の中央演算装置側
に各端子毎に設けられたコンピュータの優先度を記憶す
る優先度メモリと、割り込まれたコンピュータの収容位
置を記憶する被割込みメモリとを備え、データ通信中の
前記コンピュータに割込みがあつたとき前記中央演算装
置は割込み側と被割込み側の各端末の優先度を前記優先
度メモリから読み出して比較し、割込み側の優先度が高
い場合にはこの割込み側と通信するコンピュータの前記
被割込みメモリに被割込みコンピュータの収容位置を登
録するとともに被割込み側に割込みメッセージを送出し
て割込み側との通信を開始させ、その通信終了後に前記
被割込みメモリから被割込みコンピュータを読み出して
再通信させることを特徴とするデータ通信割込み処理方
式。
In a storage program controlled switching system capable of data communication by a computer, a priority memory is provided for each terminal on the central processing unit side of the switching system to store the priority of the computer, and a storage position of the interrupted computer is stored. When an interrupt occurs to the computer during data communication, the central processing unit reads the priorities of each terminal on the interrupting side and the interrupted side from the priority memory, compares them, and interrupts the computer. If the priority of the side is high, the storage location of the interrupted computer is registered in the interrupted memory of the computer communicating with this interrupted side, and an interrupt message is sent to the interrupted side to start communication with the interrupted side. . A data communication interrupt processing method, characterized in that after the end of the communication, the computer to be interrupted is read from the memory to be interrupted and communicated again.
JP7202687A 1987-03-25 1987-03-25 Interruption process system for data communication Pending JPS63237150A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7202687A JPS63237150A (en) 1987-03-25 1987-03-25 Interruption process system for data communication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7202687A JPS63237150A (en) 1987-03-25 1987-03-25 Interruption process system for data communication

Publications (1)

Publication Number Publication Date
JPS63237150A true JPS63237150A (en) 1988-10-03

Family

ID=13477488

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7202687A Pending JPS63237150A (en) 1987-03-25 1987-03-25 Interruption process system for data communication

Country Status (1)

Country Link
JP (1) JPS63237150A (en)

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