JPS63236405A - Fm receiver - Google Patents

Abstract

PURPOSE:To stabilize demodulation, by detecting a specific signal whose amplitude in a demodulation signal is not changed, and controlling the gain of a loop by an error voltage obtained by a comparator. CONSTITUTION:A signal demodulated by a PLL is branched and inputted to an amplitude detection circuit 6, and the signal whose amplitude in the demodulation signal is not changed, for example, the synchronizing signal of a video signal, etc., is detected, and it is compared with the output of an amplitude setting circuit 7, and a difference between them is fed back to a loop amplifier 4. Also, in a no signal period, or at the time of applying a power source, the output of a fixed voltage generator 23 is applied on the loop amplifier 4 by a switch 22 in the middle way of selection. Thereby, it is possible to perform a stable signal processing, and the frequency width of a pull-in operation is expanded in a selection period and in the missing term of a reception signal, then, the processing can be performed at high speed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a phase-locked loop (PIGJF#Laockm
The present invention relates to an A receiver that receives and demodulates a frequency modulation (FM) signal using a ti Loop (hereinafter abbreviated as PLL).

[Conventional technology]

Conventionally, a receiver that simultaneously performs tuning and demodulation using a PLL-based FM demodulation circuit uses a variable capacitance diode that constitutes a voltage-controlled oscillator of the demodulation circuit to select a tune, as described in Japanese Utility Model Application No. 58-176414. Tuning is performed by applying a voltage and varying the free-running oscillation frequency of the voltage controlled oscillator, and FM demodulation is performed using the same PLL.

[Problem that the invention seeks to solve]

The frequency KMII4 sensitivity of the voltage controlled oscillator of the PLL can be considered to be constant within the signal band in which demodulation operation is performed, but when considered over a wide range of the receiving band 9, for example 1 to 1.5 GHz (first intermediate frequency) of satellite broadcasting, Not necessarily constant but different. For the PLL loop gain, the sensitivity of the phase comparator is
, (V/rad), the frequency modulation sensitivity of the voltage controlled oscillator is (ra←X), and the gain of the loop amplifier is
It is expressed by the following formula.

K = AK, a K, * Ka (1) From equation +11, when the frequency modulation sensitivity of the voltage-controlled excavator changes, the PLL
This results in a change in the loop gain of the PLL, resulting in a problem that the PLL loop conditions differ depending on the receiving channel. Further, since the amplitude of the demodulated signal of the PLL is inversely proportional to the frequency modulation sensitivity of the voltage controlled oscillator, even if signals with the same frequency shift are demodulated, the image width of the demodulated signal varies depending on the receiving channel.

An object of the present invention is to provide stable QIvI4 even if the frequency modulation sensitivity of the voltage controlled oscillator changes.

[Means to solve the problem]

The above object is an amplitude detection circuit that detects the amplitude of a demodulated signal output from the input side of a loop amplifier in a PLL, and an amplitude set by inputting the output of the amplitude detection circuit.

It is equipped with an amplitude comparator that outputs an error voltage by comparing the amplitude comparator with the amplitude comparator, and forms a loop that controls the gain of the above-mentioned loop amplifier using the output of the amplitude collector, and also controls the tuning period of the receiving channel and the receiving signal. The dropout period is achieved by fixing the gain of the loop amplifier to approximately the maximum gain. - [Function] The amplitude of the signal demodulated by the PLL is inversely proportional to the frequency modulation sensitivity of the voltage controlled oscillator. , you can know whether the frequency modulation sensitivity of the voltage controlled oscillator has changed. Now, if the frequency modulation sensitivity of the voltage-controlled excavator doubles, the PL
The demodulated signal amplitude in the L loop becomes +. At this time, PL
The loop gain of L is twice according to equation +11. Therefore, if the gain of the loop amplifier is controlled sufficiently, the loop gain can be returned to the level before the frequency modulation sensitivity of the voltage controlled oscillator changes. Here, if we focus on the signal amplitude before and after the loop amplifier, the signal amplitude on the side connected to the voltage controlled oscillator, that is, the output side of the loop amplifier, remains the original + due to the frequency modulation sensitivity of the voltage controlled oscillator. However, since the gain of the loop amplifier is controlled to +, the input side of the loop amplifier returns to the value before the change. From the above, a demodulated signal is output from the input side of the loop amplifier, a specific signal whose amplitude does not change within this demodulated signal is detected by the amplitude detection circuit, and is compared with a preset amplitude value by the amplitude comparator to compare the amplitude. The gain of the loop amplifier in the PLL loop is controlled using the error voltage obtained by the circuit, and the signal amplification before the loop amplifier, that is, the specific signal amplitude mentioned above, is controlled to be constant, so the loop gain of the PLL is constant. , and the amplitude of the demodulated signal output from the input side of the loop amplifier is related to the change in the frequency modulation sensitivity of the voltage-controlled excavator (obtained with a constant demodulation sensitivity. Also, the amplitude of the demodulated signal output from the input side of the loop amplifier is related to the change in frequency modulation sensitivity of the voltage-controlled excavator (obtained with a constant demodulation sensitivity. By fixing the gain of the loop amplifier during the signal drop period and setting it to the maximum gain, it is possible to prevent the above-mentioned control malfunction, and to expand the pull-in frequency width and speed up the PLL pull-in operation during the same period. .

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is a diagram showing the basic configuration of the present invention, in which a PLL is formed by a voltage controlled oscillator 1, a phase comparator 2, a low-pass filter 5, and a loop amplifier 4, and the other input of the phase comparator 2 is A band pass filter 5 is connected to a detector 20, an AGC 21 is connected to the input of the band pass filter 5 and is controlled by the output of the detector 20, and the demodulated signal of the PLL is output from the input side of the loop amplifier 4. The demodulated signal is branched and inputted to an amplitude detection circuit 6 that detects a specific signal whose amplitude does not change within the demodulated signal, and the output of the amplitude detection circuit 6 and the output of the amplitude setting circuit 7 are inputted to an amplitude comparator 8. The output of the amplitude comparator 8 and the output of the fixed voltage generator 25 are input to the switch 22, and the output of the switch 22 is input to the loop amplifier 4.
The switch 22 is connected to the OR circuit 25 which outputs the logical sum of the channel selection signal from the channel selection pirate (not shown) and the output of the threshold circuit 24 to which the output of the detector 20 is input. Output selectively with output. The amplitude detection circuit 6 detects a specific signal whose amplitude does not change in the demodulated signal, such as a synchronization signal of the image signal, and outputs an amplitude value of 7, which is compared with the output of the amplitude setting circuit 7 by the amplitude comparator 8. , the difference is fed back to the loop amplifier 4. The amplitude comparator 8 can be easily constructed using a differential amplifier circuit. Further, the output of the fixed voltage generator 25 is applied to the loop amplifier by the switch 22 when the output of the detector 20 is below a certain threshold value, that is, when there is no signal, or when the power of the receiver is turned on, or during channel selection. The control of the switch 22 is such that when there is no signal, the output of the threshold circuit 24 is 1, and when the receiver is powered on, the tuning signal output from the tuning circuit becomes 1 while tuning is in progress, and these are output by the OR circuit 25. When the output of the OR circuit 25 is 1, the fixed voltage generator 25 is selected.

FIG. 1 is a diagram showing another embodiment of the present invention, in which a tuning circuit 9
The configuration is such that the free-running excavation frequency of the voltage controlled oscillator and the center frequency of the bandpass filter are varied to match and receive a desired signal.

FIG. 5 shows another embodiment of the present invention, in which a tuning circuit 9 includes a tuning voltage generation circuit 10, a detuning detection circuit 11, and a tuning voltage generation circuit 1.
The output of 0 and the output of the abuse detection circuit 11 are added and input to the voltage controlled oscillator. The detuning detection circuit constitutes an AFC circuit by detecting the direction and magnitude of detuning based on the average DC voltage of the demodulated output of the PLL or the DC component of a specific signal, and feeding back the output to the tuning voltage.

FIG. 4 shows another embodiment of the present invention, in which the tuning circuit 9 includes a reference frequency generator 12 that generates a reference frequency, a programmable divider 15 that divides the output of a voltage controlled oscillator, and a second
A programmable divider 15 is provided with a low-pass filter 14 and a second phase comparator to set the center frequency of a PLL tuning circuit that shares a voltage-controlled oscillator and a band-pass filter 5.
The control circuit 16 is configured to perform control according to a program code input to the control circuit 16.

FIG. 5 shows another embodiment of the present invention, in which the signal is suppressed or irregular, such as scrambled satellite broadcasting or high-definition broadcasting, and the specific signal input to the amplitude detection circuit 6 is easily If separation is not possible, a timing pulse of a specific signal is output from the signal processing circuit 17 that processes the demodulated signal,
The timing pulse allows detection of a specific signal whose amplitude does not change within the demodulated signal.

〔Effect of the invention〕

According to the present invention, even if the frequency modulation sensitivity of the voltage controlled oscillator in the PLL differs depending on the receiving channel, the loop gain of the PLL remains constant and does not change, and FM demodulation can be performed under stable loop conditions. Further, the amplitude of the demodulated signal output from the input side of the loop amplifier in the PLL is obtained with constant demodulation sensitivity regardless of changes in the frequency modulation sensitivity of the voltage controlled oscillator in the PLL, and stable signal processing can be performed. Furthermore, during the reception channel selection period and the reception signal dropout period, the frequency width of the PLL pull-in operation is expanded, which has the effect of speeding up the operation.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a block diagram showing the basic configuration of the present invention, FIG. 5 is a block diagram showing another embodiment of the present invention, and FIG. 4 is a block diagram showing the basic configuration of the present invention. Block Diagram Showing Another Embodiment of the Invention FIG. 5 is a block diagram showing another embodiment of the invention. 1...Voltage controlled oscillator 2...Phase comparator 5...Low pass filter 4...Loop amplifier 5...Band pass filter 6...Amplitude detection circuit 7...Amplitude setting circuit 8...・Amplitude comparator 9...Tuition selection circuit 20...Detector 21...AGC circuit 22...Switch 25...Fixed voltage generator 24...Threshold circuit 25...OR circuit

Claims (1)

[Claims] 1. Phase comparator, voltage controlled oscillator, low pass filter,
F, which is composed of a phase locked circuit consisting of a loop amplifier and a bandpass filter connected to the input of the phase comparator.
In the M receiver, a desired signal is received by varying the free-running oscillation frequency of the voltage-controlled oscillator and the center frequency of the band-pass filter to coincide with each other using a tuning circuit equipped with means for tuning and stabilizing the tuning frequency. The configuration includes an amplitude detection circuit that inputs the demodulated signal output from the input side of the loop amplifier and detects the amplitude of the demodulated signal, and an amplitude comparator that inputs the output of the amplitude detection circuit and compares it with a set amplitude value. It is characterized by comprising a switch for selectively outputting an output and a fixed voltage, means for controlling the gain of the loop amplifier according to the output of the switch, and means for setting the output of the switch to a fixed voltage during a tuning period or a period when there is no received signal. FM receiver.