JPS63236178A - Multiplying circuit - Google Patents

Multiplying circuit

Info

Publication number
JPS63236178A
JPS63236178A JP6986087A JP6986087A JPS63236178A JP S63236178 A JPS63236178 A JP S63236178A JP 6986087 A JP6986087 A JP 6986087A JP 6986087 A JP6986087 A JP 6986087A JP S63236178 A JPS63236178 A JP S63236178A
Authority
JP
Japan
Prior art keywords
circuit
temperature
temperature coefficient
bias current
multiplying circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6986087A
Other languages
Japanese (ja)
Inventor
Haruo Watanabe
晴夫 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to JP6986087A priority Critical patent/JPS63236178A/en
Publication of JPS63236178A publication Critical patent/JPS63236178A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To constitute an analog multiplying circuit having high accuracy, which is not influenced by a variation of an ambient temperature, by using a simple temperature compensating circuit. CONSTITUTION:A temperature compensating circuit (b) is inserted into a bias current circuit. That is, when the temperature compensating circuit (b) is used, a bias current Ia can be shown by Ia=VL/R3. In this regard, VL and R3 denote a fixed potential of a point L, and a constant of a resistance 20, respectively. A proportional constant K is K=RLXR3/(R1XR2XVL). In this case, VL denote a (+) input terminal voltage, namely, a fixed voltage having no temperature coefficient of an operational amplifier 21, and on the other hand, the resistances RL, R1, R2 and R3 can have the same temperature coefficient, respectively, since they are formed by using the same diffused resistor, in case of forming this multiplying circuit by an IC. Accordingly, the temperature coefficient can be canceled by a numerator and a denominator, and the proportional constant K of the multiplying circuit has no temperature coefficient.

Description

【発明の詳細な説明】 本発明は湿度補償回路を備えた掛算回路に関するもので
ある。従来半導体集積回路(IC>に形成されるマルチ
プレイヤ方式等のアナログ掛算回路はその演算出力(比
例定数)に内部抵抗或はバイアス電流の大きな温度係数
が影響し、正確な演算出力を得ることが困難であった。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiplication circuit with a humidity compensation circuit. Conventionally, analog multiplication circuits such as multiplayer type multipliers formed on semiconductor integrated circuits (IC) are affected by internal resistance or a large temperature coefficient of bias current on their calculation output (proportionality constant), making it difficult to obtain accurate calculation output. It was difficult.

本発明は、温度補償回路によって、lI)算回路の比例
定数の温度係数を零にして、周囲゛温度に影響されるこ
とのない掛算回路を構成することを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to use a temperature compensation circuit to make the temperature coefficient of the proportionality constant of the II multiplication circuit zero, thereby configuring a multiplication circuit that is not affected by the ambient temperature.

以下図面を用いて本発明を説明する。The present invention will be explained below using the drawings.

第1図は、本発明の(−)実施例回路図であり、イは、
掛算主回路、口は、温度補償回路である。
FIG. 1 is a circuit diagram of a (-) embodiment of the present invention;
The main multiplication circuit is the temperature compensation circuit.

図において1.2,8,9.12,16,17゜20.
22.23は夫々抵抗、3.4.5.6゜7.10.1
3,14.15.18.19は、NPN型トランジスタ
21は、差動増巾回路(以下オペアンプ)11は、電流
源である。
In the figure: 1.2, 8, 9. 12, 16, 17° 20.
22.23 are the respective resistances, 3.4.5.6°7.10.1
3, 14, 15, 18, and 19, the NPN transistor 21 and the differential amplifier circuit (hereinafter referred to as an operational amplifier) 11 are current sources.

この回路の動作は、端子A−B間に、電源電圧を印加し
、端子E−F間に入力電圧V inlを印加し、又端子
G−H@に、入力電圧Vin−2を印加すルト、c−o
間に、出力電圧Vo  (3111出力)が発生する。
The operation of this circuit is to apply a power supply voltage between terminals A and B, apply an input voltage Vinl between terminals E and F, and apply an input voltage Vin-2 to terminals GH@. , c-o
During this time, an output voltage Vo (3111 output) is generated.

この時、入力電圧と出力電圧との関係は、次式で表わさ
れる。
At this time, the relationship between the input voltage and the output voltage is expressed by the following equation.

VO−KxVin−1xVin−2++ (1)この式
でKは、比例定数であり、次式で表される。
VO-KxVin-1xVin-2++ (1) In this equation, K is a proportionality constant, which is expressed by the following equation.

K=RL / (R4xR2x Ia l   −(2
)たtごし、Rしは、抵抗(、及び抵抗2の定数であり
、R1は、抵抗8、及び、抵抗9の定数であり、R2は
抵抗16、及び抵抗17の定数であり、laは、K点を
流れる電流値(バイアス電流)である。
K=RL/(R4xR2x Ia l -(2
) and R are the constants of the resistors (and resistors 2, R1 is the constant of resistors 8 and 9, R2 is the constant of resistors 16 and 17, and la is the current value (bias current) flowing through point K.

ここで、このlL)算主回路イは、RL 、R1、R2
,laのそれぞれの温度係数によって決定される独自の
温度係数を持っている。
Here, this lL) main circuit I is RL, R1, R2
, la have their own temperature coefficients determined by their respective temperature coefficients.

そこで該バイアス電流1aを図中点線矢印に流れる如く
設定すると上述の温度ドリフトの問題が生じる。従って
本発明は簡単なll!度補償回路(ロ)を該バイアス電
流回路に挿入することにより上述の問題を解消したもの
である。即ち温度補償回路口を用いると、バイアスN流
1aは、次式によって表わすことができる。
Therefore, if the bias current 1a is set to flow in the direction of the dotted arrow in the figure, the above-mentioned temperature drift problem occurs. Therefore, the present invention is simple! The above-mentioned problem is solved by inserting a degree compensation circuit (b) into the bias current circuit. That is, using the temperature compensation circuit port, the bias N current 1a can be expressed by the following equation.

l a =VL /R3−(3) ただし、VLは、L点の固定電位、R3は、抵抗20の
定数である。
la =VL/R3-(3) where VL is a fixed potential at point L, and R3 is a constant of the resistor 20.

(3)式を(2)式に代入すると に−RLxR3/ (R1xR2xVL )−(4)こ
こで、VLは、オペアンプ21の(+)入力端子電圧即
ち温度係数を持たない固定電圧であり、一方抵抗RL 
、 R4、R2、R3は、このIft譚回路をICで作
る場合、同じ拡散抵抗を使用して形成されるので夫々同
じ、温度係数を持つことができる。従って(4)式にお
い°て、これらの温度係数は、分子と分母とで、キャン
セルすることができ、掛算回路の比例定数には、温度係
数を持たないことになる。
Substituting equation (3) into equation (2), -RLxR3/ (R1xR2xVL) - (4) Here, VL is the (+) input terminal voltage of the operational amplifier 21, that is, a fixed voltage without a temperature coefficient; Resistance RL
, R4, R2, and R3 are formed using the same diffused resistor when this Ift circuit is formed using an IC, so they can each have the same temperature coefficient. Therefore, in equation (4), these temperature coefficients can be canceled between the numerator and denominator, and the proportionality constant of the multiplication circuit does not have a temperature coefficient.

第2図は本発明の他の実施例回路図で上記実施例と相違
するところはオペアンプ28の出力をトランジスタ24
.26、及び27より成るカレントミラー回路を介して
印加するようにしたものでありこれによっても同様な効
果を得ることができる。
FIG. 2 is a circuit diagram of another embodiment of the present invention, and the difference from the above embodiment is that the output of the operational amplifier 28 is connected to the transistor 24.
.. The voltage is applied via a current mirror circuit consisting of 26 and 27, and the same effect can be obtained by this.

以上の説明から明らかなように本発明によればm生な 温度補償回路を使用することによって周囲温度変化の影
響を受けない高精度のアナログ掛算回路を構成すること
ができるので特にIC化に好適である等実用上の効果は
大きい。
As is clear from the above description, according to the present invention, a high-precision analog multiplication circuit that is not affected by ambient temperature changes can be constructed by using a low-temperature compensation circuit, and is therefore particularly suitable for IC implementation. The practical effects are great.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図は本発明の実施例回路図である。 図において(会)は掛算主回路、(ロ)(ハ)イ は′6A度補償回路、21.28は差動増巾回路、19
.24はトランジスタである。
1 and 2 are circuit diagrams of embodiments of the present invention. In the figure, (A) is the main multiplication circuit, (B), (C)A is the '6A degree compensation circuit, 21.28 is the differential amplification circuit, and 19
.. 24 is a transistor.

Claims (1)

【特許請求の範囲】 差動増巾回路と、該差動増巾回路の(+)入力端子の電
位を固定する回路と該差動増巾回路の位 (−)入力端子及び出力端子間にエミッタ及びベースが
接続されたトランジスタと該トランジスタのエミック抵
抗を備え該トランジスタのコレクタ側を直接もしくはカ
レントミラー回路を介して掛算回路のバイアス電流経路
に接続するようにしたことを特徴とする掛算回路。
[Claims] A differential amplification circuit, a circuit for fixing the potential of the (+) input terminal of the differential amplification circuit, and a circuit between the (-) input terminal and the output terminal of the differential amplification circuit. A multiplication circuit comprising a transistor whose emitter and base are connected, and an emmic resistor of the transistor, the collector side of the transistor being connected to a bias current path of the multiplication circuit directly or via a current mirror circuit.
JP6986087A 1987-03-24 1987-03-24 Multiplying circuit Pending JPS63236178A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6986087A JPS63236178A (en) 1987-03-24 1987-03-24 Multiplying circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6986087A JPS63236178A (en) 1987-03-24 1987-03-24 Multiplying circuit

Publications (1)

Publication Number Publication Date
JPS63236178A true JPS63236178A (en) 1988-10-03

Family

ID=13414980

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6986087A Pending JPS63236178A (en) 1987-03-24 1987-03-24 Multiplying circuit

Country Status (1)

Country Link
JP (1) JPS63236178A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04181487A (en) * 1990-11-16 1992-06-29 Inter Nitsukusu Kk Cubing circuit
JP2010176436A (en) * 2009-01-30 2010-08-12 Fujitsu Semiconductor Ltd Square circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04181487A (en) * 1990-11-16 1992-06-29 Inter Nitsukusu Kk Cubing circuit
JP2010176436A (en) * 2009-01-30 2010-08-12 Fujitsu Semiconductor Ltd Square circuit

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