JPS63234494A - Dynamic type semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce a capacity coupling noise by connecting either of bit line pairs to a sense amplifier and separating the other one from the sense amplifier. CONSTITUTION:One bit line of the bit line pair constituted of odd number-th bit lines BL1 and the inverse of BL1 based on the sense amplifier activating signals phiso, and the inverse of phiso of a sense amplifier activating signal generating circuit SAG as a connecting and separating means is connected to the sense amplifier SA1 and the other bit line is separated from the SA1. Based on other sense amplifier activating signals phis1, and the inverse of phis1, one bit line of the bit line pair constituted of the even number-th bit lines BL2, and the inverse of BL2 is connected to the sense amplifier SA3 and the other bit line is separated from the SA3. Thereby, the capacity coupling noise resulting from the capacity between the adjacent bit lines can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a dynamic semiconductor memory device.

[Conventional technology]

No. 'y1m shows a conventional dynamic semiconductor memory device. In the figure, MC, MC is a memory cell composed of one MC5 transistor and one capacitor, and the memory cell MC has a bit line BL and a word line WL. has a bit line BL and a word line WL.

is connected. Q + and Q'1 are transfer gates, a column decoder CD is connected to each gate, and a bit 1ilBL is connected to the transfer gate Q1.
and the data input/output line I10 are connected to the transfer gate Q.
1 is connected to the bit line BL and the data output line I10. DCo and DC are dummy cells, and a dummy word line DWLo is connected to the dummy cell DCo, and a dummy word line D W L + is connected to the dummy cell DC. SA is a sense amplifier, and the bit lines BL, B
L and sense amplifier activation signal line φ8°φS are connected (see FIG. 8).

As shown in FIG. 9, each bit line has a resistance R to ground potential (fixed potential) via the cell plate or substrate.
c+, a capacitance C2 between paired bit lines, and a capacitance C3 between adjacent bit line pairs.

In the memory cells MC,, MC, a charge of Cm V cc (V cc write) is accumulated when it is at a high level (l()), and a charge of o (ova write) is accumulated when it is at a low level (L).
, that is, no charge is accumulated. Also, dummy cell D
It is assumed that a charge of C5vI,c/2 (for example, the capacitance of C3 includes Vcc/2 old) is accumulated in C,,DC,.

Next, the operation will be explained.

In FIG. 9, for example, the bit line BL.

If the memory connected to the bit line BL is selected, and the bit line BL,
When a dummy cell is connected to the bit line and the precharge level of the bit line is V,, /2, the potential VBL of the bit line BL is as follows. The potential vn, which is one in a hundred, is...
2) However, ΔVRLO is the potential fluctuation h1 of the bit line BL,
ΔV mouth is the amount of potential variation of bit MBL, ΔV nLl is the amount of potential variation of bit line BL, ΔVnL2 is bit line B
This is the amount of potential fluctuation of L2.

The difference between the potential VRLI and the potential VBI is expressed by the above formula (1).
, (2), formula (3) is obtained.

CI+62+03 +: At the time of H reading, -2 at the time of reading.

The first term on the right side of the above equation (3) is the original read potential difference,
The second term is the adjacent bit line BL a and bit line BL2
This is a noise component caused by the capacitance between .

(Problems to be Solved by the Invention) Since the conventional dynamic semiconductor memory device is configured as described above, when the bit line pitch is reduced in response to the demand for higher integration of memory elements, the distance between bit line pairs increases. Yong! IC
3 increases, the coefficient α of the above equation (3) decreases, γ increases, and the second term of the surface equation (3) increases.

As a result, there is a problem in that the read voltage difference decreases, the operating margin decreases, and malfunction occurs.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a dynamic semiconductor memory device that can reduce capacitive coupling noise caused by capacitance between adjacent bit lines.

[Means for solving problems]

A dynamic semiconductor memory device according to the present invention comprises: a number of word line pairs consisting of a first word line and a second word line; a plurality of bit lines intersecting these word line pairs; A memory cell is placed at the intersection of the word line No. 1 and the odd-numbered bit line, and the memory cell is connected to both lines.
A memory cell group consisting of a memory cell arranged at the intersection of the second word line and the even-numbered bit line and connected to both lines, and an adjacent odd-numbered bit line,
In addition, adjacent even-numbered bit lines each constitute a bit line pair, one bit line of each bit line pair is connected to a sense amplifier, and the other bit line is isolated from the sense amplifier. It has been established.

(Operation) The connecting/disconnecting means in the present invention connects one of the bit line pairs to a sense amplifier and separates the other from the same sense amplifier, thereby eliminating capacitive coupling noise caused by capacitance between adjacent bit lines. Reduce.

〔Example〕

FIG. 1 shows an embodiment of the invention. This dynamic semiconductor memory device is composed of a block 1 and a block 2.

In the figure, the first bit line BL and bit IQB
Ll is not connected, and the second #th bit line B
L2 and bit line BLJ are not connected. The third bit line BL and the bit line BL,° are connected via a transfer gate T1, and the fourth bit line BL2 and the bit line BL2' are connected via a transfer gate T'r. .

WL is a first word line, wt,i is a second word line, and both lines form a word line pair.

BLl, BLI are odd bit lines, BL2, BL2
are even-numbered bit lines, each of which intersects the word line pair. C01, CG2 are memory cells, and the first word 1iIWL and odd-numbered bit lines BL1.
It is placed at the intersection with BτT and connected to both lines. CI 1% CI2 is a memory cell that connects the word line WL of planar memory 2 and the even bit line BL or B
It is placed at the intersection of L2 and connected to both lines.

The memory cell c. ,,CG2. A memory cell group is constituted by c, , c, .

Adjacent odd-numbered bit lines BLI, BLI form a bit line pair, and adjacent even-numbered bit lines BL2 .
A bit line pair is formed by iτ. SAI and SA3 are sense amplifiers, and a bit line pair constituted by odd bit lines BLI and π1 knee is connected to the sense amplifier SAI, and on the other hand, even bit lines BL2 . A bit line pair constituted by B17 is connected. SAG is a sense amplifier activation No. 8 generation circuit as a connection/disconnection means, and a sense amplifier activation signal φ3
o, φso, the odd-numbered bit lines BL, ,
Of the bit line pair constituted by BL, one bit line is connected to the sense amplifier SAI, the other bit line is isolated from the sense amplifier SAI, and the other bit line is connected to the sense amplifier activation signal φ! +1, φs1, the even-numbered bit line BL2 . One bit line of the bit line pair constituted by BL2 is connected to the sense amplifier SA3, and the other bit line is isolated from the sense amplifier SA3. A transfer gate I2 controls the connection between the bit line BL, the sense amplifier SAI, and the precharge transistor PT based on the transfer gate signal φ7□. T; is a transfer gate, and based on the transfer gate signal φ1, the bit line BL2 and 1! It controls the connection between the sense amplifier SA3 and the precharge transistor PT2.

The solid lines in FIGS. 2(f) and 2(g) indicate when block 1 is selected, and the broken lines indicate when block 2 is selected.

The bit line BL is connected to a sense amplifier SAI and a precharge transistor PT3, and the bit line BL2 is connected to a sense amplifier SA3 and a precharge transistor PT3.
Connected to 4.

The bit line BL is connected to the transistor for the sense amplifier SA2 and precharge PT5, and the bit line St,'
2 is connected to a sense amplifier SA4 and a precharge transistor PT8. The bit lines BL,' are connected to the sense amplifier SA2 via a transfer gate T3.
The bit line B L2' is connected to the sense amplifier SA4 and the precharge transistor P via the transfer gate Ta.
Connected to T8.

Next, the operation will be explained based on the timing chart shown in FIG.

FIG. 2(a) shows the external signal RAS, and FIG. 2(b) shows the precharge signal φPRO+φPRI.

When the word line WLo rises at (+) time*lt, the second bit lines BLI and BLI are connected to the memory cells C61 and CG2, respectively, and the memory cells C81 and CO2 are connected to the second bit line BLI and BLI, respectively. The accumulated signal charges appear on each bit line BL, , BLI.

At this time, since the transfer gate T is in the ON state, the bit lines B L+ , B L+ , B L+',
Potential change appearing in BLI' ΔVBL1, ΔV:, ΔV
nLI・, ΔV “destruction” is the stray capacitance of the bit line.
When B/2 is assumed, equations (4) and (5) are obtained.

However, +: When reading H from memory cell Col - 2 When reading L from memory cell C8l...------(5) However, +: When reading H from memory cell C62 -: When reading H from memory cell C62 -: When reading L from memory cell C62 Since CB/C5 is normally 10 to 20 during reading, the above formula (4
), from (5), bit line B is written by memory C0.
The signal potential appearing on bit lines BL, , Bτ7 by memory cell Co2 is approximately twice as high as the signal potential appearing on bit lines BL, .

(2) At time t2, as shown in FIG. 2(e),
Transfer gate signal φT1 falls and transistor T1 is turned off.

(3) After that, at time t3, as shown in FIG. 2(d), the sense amplifier activation signal φ,0 rises, and the sense amplifier activation signal φ,0 rises. stands. At this time, since the transfer gate signal φd2 is rising, the sensing operation of the sense amplifier SAI is started.

(4) Then, at time t4, as shown in FIGS. 2(e) to 2(g), transfer gate signal φ7. rose up,
Transfer gate signal φT2 falls. At this time,
Since the transfer gate signal φ73 is rising (see the solid line in the figure), the signal information of the memory cell Co2 detected and amplified by the sense amplifier SA2 is transferred to the bit line B.
The data δ is rewritten into the memory cell C62 through L.

FIG. 3 shows the potential appearing on each bit line. Figure 3 (a
) is when memory cell Col is H and memory cell CQ2 is L, FIG. 3(b) is when memory cell C8I is H and memory cell C62 is H, and FIG. 3(C) is memory cell C6.
1 and memory cell C02 is L, Fig. 3(d)
indicates the potential appearing on each bit line when memory cell Co1 is at H level and memory cell C82 is at H level. It can be seen from FIG. 3 that memory cell data is read and written.

Finally, the data in memory cell C8 is transferred to sense amplifier S.
The data of memory cell C02 is sent to AI by sense amplifier SA.
It is latched to 2. Furthermore, the original accumulated data is written into the memory cell Co2 via the bit line BL. Therefore, in this state, when the external signal τ茗 is raised again to end the cycle, for memory cells C01 and CO2,
Reading and rewriting of accumulated data, that is, a refresh operation will be performed.

■After that, when the external signal ττi is lowered, a column is selected by the column address, and data is outputted to the memory cell C61%co2 of the corresponding column, the same operation as normal is used to select the column from the memory cell C6, Data can be input and output to and from ,C,.

FIG. 4 shows a circuit diagram of the column selection system. The same or corresponding parts as in FIG. 7 are given the same reference numerals.

The effects of this embodiment will be described below.

(2) Due to the shielding effect of keeping every other bit line completely inactive (precharged state), capacitive coupling noise between activated bit lines can be almost completely eliminated.

■The charging/discharging current of the bit line is V. In the case of e/2 precharge method, if the sum of the stray capacitance of all the bit lines is ΣCR, and the cycle period is Tc, then 1/4 of the bit line is charged during sensing. v,,c/2 to v,,.

(6) Furthermore, during rewrite operation, even in the worst case, 1/8 of the bit lines are pulled up from the ground potential to Vo.

Since it is pulled up to , the total is ・・・・・・・・・・・・(8). Therefore, even if a write operation is performed, the maximum consumed F current is the same as in the conventional example.

(2) Since the sensing operation of this embodiment is exactly the same as that of the folded bit line system shown in FIG. 10, the canceling effect of common mode memory array noise is not impaired at all. In No. 1o11, circles indicate memory cells, and S indicates a sense amplifier.

In the above embodiment, the transfer gate signal φT2 rises after sufficient time is allowed between times t3 and t4, and after the potential appearing on the bit line is determined from the ground potential to the power supply potential (VC,). On the other hand, we have explained the case where the transfer gate signal φTl rises, but at additional time t
, and t4, the value of n'2 equation (7) becomes smaller than that of the above embodiment, and the current consumption can be reduced to approximately 1/2 compared to the conventional example.

FIG. 5 shows a second embodiment of the invention. The same or equivalent parts as in FIG. 1 are given the same reference numerals. The difference between this second embodiment and the first embodiment is that the sense amplifiers SA, . BL
2, and one of the bit lines of each bit line pair is connected to the sense amplifiers SA+ and SA2 by switches S, -S, and l. Figure 6 shows the switch signal φ. , φ1 is the external signal RAS,
Precharge signals φ, □, sense amplifier activation signal φ3
, φ3.

Since the second embodiment is configured as described above, it can achieve essentially the same effects as the first embodiment.

Furthermore, in this second embodiment, the chip occupation area can be reduced by reducing the number of sense amplifiers by half and doubling the sense amplifier pitch.

Furthermore, even if the present invention is applied to a dynamic semiconductor memory device having dummy cells, the same effects as in the above embodiments can be obtained.

(Effects of the Invention) As described above, according to the present invention, since one of the bit line pairs is connected to the sense amplifier and the other is separated from the sense amplifier, capacitive coupling noise can be reduced. It has the effect of being able to.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention. Second
The figure is a timing chart, and Figure 2 (a) shows the external signal R.
A diagram showing whether the precharge signal φPR
0, φPRI, FIG. 2(C) is the word line WLO
, WLz, ':JJ2 Figure (d) is the sense amplifier activation signal ψ sol ψ ffoh
ψ −11, ψ s+Y with sword] Shiku J, #7
(C) is the transformer tube gate signal φ7. The second diagram [) is a diagram showing the transfer gate signal φT2, and FIG. 2(g) is a diagram showing the transfer gate signal φ〒3. FIG. 3 is a diagram showing the voltage appearing on the bit line, and FIG. 3(a) shows that the memory cell C6I is the H1 memory cell C
3(b) when 62 is at L, and FIG. 3(C) when memory cell CQI is at H and memory cell CO2 is at H, memory cell C8, memory cell C02 is at L. of the time,
FIG. 3 (d> is memory cell C6,
2 is a diagram showing the potential appearing on each bit line when bit line 2 is H. FIG. FIG. 4 is a circuit diagram of a column selection system, and FIG. 5 is a diagram showing a second embodiment of the present invention. Figure 6 shows switch signals φ0, φI, external signal RAS, and precharge signal φP.
FIG. 6(a) is a diagram showing the external signal RAS, and FIG. 6(b) is a diagram showing the precharge signal φPR. (C
) is a diagram showing the switch signals φ0 and φ1, FIG. 6(d) is a diagram showing the sense amplifier activation signal φ3, and FIG. 6(e) is a diagram showing the sense amplifier activation signal T7. 7 is a diagram showing a conventional dynamic semiconductor memory device, FIG. 8 is a specific circuit diagram of the sense amplifier SA shown in FIG. 7, FIG. 9 is a diagram showing the stray capacitance of each bit line, and FIG. The figure shows a folded bit line structure. In the figure, WLo is the first word line, WL is the second word line, BL, BL2, BL+, BL2 are the bit lines, Co1. Co2, C11, C1□ are memory cells, S
A, ~SA4 are sense amplifiers, and SAG is a sense amplifier activation signal generation circuit. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] A plurality of word line pairs consisting of a first word line and a second word line, a plurality of bit lines intersecting these word line pairs, and odd-numbered bit lines with the first word line. a memory cell arranged at the intersection of the second word line and the bit line and connected to both lines; and a memory cell arranged at the intersection of the second word line and the even-numbered bit line and connected to both lines. The cell group and adjacent odd-numbered bit lines and adjacent even-numbered bit lines form bit line pairs, respectively.
1. A dynamic semiconductor memory device, comprising connecting/disconnecting means for connecting one bit line of each bit line pair to a sense amplifier and isolating the other bit line from the sense amplifier.