JPS6323419A - Programmable logic device - Google Patents

Abstract

PURPOSE:To contrive to attain large scale integration by separating an AND-OR constitution section and an input/output buffer section and connecting them optionally so as to make the method effective to a device requiring lots of input pins. CONSTITUTION:A metal line 6 is divided into five regions 6-l-6-5 by programmable switch groups 16-1-16-5. Further, the input/output lines 8, 10 of the AND-OR constitution blocks 2-1-2-3 are not concentrated on one signal metal line region but separated into plural metal line regions. In giving a signal outputted from an input/output buffer section block 4-1 to the input line 8 of the AND-OR constitution blocks 2-2, 2-3, it can be attained by having only to conduct the switch group 16-5. Thus, the part of signal flowing through the switch groups 16-1-16-5 on the metal line 6 is less and the required metal line length is reduced. Thus, the number of metal lines and of switch groups 16-1-16-5 is reduced to improve the signal tramsmission speed.

Description

Detailed Description of the Invention (Technical Field) The present invention includes an AND gate array and an OR gate array, and configures a desired logic circuit by programming one or both of them at the user's request. field programmable logic
It's about devices.

(Prior art) As field programmable logic devices, there are devices called PAL in which an AND gate array is programmable and an OR gate array is fixed, and
There is something called a PLA in which both the gate array and the OR gate array are programmable.

In a conventional field programmable logic device, an input line leading to an input buffer intersects a product term line of a portion including an AND gate array and an OR gate array (referred to as an AND-OR component), and the product term line and the input line intersect. A programmable element is provided at each intersection of the lines.

However, in a device that requires many input/output pins, the number of input lines increases, and the number of product term lines also increases.

As a result, there is a limit to the number of input/output pins due to chip area and number of gates.

In addition, as the number of product terms increases, the calculation speed decreases,
Furthermore, there is a problem that the unused portion of the AND-OR#I component also increases.

(Objective) The present invention removes constraints on the number of input/output bins by making the number of product terms in an AND-OR component independent of the number of input/output pins, thereby preventing a reduction in calculation speed, and The purpose is to increase the usage efficiency of the OR component.

The invention also aims to reduce the number of programmable memory elements.

(Structure) In the present invention, the AND-OR configuration section and the input/output bus sofa section are separated from each other, and the AND-OR@configuration section is not made into a single unit, but is divided into a plurality of small-scale units. Further, the AND-OR configuration section and the input/output buffer section can be arbitrarily connected.

That is, the field programmable logic device of the present invention includes a plurality of programmable AND-OR component blocks that include an AND gate array and an OR gate array and can arbitrarily configure a logic circuit;
A plurality of input/output buffer blocks having input/output buffers and a plurality of metal lines are provided in one semiconductor chip, and the input/output lines of each AND-OR component block and the individual output lines are provided in one semiconductor chip. The input/output lines of the cover sofa block intersect with each of the metal lines, and each intersection is provided with a switch that can set the electrical connection on or off, and is connected to the input/output lines. The switch is configured to be controlled by a programmable memory element via a decoder.

Examples will be specifically described below.

FIG. 1 represents one embodiment of the invention.

2-1 to 2-3 are programmable AND-OR configuration blocks that include an AND gate array and an OR gate array and can arbitrarily configure a logic circuit, and 4-
1 to 4-12 are input/output buffer unit blocks provided with input/output buffers. 6 are AND-OR component blocks 2-1 to 2-3 and input/output buffer blocks 4-1 to 4
- 12, and a plurality of metal lines 6 (for example, 12 lines) are arranged in parallel,
AND-OR structure between the gob 0 blocks 2-1 to 2-3 and the input/output bus sofa blocks 4-1 to 4-12.
-OR component is provided so as to surround the blocks 2-1 to 2-3.

A programmable switch is provided at each intersection of the input line 8 (solid line) of the AND-OR component block 2-1 to 2-3 and the metal line 6.

A programmable switch is also provided at each intersection of the output line 10 (broken line) of the AND-OR component blocks 2-1 to 2-3 and the metal line 6. In addition, programmable switches are provided at each intersection of the input line (solid line) 12 of the crowd cover sofa block 4-1 to 4-12 and the metal line 6, and the input/output buffer block 4
A programmable switch is also provided at each intersection of the output lines (broken lines) 14 from -1 to 4-12 and the metal line 6.

Metal line 6 is an arbitrary AND-OR component block 2
-1 to 2-3 and any input/output buffer block 4-1
~4-12 in a suitable area 6 to make a connection between
A programmable switch group 16-1 to 16-5 is provided so as to be divided into groups 16-1 to 6-5.

To briefly explain the signal flow in this embodiment, external signals coming from the input/output bin are input to the input buffer section block 4.
Output line 14 via input buffers from -1 to 4-12
Go out. This output line 14 is connected to a metal line 6 running nearby, and is connected to a group of programmable switches 16-1 to 16-1.
Any AN by turning 16-5 on or off.
Input line 8 of D-OR component blocks 2-1 to 2-3
reach. Conversely, AND-OR component block 2-1~
The signals converted in 2-3 are AND-ORed in the same way.
Any input/output bus sofa section block 4-1 connected to the nearby metal line 6 from the output line 10 of the component blocks 2-1 to 2-3 and designated by a programmable switch group 16-1 to 16-5. ~4-12 input line 1
Connected to 2. And input/output buffer block 4
Signals can be output to the outside via the output sofas in -1 to 4-12.

Next, FIG. 2 shows an example of the internal configuration of the AND-OR component blocks 2-1 to 2-3.

This basic configuration is the same as conventional PAL <AND-OR([
), and the AND gate array part is EF
ROM process technology allows the user to perform programming.

An input line 20 that transmits an input signal in an inverted or non-inverted manner.
intersects the product term fi22 connected to the AND sense circuit 24. At each intersection of input line 20 and product term line 22 there is a programmable element, such as an EFROM, which can be programmed in an AND gate array. The output of the AND sense circuit 24 is the OR circuit 2
Connected to 6. The output from the AND-OR logic circuit section is connected to the input of the D-type flip-flop 28 and also to one input terminal of the switch 30. The other input terminal of the switch 30 is connected to the Q output terminal of the flip-flop 28, so that the switch 30 allows the output from the AND-OR logic circuit to pass through the flip-flop 28 or directly to the AND-OR component. You can choose whether to output it outside the block. The flip-flop 28 is provided with a set terminal 32 and a reset terminal 34. These terminals can be programmed simultaneously when programming the AND gate array. Further, as the clock for the flip-flop 28, either an internal clock or an external clock can be selected by a switch 36.

A feedback line 38 is provided in this AND-OR logic circuit section. One input terminal of the switch 40 connected to the feedback line 38 has an AND-OR
The output of the OR circuit 26 of the logic circuit section is connected, and the Q output terminal of the flip-flop 28 is connected to the other input terminal, so that the output of the AND-OR logic circuit section can be directly connected to the flip-flop 28 by the switch 40. Feedback can be provided via 28. This AND-O
The input terminal of the R component block is connected to input line 8 and the output terminal to output line 10.

Next, an example of the configuration of the input/output buffer blocks 4-1 to 4-12 is shown in FIG.

The basic configuration of the crowd cover sofa section blocks 4-1 to 4-12 is an input buffer 42, an output buffer 44, and a D-type flip-flop 46 that synchronizes external input signals.

The input terminal of the input buffer 42 is connected to the input/output pin 48, and the output terminal of the input buffer 42 is connected to the flip-flop 4.
6 and one input terminal of the switch 50.

A flip-flop 4 is connected to the other input terminal of the switch 50.
The output terminal to which the output terminal 6 is connected and connected to the switch 50 is connected to the output line 14.

A switch 52 is connected to the input terminal of the output buffer 44, and one input terminal of the switch 52 is connected to the input line 1.
2, and the other input terminal is connected to the input terminal via an inverter 54. The output terminal of output buffer 44 is connected to input/output pin 48.

Further, a switch 56 is connected to the control terminal of the output buffer 44, and the first input terminal of this switch 56 is connected to the power supply (
Vcc), the second input terminal is connected to the tri-state enable signal input terminal, and the third input terminal is connected to ground.

In this input/output buffer block, input/output pin 4
8 is used as an input pin, the signal input from the input/output pin 48 is passed through the input buffer 42, and a switch 50 selects whether to synchronize with another input signal (I10 clock) or input it independently. can do. The clock of the flip-flop 46 is common to that of other cover sofa blocks, and the input signals can be synchronized by the lock line 58.

When the input/output pin 48 is used as a connector pin, the polarity of the signal coming in from the input line 12 can be selected by a switch 52, and the output signal can be further controlled by a switch 56. Programmable switch group 16- provided for dividing
An example of the configuration of Nos. 1 to 16-5 is shown in FIG.

Transmission gate 6 in the middle of each metal line 6
0 is provided, and whether or not the transmission gate 60 is turned on or off is determined depending on whether programming is performed on the EPROM connected to each transmission gate. When the transmission gate 60 is on, the signal passing through the metal line 6 passes through as is, and when it is off, the signal can be separated using the transmission gate 60 as a boundary.

Next, FIG. 5 shows the metal line 6, the input line 8 and the output line 1 of the AND-OR component blocks 2-1 to 2-3.
0. and input/output buffer 7 blocks 4-1 to 4-12
An example of the configuration of a programmable switch provided at the connection point with each of the input line 12 and output line 14 is shown.

A transmission gate 62 is connected to each intersection of the metal line 6 and the input line 8 (12) or the output line 1.0 (14), and each transmission gate 62 is controlled to be turned on or off by a decoder 64. Only when the transmission game 62 is on, the input line 8 (12) or the output line 10 (14) is connected to the metal line 6, and signals are input and output.

1 of input line 8 (12) or output line 1O (14)
Since the book is connected to only one of the metal lines 6 that intersect with it, the number of EPROMs required can be reduced by using the decoder 64. That is, in this example, if one bit of EPROM is used for one transmission gate 62, the number of bits of EPROM required is 8, but by using the decoder 64, this input/output line is not used. Even if an enable terminal 66 is added for use in this case, the required EPROM can be reduced to 4 bits. Also,
In the example in Figure 1, if a decoder is not used, the required EP
The number of bits of the ROM is 924 bits including the programmable switches 16-1 to 16-5 on the metal line 6, but in the example of FIG.
1 to 4-12 and AND-OR component block 2-1
If decoders were used at the intersections of all input/output lines ~2-3 and metal line 6, the number of EPROM bits required would be reduced by 348k.

Returning to FIG. 1, in this embodiment, the metal line 6 is divided into five regions 6-1 to 6-5 by programmable switch groups 16-1 to 16-5. The input/output lines 8, 10 of the AND-○R component blocks 2-1 to 2-3 are not concentrated in a single metal line area, but are dispersed over a plurality of metal line areas.

Now, to explain the case where it is necessary to input the signal output from the input/output buffer section block 4-1 to the input line 8 of the AND-OR component block 2-2 and 2-3, this embodiment will be described. Then, it is sufficient to simply make the switch group 16-5 conductive. On the other hand, if we assume that all the input lines 8 of the AND-OR component block 2-2.2-3 intersect with the metal line 6 in the metal line region 6-2.6-3, respectively: Crowded Hippo Sofa Block 4-1
AND-OR component block 2-2.2-
In order to input to the input line 8 of 3, switch group 16-
Three groups of switches 1 to 16-3 must be made conductive.

As described above, in this embodiment, one signal from one cover sofa block 4-1 to 4-12 is processed by multiple AND signals.
- For input signals of OR9 component blocks 2-1 to 2-3 or for connections between AND-OR component blocks separated by distance, switch group 16- on metal line 6
1 to 16-5, and the required metal line length is also shortened, so the number of metal lines and the number of switch groups 16-1 to 16-5 can be reduced. It is possible to improve the signal transmission speed.

In the above embodiment, the programmable storage elements of the AND-'OR component blocks 2-1 to 2-3 and the rewritable E as the storage elements of the programmable switch.
Although PROM is used, other rewritable storage elements such as EEPROM may also be used, and fuse elements that are not rewritable but programmable may also be used.

(Effects) In conventional field programmable logic devices, as the number of input/output pins increases, the number of product terms in the AND-OR component also increases. The number of terms also becomes enormous, and there are limits to the chip area and the number of gates.

In contrast, in the present invention, the AND-OR configuration section and the input/output buffer section are separated from each other, and the AND-OR configuration section and the input/output buffer section are separated from each other.
The OR component is not made into a single unit, but is divided into multiple small-scale components, and the AND-OR component and the input/output buffer can be arbitrarily connected via metal lines. Because I did.

Because the number of product terms inside the AND-OR configuration is unrelated to the increase in the number of input/output pins, it is very effective for devices that require multiple input pins, and the number of gates is also comparable to conventional field programmable devices. - Can be scaled up compared to logic devices. Moreover, EPROM technology and
EPROMEPROM technology is programmable on the user side, which can significantly reduce development costs and shorten development time.

In addition, the input/output lines and A
Since a decoder method is adopted to control the connection between the input/output lines of the ND-OR component block and the metal lines, the number of necessary programmable memory elements can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a circuit diagram showing an example of the AND-OR component block in the same embodiment, FIG. 3 is a circuit diagram showing an example of the input/output buffer 7 block in the same embodiment, and FIG. 4 is a circuit diagram showing an example of the input/output buffer 7 block in the same embodiment. A circuit diagram showing an example of a programmable switch in a metal line. FIG. 5 is a circuit diagram showing an example of a programmable switch provided at a connection point between a metal line and an input/output line in the same embodiment. 2-1 to 2-3... AND-OR component block, 4-1 to 4-12... Crowd cover sofa block. 6...Metal line, 8...Input line of AND-ORi component block, 10...Output line of AND-OR component block, 12... - Input line of input/output buffer section block, 14... Output line of input/output buffer section block, 16... programmable switch, 64... decoder.

Claims (1)

[Claims] (1) Multiple programmable AND-OR component blocks that include an AND gate array and an OR gate array and can arbitrarily configure a logic circuit, and multiple input/output buffer blocks that include an input/output buffer. and a plurality of metal lines are provided in one semiconductor chip, and the input/output lines of each AND-OR component block and the input/output lines of each input/output buffer block are connected to the respective metal lines. each intersection is provided with a switch that can set the electrical connection on or off, and the switch connected to the input/output line is a memory element programmable via a decoder. programmable control controlled by
logic device.