JPS63232573A - Threshold deciding circuit - Google Patents

Threshold deciding circuit

Info

Publication number
JPS63232573A
JPS63232573A JP62065472A JP6547287A JPS63232573A JP S63232573 A JPS63232573 A JP S63232573A JP 62065472 A JP62065472 A JP 62065472A JP 6547287 A JP6547287 A JP 6547287A JP S63232573 A JPS63232573 A JP S63232573A
Authority
JP
Japan
Prior art keywords
threshold level
level
threshold
rom
picture element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62065472A
Other languages
Japanese (ja)
Inventor
Shinji Kaizuka
眞二 海塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62065472A priority Critical patent/JPS63232573A/en
Publication of JPS63232573A publication Critical patent/JPS63232573A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To remarkably simplify a threshold deciding circuit, by reading out the threshold level corresponding to a notable picture element position from a memory after the level is once stored in the memory and correcting the level by moving it upward or downward by means of a level changing means in corresponding to the designation of the density at the time of reading an original. CONSTITUTION:A ROM 11 for outputting threshold level which inputs levels of picture elements P, Q, R, and S in the vicinity of a notable picture element A and decides at which threshold level the notable picture element is binary coded, is provided. The ROM 11 reads out the threshold level of the notable picture element A from the correlation among the picture elements P, Q, R, and S. With respect to the output of the ROM 11, the process of the density mode designated at the time of reading an original is performed by means of a density switching device 12 in such a way that, when the density mode is designated to 'dark', the threshold level is lowered and, when designated to 'light', the threshold level is raised. In other words, the threshold level is decided by means of the combination of the ROM 11 and switching device 12 and binary signals are produced after the threshold level is com pared with the notable picture element A at a comparator 13. Therefore, this circuit is made smaller in size and simpler in constitution. In addition, this circuit can be changed easily.

Description

【発明の詳細な説明】 〔概 要〕 本発明は、原稿の注目画素に対し近傍の画素のレベルを
入力して2値化回路にしきい値を与える場合に、注目画
素の近傍の複数の画素のレベルを入力して注目画素位置
に対するしきい値レベルなメモリに格納し、さらにこれ
を読出し原稿読取時の濃淡の指定に応じレベル切替手段
でレベルを下げまたは上げるように設定する。これによ
シ、簡単で変更容易な構成によ〕しきい値を出力できる
[Detailed Description of the Invention] [Summary] The present invention provides a method for inputting the levels of neighboring pixels to a pixel of interest on a document to provide a threshold value to a binarization circuit. The level is inputted and stored in a memory that is a threshold level for the pixel position of interest, and then read out and set to lower or raise the level using a level switching means in accordance with the specification of shading when reading an original. This makes it possible to output a threshold value with a simple and easily changeable configuration.

〔産業上の利用分野〕[Industrial application field]

本発明は、画像読取装置によシ原稿をライン走査し注目
画素に対するしきい値を求め2値化回路に与えるしきい
値決定回路に関するものでアラ。
The present invention relates to a threshold value determination circuit that scans a line of a document using an image reading device, determines a threshold value for a pixel of interest, and supplies the threshold value to a binarization circuit.

〔従来の技術〕[Conventional technology]

従来、ファクシミリ装置の原稿読取部に用いる画像読取
装置において、原稿を走査し2値化回路で2値化する場
合、シキい値を与えるしきい値決る。
Conventionally, in an image reading device used in a document reading section of a facsimile machine, when a document is scanned and binarized by a binarization circuit, a threshold value is determined to give a sharp value.

すなわち、ライン走査における同図(5)に示す3×3
画素列の窓で、中心人と上下PR,左右QBをたとえは
4ビツトレベルで表わす。
In other words, 3×3 shown in (5) in the same figure in line scanning
For example, the center person, upper and lower PRs, and left and right QBs are represented at a 4-bit level using a window of pixel columns.

同図(6)の構成図で、これら各P、Q、R,SとAの
lzヘルヲソttt’tt減gl)(1) 1 、 (
If)2 、 (1103、QV)4 Vc大入力て差
を求め、加算器5に入れて加算し、係数乗算器6で所定
係数と乗算する。
In the configuration diagram in (6) of the same figure, each of these P, Q, R, S and A is shown in the diagram (1) 1, (
If) 2 , (1103, QV) 4 Vc large input, calculate the difference, put it in the adder 5 and add it, and multiply it by a predetermined coefficient in the coefficient multiplier 6.

その結果、注目画素に対する周囲画素の影響を示す値が
得られる。
As a result, a value indicating the influence of surrounding pixels on the pixel of interest is obtained.

次に加算器7でこの値と注目画素人とを加算し、この合
成値を比較器8に入れ別に設定したしきい値レベルと比
較し2値信号を出力する。
Next, an adder 7 adds this value to the pixel of interest, and this combined value is entered into a comparator 8 and compared with a separately set threshold level to output a binary signal.

同図(6)は他の構成図を示したもので、同図(6)の
減算器(1) 1 、 (II) 2・・・等と加算器
5の間に係数乗算器(1) ? 、 (n) 10等を
挿入したものである。すなわち、周囲画素の影響がP、
Q、R,Sで異なる場合に適合した方法である。
Figure (6) shows another configuration diagram, in which a coefficient multiplier (1) is installed between the subtracters (1) 1, (II) 2, etc. in figure (6) and the adder 5. ? , (n) with 10 etc. inserted. That is, the influence of surrounding pixels is P,
This method is suitable for cases where Q, R, and S are different.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記従来の構成においては、第3図(6)に示すように
、しきい値レベルは終始一定であシ、注目画素に対し周
囲の4画素の影響が加味されこれを元に適当なレベルが
設定されて2値信号が作成される。このように注目画素
の周囲の画素配列が変化しても、それを加味した最適の
2値信号が作成されることになシ、その点では問題ない
が、同図(6)に示したように、構成が、2値信号を発
生する比較器8の前に4つの減算器1〜4と2つの加算
器5.7と係数乗算器6をもたなければならず回路規模
が大きく複雑となる欠点がある。
In the above conventional configuration, as shown in FIG. 3 (6), the threshold level is constant from beginning to end, and the influence of the four surrounding pixels is added to the pixel of interest, and an appropriate level is determined based on this. is set to create a binary signal. Even if the pixel arrangement around the pixel of interest changes in this way, an optimal binary signal will not be created that takes this into account, and there is no problem in that respect, but as shown in Figure (6). In addition, the configuration has to have four subtracters 1 to 4, two adders 5.7, and a coefficient multiplier 6 before the comparator 8 that generates a binary signal, making the circuit large and complicated. There is a drawback.

本発明者は、従来の方法がしきい値レベルを一定にして
、注目画素と周囲画素とのレベル差を可変とするのに対
し、本発明では、注目画素のしきい値レベルを周囲画素
を元に可変設定することとし、これらのデータをメモリ
に格納しておき、それを用いることKよシ、構成を格段
に簡略化できることに着目した。
The present inventor discovered that while the conventional method keeps the threshold level constant and makes the level difference between the pixel of interest and surrounding pixels variable, in the present invention, the threshold level of the pixel of interest is We focused on the fact that the configuration can be greatly simplified by making the settings variable and storing these data in memory and using it.

本発明のi的は、注目画素位置の周囲画素を元にしきい
値レベルを可変設定し出力するメモリを設けたしきい値
決定回路を提供することにある。
An object of the present invention is to provide a threshold determining circuit provided with a memory for variably setting and outputting a threshold level based on surrounding pixels of a pixel of interest position.

〔問題点を解決するための手段〕[Means for solving problems]

前記目的を達成するため、本発明においては、原稿の注
目画素に対し近傍の画素のレベルを入力して2値化回路
にしきい値を供給する場合に、注目画素位置に対するし
きい値レベルをメモリに格納し、さらにこれを読出し原
稿読取時の濃淡の指定に応じレベル切替手段でレベルを
下げまたは上げるように修正するものである。
In order to achieve the above object, in the present invention, when inputting the level of a pixel in the vicinity of a pixel of interest on a document and supplying a threshold value to a binarization circuit, the threshold level for the pixel of interest position is stored in a memory. This is then read out and modified to lower or raise the level using a level switching means in accordance with the specification of shading when reading the original.

〔作 用〕[For production]

上記構成によシ、第1図の原理説明図に示すように、注
目画素位置の周囲の4画素P、Q、R,S レベルをメ
モリに入力し、対応するしきい値を読出し、原稿読取時
の濃淡切替を行ない修正されたしきい値が得られる。
According to the above configuration, as shown in the principle explanatory diagram of FIG. A revised threshold value is obtained by switching between shades of time.

〔実施例〕〔Example〕

第2図は本発明の実施例の構成説明図である。 FIG. 2 is an explanatory diagram of the configuration of an embodiment of the present invention.

同図において、注目画素人の近傍画素P、Q、R,Sレ
ベルを入力して、注目画素をどのしきい値レベルで2値
化するかというしきい値レベル出力用のROM 11を
設ける。このROM 11は、近傍画素P、Q。
In the figure, a ROM 11 is provided for inputting the P, Q, R, and S levels of neighboring pixels of the pixel of interest and outputting a threshold level at which threshold level the pixel of interest should be binarized. This ROM 11 stores neighboring pixels P and Q.

R,Sの相関関係よシ注目画素のしきい値レベルを読出
すことができる。このROM 11の出力に対し、原稿
読取時に指定した濃淡モードの処理を濃淡切替器12に
より行なう、濃淡モードを「濃く」と指定したときはし
きい値レベルを下げるように、「うすぐ」と指定したと
きはしきい値レベルを上げるようにする。すなわち、R
OM11と濃淡切替器12との組合せでしきい値レベル
を決定し、このしきい値レベルと注目画素Aとを比較器
13によシ比較し、2値信号を作成する。
The threshold level of the pixel of interest can be read out based on the correlation between R and S. For the output of this ROM 11, the density switcher 12 performs processing in the density mode specified when reading the document. When specified, raise the threshold level. That is, R
A threshold level is determined by the combination of the OM 11 and the gray scale switch 12, and this threshold level and the target pixel A are compared by the comparator 13 to create a binary signal.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、従来は減算器や加算器を複数個用
いて画素のレベルを決定するため回路規模が大きく複雑
となるのに対し、本発明ではしきい値レベルを可変とし
て設定できるメモリをもたせることによ多回路規模が小
さく簡略化され、変更も容易となる。
As explained above, conventional methods use multiple subtracters and adders to determine the pixel level, resulting in a large and complex circuit, whereas the present invention uses a memory that can set the threshold level as variable. By making it possible to reduce the number of circuits, the scale of the multiple circuits can be reduced and simplified, and changes can be made easily.

【図面の簡単な説明】 第1図は本発明の原理説明図、第2図は本発明の実施例
の構成説明図、第3図(α)〜(c)は従来例の説明図
であり、図中、11はメモリ(ROM)、12は浸炭切
替器、13は比較器を示す。
[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1 is an explanatory diagram of the principle of the present invention, Fig. 2 is an explanatory diagram of the configuration of an embodiment of the present invention, and Figs. 3 (α) to (c) are explanatory diagrams of a conventional example. In the figure, 11 is a memory (ROM), 12 is a carburizing switch, and 13 is a comparator.

Claims (1)

【特許請求の範囲】 画像読取装置により原稿をライン走査し、注目画素に対
するしきい値を求め2値化回路に供給するしきい値決定
回路において、 注目画素の近傍の複数の画素のレベルを入力して注目画
素位置に対するしきい値を格納しておき出力する手段と
、 該格納手段の出力に対し原稿読取時の濃淡指定に応じて
レベルが変化する濃淡切替手段と、を具えたことを特徴
とするしきい値決定回路。
[Claims] In a threshold determination circuit that lines scans a document using an image reading device, determines a threshold value for a pixel of interest, and supplies it to a binarization circuit, the levels of a plurality of pixels in the vicinity of the pixel of interest are input. and a means for storing and outputting a threshold value for the pixel position of interest; and a grayscale switching means for changing the level of the output of the storage means according to a grayscale specification when reading a document. threshold determination circuit.
JP62065472A 1987-03-19 1987-03-19 Threshold deciding circuit Pending JPS63232573A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62065472A JPS63232573A (en) 1987-03-19 1987-03-19 Threshold deciding circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62065472A JPS63232573A (en) 1987-03-19 1987-03-19 Threshold deciding circuit

Publications (1)

Publication Number Publication Date
JPS63232573A true JPS63232573A (en) 1988-09-28

Family

ID=13288086

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62065472A Pending JPS63232573A (en) 1987-03-19 1987-03-19 Threshold deciding circuit

Country Status (1)

Country Link
JP (1) JPS63232573A (en)

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