JPS63232436A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63232436A JPS63232436A JP62066146A JP6614687A JPS63232436A JP S63232436 A JPS63232436 A JP S63232436A JP 62066146 A JP62066146 A JP 62066146A JP 6614687 A JP6614687 A JP 6614687A JP S63232436 A JPS63232436 A JP S63232436A
- Authority
- JP
- Japan
- Prior art keywords
- connection
- lead
- opening
- sections
- leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 239000008188 pellet Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- -1 etc. Substances 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置関し、特に外部導出用リードを有す
るフィルムキャリア方式の半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a film carrier type semiconductor device having external leads.
従来のかかるフィルムキャリア方式の半導体装置は、ポ
リイミド樹脂等で形成された長尺状のフレキシブルな絶
縁性フィルムテープに、このテープを順次送る為のスズ
ロケット・ホールと半導体ペレットを収納するデバイス
・ホールと外部基板との接続用開孔部とを形成し、この
フィルムテープ上にリードパターン及び配線パターンが
密着して設けられている。Conventional film carrier type semiconductor devices include a long flexible insulating film tape made of polyimide resin, etc., and a tin rocket hole for sequentially feeding the tape and a device hole for storing semiconductor pellets. and an opening for connection to an external board, and a lead pattern and a wiring pattern are provided on this film tape in close contact with each other.
第４図は従来の半導体装置を搭載したモジュールの断面
図である。FIG. 4 is a sectional view of a module equipped with a conventional semiconductor device.
第４図に示すように、従゛来のフィルムキャリア方式の
半導体装置は、半導体素子１３に接続されたリード１６
を接続用開孔部１５で切断し、それを個々に外部基板１
９に接続していた。As shown in FIG. 4, the conventional film carrier type semiconductor device has a lead 16 connected to a semiconductor element 13.
are cut at the connection openings 15 and attached to the external board 1 individually.
It was connected to 9.
しかしながら、ＩＣカード等の２個以上のベレットをフ
ィルムキャリア上で接続する場合、ボンディング接続の
ための接続用開孔部の外周に接続用配線パターンが形成
されており、この様な形状の半導体装置を外部基板等に
接続するときには接続用開孔部で切断することが不可能
となる。そのため接続用開孔部を介して接続するか、半
導体装置を逆にして接続することになるが、前記接続用
開孔部を介して接続すると接続リードが断線したり、ま
た逆に接続すると配線ショート等が生ずる欠点がある。However, when connecting two or more pellets such as IC cards on a film carrier, a connection wiring pattern is formed around the outer periphery of the connection hole for bonding connection, and semiconductor devices with such a shape are When connecting to an external board or the like, it becomes impossible to cut at the connection opening. Therefore, the connection must be made through the connection hole or by inverting the semiconductor device, but if the connection is made through the connection hole, the connection lead may be disconnected, and if it is connected in the reverse direction, the wiring There is a drawback that short circuits may occur.
更に、逆に接続する場合は、眉間に絶縁シートあるいは
レジスト等を設ける必要があるが、この場合は製造工数
が複雑になる等の欠点がある。Furthermore, in the case of reverse connection, it is necessary to provide an insulating sheet or resist between the eyebrows, but in this case, there are disadvantages such as complicated manufacturing steps.
本発明の目的はかかる接続リードの断線、配線のショー
トおよび製造工数を簡略化するフィルムキャリア方式の
半導体装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a film carrier type semiconductor device that can reduce disconnection of connection leads, short circuits, and manufacturing steps.
本発明はかかる半導体装置を実現するため、フィルム上
に外部基板へのボンディング接続用開孔部と、半導体素
子の配置用開孔部と、前記接続用開孔部をブリッジする
リードと、前記リード部に形成した複数個の伸び補償部
とを含んで構成される。In order to realize such a semiconductor device, the present invention provides an opening on a film for bonding connection to an external substrate, an opening for arranging a semiconductor element, a lead for bridging the connection opening, and the lead. and a plurality of elongation compensating sections formed in the section.
また、特に前記接続用開孔部内に設けられたリードの複
数個（例えば２７個）の伸び補償部は接続用開孔部の両
端に設けられ、この伸び補償部間のリードと外部基板と
の接続を行なうように構成される。In particular, a plurality of (for example, 27) elongation compensating parts of the lead provided in the connection aperture are provided at both ends of the connection aperture, and the leads between the elongation compensating parts and the external board are connected to each other. configured to make the connection.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を説明するための半導体装置
の平面図である。FIG. 1 is a plan view of a semiconductor device for explaining one embodiment of the present invention.
第１図に示すように、本発明の半導体装置は、ポリイミ
ド、ガラス・エボシキ、ポリエステル等の絶縁フィルム
で作られたテープ１に、このテープ１を順次送るための
スプロケットホール２と半導体素子３を収納するデバイ
スホール４とアウター・リード・ボンディング接続を行
なうための接続用開孔部５とをあけ、このテープ１に密
着してリード６及び配線７を形成する。このとき、ボン
ディング接続用開孔部５をブリッジするリード６は各々
２個の角形のメガネ状伸び補償部８を有し、且つこの２
つの伸び補償部８は接続用開孔部５の両端に形成される
。As shown in FIG. 1, the semiconductor device of the present invention includes a tape 1 made of an insulating film such as polyimide, glass epoxy, polyester, etc., and sprocket holes 2 and semiconductor elements 3 for sequentially feeding the tape 1. A device hole 4 to be accommodated and a connection opening 5 for making an outer lead bonding connection are made, and leads 6 and wiring 7 are formed in close contact with this tape 1. At this time, each lead 6 bridging the bonding connection opening 5 has two rectangular glasses-like elongation compensation parts 8, and these two
Two elongation compensating parts 8 are formed at both ends of the connecting hole 5.
次に、第２図は第１図に示す半導体装置を搭載したＩＣ
カード等のモジュールのＡ−Ａ″線断面図である。Next, Figure 2 shows an IC equipped with the semiconductor device shown in Figure 1.
It is a sectional view taken along the line AA'' of a module such as a card.
第２図に示すように、Ａ−Ａ’線断面はフィルム１上に
接続配置した半導体素子３をＩＣカード用基板９に搭載
したモジュールの断面を示し、特にかかる半導体装置は
そのリード６が伸び補償部８間で接続されている。As shown in FIG. 2, a cross section taken along the line A-A' shows a cross section of a module in which a semiconductor element 3 connected and arranged on a film 1 is mounted on an IC card substrate 9. In particular, in such a semiconductor device, its leads 6 extend. The compensation units 8 are connected to each other.
また、第３図は本発明の第二の実施例を説明するための
半導体装置の平面図である。Further, FIG. 3 is a plan view of a semiconductor device for explaining a second embodiment of the present invention.
第３図に示すように、この半導体装置はフィルムチー１
１上にデバイスホール４．このデバイスホール４の周囲
に形成されたボンディング接続用開孔部５等を有し、且
つ前記テープ１上に密着してリード６が形成される。こ
のリード６がブリッジされる接続用開孔部５内において
は、２個所以上の円形の伸び補償部８が接続用開孔部５
の端部に形成される。As shown in FIG.
1 device hole on top 4. A lead 6 is formed having an opening 5 for bonding connection formed around the device hole 4 and in close contact with the tape 1 . In the connecting hole 5 where the lead 6 is bridged, two or more circular elongation compensating portions 8 are formed in the connecting hole 5.
formed at the end of the
尚、この円形の形状は、基板等に伸び補償部間で接続す
る時、リードが伸び、切断されなければ他の形状でもよ
い。Note that this circular shape may be any other shape as long as the leads stretch and are not cut when connecting the stretch compensating portions to a substrate or the like.
以上の実施例では半導体素子が２個までの例をとり上げ
て説明したが、本発明においては特にこの数に制限され
るものでもない。Although the above embodiments have been described using an example in which the number of semiconductor elements is up to two, the present invention is not particularly limited to this number.
以上説明したように、本発明の半導体装置はフィルム上
に形成したボンディング接続用開孔部をブリッジするリ
ードと前記開孔部内の前記リードに形成した数個の伸び
補償部とを設けることにより、基板に熱圧着ボンディン
グ等を行って伸びた前記リードを前記伸び補償部で吸収
することができる効果がある。また、本発明の半導体装
置は前記フィルムに配置される半導体素子間を個々に切
断することなく前記基板にフィルム毎に搭載できるので
前記半導体素子間の配線がショートする問題も解消され
る効果がある。更には、本発明の半導体装置はモジュー
ル組立における製造上の工数も簡略化される効果がある
。As explained above, the semiconductor device of the present invention includes a lead bridging the bonding connection opening formed on the film and several elongation compensating parts formed on the lead within the opening. There is an effect that the elongation of the lead caused by thermocompression bonding or the like to the substrate can be absorbed by the elongation compensating section. Further, since the semiconductor device of the present invention can be mounted on each film on the substrate without individually cutting the semiconductor elements arranged on the film, the problem of short-circuiting of wiring between the semiconductor elements can be solved. . Furthermore, the semiconductor device of the present invention has the effect of simplifying the manufacturing steps in assembling the module.
第１図は本発明の第二の実施例を説明するたｙの半導体
装置の平面図、第２図は第１図に示す内導体装置を搭載
したモジュールのＡ−Ａ’線＠Ｕ図、第３図は本発明の
第二の実施例を説明するｉめの半導体装置の平面図、第
４図は従来の半導体装置を搭載したモジュールの断面図
である。
１・・・テープ、２・・・スプロケットホール、３・・
・引導体素子、４・・・デバイスホール、５・・・接続
用開了部、６・・・リード、７・・・配線、８・・・伸
び補償部、≦・・・基板。FIG. 1 is a plan view of a semiconductor device according to a second embodiment of the present invention, and FIG. 2 is an AA' line @U diagram of a module equipped with the inner conductor device shown in FIG. 1. FIG. 3 is a plan view of an i-th semiconductor device illustrating a second embodiment of the present invention, and FIG. 4 is a sectional view of a module mounting a conventional semiconductor device. 1...Tape, 2...Sprocket hole, 3...
- Leading conductor element, 4... Device hole, 5... Connection opening part, 6... Lead, 7... Wiring, 8... Elongation compensation part, ≦... Board.
Claims (1)
素子の配置用開孔部と、前記接続用開孔部をブリッジす
るリードと、前記リード部に形成した複数個の伸び補償
部とを有するように形成したことを特徴とする半導体装
置。 ２、リードに形成した少なくとも二つの伸び補償部を接
続用開口部の両端に形成するようにした特許請求の範囲
第１項記載の半導体装置。[Claims] 1. An opening on the film for connection to an external substrate, an opening for arranging a semiconductor element, a lead for bridging the connection opening, and a lead formed in the lead. 1. A semiconductor device characterized in that it is formed to have a plurality of elongation compensating parts. 2. The semiconductor device according to claim 1, wherein at least two stretch compensation portions formed on the lead are formed at both ends of the connection opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62066146A JPS63232436A (en) | 1987-03-20 | 1987-03-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62066146A JPS63232436A (en) | 1987-03-20 | 1987-03-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63232436A true JPS63232436A (en) | 1988-09-28 |
Family
ID=13307432
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62066146A Pending JPS63232436A (en) | 1987-03-20 | 1987-03-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63232436A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5681777A (en) * | 1992-06-04 | 1997-10-28 | Lsi Logic Corporation | Process for manufacturing a multi-layer tab tape semiconductor device |
-
1987
- 1987-03-20 JP JP62066146A patent/JPS63232436A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5681777A (en) * | 1992-06-04 | 1997-10-28 | Lsi Logic Corporation | Process for manufacturing a multi-layer tab tape semiconductor device |
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