JPS63229995A - Two-wire/four-wire conversion circuit - Google Patents

Two-wire/four-wire conversion circuit

Info

Publication number
JPS63229995A
JPS63229995A JP6240187A JP6240187A JPS63229995A JP S63229995 A JPS63229995 A JP S63229995A JP 6240187 A JP6240187 A JP 6240187A JP 6240187 A JP6240187 A JP 6240187A JP S63229995 A JPS63229995 A JP S63229995A
Authority
JP
Japan
Prior art keywords
wire
impedance
line
operational amplifier
conversion circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6240187A
Other languages
Japanese (ja)
Other versions
JPH0533880B2 (en
Inventor
Toshiyoshi Kitaguchi
北口 利喜
Kenji Sakai
謙二 酒井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6240187A priority Critical patent/JPS63229995A/en
Publication of JPS63229995A publication Critical patent/JPS63229995A/en
Publication of JPH0533880B2 publication Critical patent/JPH0533880B2/ja
Granted legal-status Critical Current

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  • Interface Circuits In Exchanges (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

PURPOSE:To increase the quantity of mismatching attenuation on the side of two-wire line by setting the impedance on the side of a four wire to a pure resistance and providing an equilibrium connection network on an infiltrating cancellation line part. CONSTITUTION:For matching the load impedance 12 of the two-wire analogue line in an analogue trunk 11, the impedance 13 on the side of the four-wire is set to the pure resistance, and the equilibrium connection network 14 which prevents a reception signal from a four-wire digital channel 10 form infiltrating into the channel 10 is provided in the infiltrating cancellation line part 15 with the least influence of the impedance on the pure resistance. Thus, the equilibrium connection network 14 does not influence the quantity of mismatching attenuation on the side of the two-wire, and the input impedance 13 on a return loss on the side of the four-wire. Since a two-wire/four-wire conversion circuit can be designed without the consideration of influence on both, the quantity of mismatching attenuation on the side of the two-wire can freely be increased.

Description

【発明の詳細な説明】 〔概 要〕 ディジタル交換機におけるアナログトランクにおいて、
二線アナログ回線の負荷インピーダンスと整合をとるた
めの四線側のインピーダンスを純抵抗とし、かつ、平衡
結線網をまわり込み相殺回線部に設けたことにより、二
線回線側の不整合減衰量を増大させたもの。
[Detailed Description of the Invention] [Summary] In an analog trunk in a digital exchange,
By using pure resistance as the impedance on the four-wire side to match the load impedance of the two-wire analog line, and by providing a balanced connection network in the wrap-around canceling line section, the amount of mismatch attenuation on the two-wire line side can be reduced. something that has been increased.

〔産業上の利用分野〕[Industrial application field]

本発明はディジタル交換機におけるアナログトランクの
二線−四線変換回路に関する。
The present invention relates to a two-wire to four-wire conversion circuit for analog trunks in a digital exchange.

ディジタル交換機におけるアナログトランクにおいては
、交換機の通話路がディジタル通話路であるので四線構
成となり、一方アナログ回線は二線式が多いので二線−
四線交換を行なうハイブリッド機能が必要となる。この
際、四線側の受信信号が四線の送信側に回り込まないよ
うに、平衡結線m(BN)を挿入して二線側のインピー
ダンスと整合させるとともに回り込みを防止する必要が
ある。しかし、BNの挿入により対局との整合が悪くな
り二線側の不整合減衰量の減少につながるため改善が要
望されている。
In analog trunks in digital exchanges, the communication path of the exchange is a digital communication path, so it is a four-wire configuration, whereas analog lines are often two-wire systems, so two-wire
A hybrid function that performs four-wire exchange is required. At this time, it is necessary to insert a balanced connection m (BN) to match the impedance of the two-wire side and to prevent the reception signal from the four-wire side from going around to the four-wire transmitting side. However, since the insertion of the BN deteriorates the matching with the game and leads to a decrease in the amount of mismatch attenuation on the second line side, improvements are desired.

〔従来の技術〕[Conventional technology]

従来の二線−四線変換回路を第2図に示す。 A conventional two-wire to four-wire conversion circuit is shown in FIG.

第2図において、1,2.3及び4はオペアンプ、5は
平衡結線網(BN) 、6はトランス、7は線路抵抗を
含む対局の終端抵抗である。四線側の入力端aは図示し
ないD/A変換器を介してディジタル交換機のネットワ
ークに接続されている。
In FIG. 2, 1, 2, 3, and 4 are operational amplifiers, 5 is a balanced wiring network (BN), 6 is a transformer, and 7 is a terminal resistor of the opposite station including line resistance. The input terminal a on the four-wire side is connected to a digital exchange network via a D/A converter (not shown).

四線側の出力端すは図示しないA/D変換器を介してデ
ィジタル交換機のネットワークに接続されている。
The output terminal on the four-wire side is connected to a network of digital exchanges via an A/D converter (not shown).

BN5のインピーダンスを211%二線側の終端抵抗と
線路抵抗との和をZI−1四線側の入力端aにおける電
圧をe、とする。ここで入力電圧e。
The impedance of BN5 is 211%, the sum of the terminating resistance on the two-wire side and the line resistance is ZI-1, and the voltage at the input terminal a on the four-wire side is e. Here the input voltage e.

をオペアンプ2で増巾しくオペアンプ3の利得は1とす
る)、オペアンプ2と3の出力である点Cと点dの間の
電圧をAe、とすると、入力電圧対c−d間の電圧がA
となる。そこでオペアンプ4オペアンプ4の利得をBと
すると、オペアンプれてオペアンプ1に入力される。オ
ペアンプ1によりオペアンプ4の出力である の差動入力が増幅されて出力端すに電圧e0の信号が出
力される。
is amplified by operational amplifier 2 and the gain of operational amplifier 3 is 1), and the voltage between points C and d, which are the outputs of operational amplifiers 2 and 3, is Ae, then the voltage between the input voltage and c-d is A
becomes. Therefore, if the gain of the operational amplifier 4 is B, the signal is input to the operational amplifier 1 through the operational amplifier. The differential input, which is the output of the operational amplifier 4, is amplified by the operational amplifier 1, and a signal of voltage e0 is outputted to the output terminal.

リターンロスを最大にするためには、すなわち四線側で
の回り込みを最小にするためには、オペアンプ1の差動
入力が零になればよく、したがつとすればよい。四線側
と二線側のインピーダンス整合の条件はZl、=Z!+
であるので、ZI=ZllとA−B=2を満たせばイン
ピーダンス整合がとれ、かつe。=0となってリターン
ロスが最大となる。したがってオペアンプ2.3.及び
4はA−B=2となるように考慮されている。
In order to maximize the return loss, that is, to minimize the wraparound on the four-wire side, the differential input of the operational amplifier 1 only needs to be zero. The conditions for impedance matching between the four-wire side and the two-wire side are Zl, = Z! +
Therefore, if ZI=Zll and A-B=2 are satisfied, impedance matching can be achieved, and e. = 0, and the return loss becomes maximum. Therefore, operational amplifier 2.3. and 4 are considered so that A−B=2.

(発明が解決しようとする問題点〕 上述の従来の二線−四線変換回路では、BN5はトラン
ス6の四線側巻線に直接接続されており、インピーダン
ス整合の条件は2.=211である。
(Problems to be Solved by the Invention) In the conventional two-wire to four-wire conversion circuit described above, BN5 is directly connected to the four-wire side winding of the transformer 6, and the impedance matching condition is 2.=211. be.

したがって、BN5のインピーダンスZRは二線側の終
端抵抗に一致して設計される。ところが、二線側のイン
ピーダンスZLには、終端抵抗のみならず線路抵抗も含
まれており、この線路抵抗の値はシステムによりまちま
ちである。このため、BN5のインピーダンスZ、は必
ずしもZI、と一致せず、また、二線側の線路インピー
ダンスに応じてBN5のインピーダンスを調節すること
は困難なので、不整合となって、二線側の不整合減衰量
が小さくなるという問題点がある。
Therefore, the impedance ZR of BN5 is designed to match the terminating resistance on the two-wire side. However, the impedance ZL on the two-wire side includes not only the terminating resistance but also the line resistance, and the value of this line resistance varies depending on the system. For this reason, the impedance Z of BN5 does not necessarily match ZI, and it is difficult to adjust the impedance of BN5 according to the line impedance on the second line side, resulting in a mismatch and the impedance on the second line side. There is a problem that the amount of matching attenuation becomes small.

〔問題点を解決するための手段〕[Means for solving problems]

第1図を用いて本発明の詳細な説明する。 The present invention will be explained in detail using FIG.

第1図において、二線アナログ回線9と四線ディジタル
通話路10を接続するディジタル交換機におけるアナロ
グトランク11が示されている。
In FIG. 1, an analog trunk 11 in a digital exchange connecting a two-wire analog line 9 and a four-wire digital communication path 10 is shown.

このアナログトランク11において、二線アナログ回線
の負荷インピーダンス12と整合をとるための四線側の
インピーダンス13を純抵抗としている。また、四線デ
ィジタル通話路10からの受信信号が四線ディジタル通
話路lOに回り込むのを防1ヒする平衡結線網14を、
上記純抵抗に対するインピーダンスの影響の最も少ない
回り込み相殺回線部15に設けである。
In this analog trunk 11, the impedance 13 on the four-wire side is a pure resistance to match the load impedance 12 of the two-wire analog line. In addition, a balanced connection network 14 that prevents the received signal from the four-wire digital communication path 10 from going around to the four-wire digital communication path 10,
It is provided in the loop cancellation line section 15 where the influence of impedance on the pure resistance is least.

〔作 用〕[For production]

二線側の負荷インピーダンスと整合をとるための四線側
のインピーダンスを純抵抗とし、平衡績vAm14を上
記純抵抗に対するインピーダンスの影響の最も少ない回
り込み相殺回線部に設けたことにより、回り込みを抑1
ヒしつつ、インピーダンス整合を容易に実現できるので
、不整合減衰量を大きくすることができる。
The impedance on the four-wire side for matching the load impedance on the two-wire side is a pure resistance, and the balanced resistance vAm14 is provided in the loop cancellation circuit section where the impedance has the least influence on the pure resistance, thereby suppressing loop loop.
Since impedance matching can be easily achieved while reducing the amount of heat, the amount of mismatch attenuation can be increased.

〔実施例〕〔Example〕

第1図の回路図によって本発明の実施例を引き続き説明
する。
An embodiment of the invention will now be explained with reference to the circuit diagram of FIG.

第1図において、9は二線アナログ回線、10は四線デ
ィジタル通話路、11はアナログトランク、13及び1
6は抵抗、15は回り込み相殺回線、14は平衡結線網
(BN) 、17,18.19及び20はオペアンプ、
21はI・ランスである。
In FIG. 1, 9 is a two-wire analog line, 10 is a four-wire digital communication line, 11 is an analog trunk, 13 and 1
6 is a resistor, 15 is a loop cancellation line, 14 is a balanced wiring network (BN), 17, 18, 19 and 20 are operational amplifiers,
21 is I. Lance.

アナログトランク11の四線側の入力端aとディジタル
通話路IOの間にはD/A変換器22が接続されており
、出力端すとディジタル通話路10の間にはA/D変換
器23が接続されている。
A D/A converter 22 is connected between the input terminal a on the four-wire side of the analog trunk 11 and the digital communication path IO, and an A/D converter 23 is connected between the output terminal and the digital communication path 10. is connected.

四線側の入力端aはオペアンプ17及びトランス21の
四線側巻線を介してオペアンプ19の一つの入力に接続
されている。オペアンプ17の出力はオペアンプ18及
び整合用の純抵抗13を介してオペアンプ19の上記一
つの入力に接続されている。オペアンプ17の出力はま
た、オペアンプ19の他の入力に直接接続されている。
The four-wire side input terminal a is connected to one input of the operational amplifier 19 via the operational amplifier 17 and the four-wire side winding of the transformer 21 . The output of the operational amplifier 17 is connected to the one input of the operational amplifier 19 via an operational amplifier 18 and a pure resistor 13 for matching. The output of operational amplifier 17 is also directly connected to the other input of operational amplifier 19.

オペアンプ19の出力はオペアンプ20の一つの入力に
接続されており、オペアンプ20の他の入力には、入力
端aが抵抗16を含む回り込み相殺回線15を介して接
続されている。回り込み相殺回線15ど地気の間には、
平衡結線網(BN)14が接続されている。
The output of the operational amplifier 19 is connected to one input of the operational amplifier 20, and the input terminal a is connected to the other input of the operational amplifier 20 via a loop cancellation line 15 including a resistor 16. Between the detour cancellation line 15 and the earth,
A balanced wiring network (BN) 14 is connected.

c−d間抵抗13の抵抗値をR3、二線側の負荷インピ
ーダンス、すなわち終端抵抗と線路抵抗との和をZI、
四線側の入力端aにおける電圧をe、とすると、入力電
圧elをオペアンプ18で増巾し、オペアンプ18の出
力とオペアンプ17の出力との間の電圧はAeHとする
と、入力電圧対c −d間の電圧がAとなる。そこで、
オペアンなる。
The resistance value of the c-d resistor 13 is R3, and the load impedance on the two-wire side, that is, the sum of the terminating resistance and line resistance, is ZI.
If the voltage at the input terminal a on the four-wire side is e, then the input voltage el is amplified by the operational amplifier 18, and the voltage between the output of the operational amplifier 18 and the output of the operational amplifier 17 is AeH, then the input voltage vs. c − The voltage between d becomes A. Therefore,
Become an operan.

オペアンプ19の利得をBとすると、オペアンされてオ
ペアンプ20の一つの入力に入力される。
Assuming that the gain of the operational amplifier 19 is B, it is operationalized and input to one input of the operational amplifier 20.

一方、BN14のインピーダンスをZ*、Fir;抗1
6の抵抗値を抵抗13と同じ<R,とすると、オペアン
プ20の他方の入力電圧は オペアンプ20の出力電圧e0を零にすれば四線側のリ
ターンロスは最大となり、回り込みは打消される。この
ためには、オペアンプ19の出力電圧と回り込み相殺回
線15の電圧が等しくなればよく、したがって すればよい。上式を満足するためにはZL−ZBとおい
てA−B=1となる必要があり、オペアンプ17 、1
8 、19 、及び20は利得がA−B=1を満足。
On the other hand, the impedance of BN14 is Z*, Fir;
If the resistance value of the resistor 6 is <R, which is the same as that of the resistor 13, then the other input voltage of the operational amplifier 20 is such that if the output voltage e0 of the operational amplifier 20 is set to zero, the return loss on the four-wire side will be maximized, and the wrap-around will be canceled. For this purpose, it is sufficient that the output voltage of the operational amplifier 19 and the voltage of the loop canceling line 15 are made equal to each other. In order to satisfy the above formula, it is necessary that A-B=1 in ZL-ZB, and the operational amplifier 17, 1
The gains of 8, 19, and 20 satisfy A-B=1.

するように設計されている。is designed to.

四線側の入力インピーダンスである抵抗13は、リター
ンロスに影響を与えない。また、BN14のインピ−ダ
ンスは入力インピーダンスである抵抗13に殆んど影響
を与えないので、整合はtl(抗値R3を調節するだけ
で可能になる。
The resistor 13, which is the input impedance on the four-wire side, does not affect the return loss. Furthermore, since the impedance of the BN 14 has almost no effect on the resistor 13, which is the input impedance, matching can be achieved simply by adjusting tl (resistance value R3).

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、二線−四線変換
回路における平衡結線M?4(BN)の位置を変更し、
インピーダンス整合を純抵抗のみで調節できるようにし
たことにより、BNは二線側の不整合減衰量に、また、
入力インピーダンスは四線側のリターンロスにそれぞれ
影響を与えなくなり相互に対する影響を考慮せずに二線
−四線変換回路を設計できこのために二線側不整合減衰
量と四線側のリターンロスとを双方とも犠牲にすること
なく向上させることが可能となる。
As explained above, according to the present invention, the balanced connection M? Change the position of 4 (BN),
By making it possible to adjust impedance matching using only pure resistance, BN can adjust the amount of mismatch attenuation on the two-wire side, and
The input impedance has no effect on the return loss on the four-wire side, and it is possible to design a two-wire to four-wire conversion circuit without considering their effects on each other. Therefore, the mismatch attenuation on the two-wire side and the return loss on the four-wire side are reduced. It is possible to improve both without sacrificing both.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の原理及び実施例による二線−四線変換
回路を示す回路図、 第2図は従来の二線−四線変換回路の回路図である。 9・・・二線アナログ回線、 10・・・四線ディジタル通話路、 12・・・負荷インピーダンス、 13・・・純抵抗、 14・・・平衡結線網、 15・・・回り込み相殺回線。
FIG. 1 is a circuit diagram showing a two-wire to four-wire conversion circuit according to the principles and embodiments of the present invention, and FIG. 2 is a circuit diagram of a conventional two-wire to four-wire conversion circuit. 9... Two-wire analog line, 10... Four-wire digital communication path, 12... Load impedance, 13... Pure resistance, 14... Balanced connection network, 15... Detour cancellation line.

Claims (1)

【特許請求の範囲】 二線アナログ回線(9)と四線ディジタル通話路(10
)を接続するディジタル交換機におけるアナログトラン
ク(11)において、 該二線アナログ回線(9)の負荷インピーダンス(12
)と整合をとるための四線側のインピーダンスを純抵抗
(13)とし、かつ、 該四線ディジタル通話路(10)からの受信信号が該四
線ディジタル通話路に回り込むのを防止する平衡結線網
(14)を、該純抵抗(13)に対するインピーダンス
の影響が最も少ない回り込み相殺回線部(15)に設け
たことを特徴とする二線−四線変換回路。
[Claims] Two-wire analog line (9) and four-wire digital communication line (10)
), the load impedance (12) of the two-wire analog line (9) is
), the impedance on the four-wire side is a pure resistance (13), and the balanced connection prevents the received signal from the four-wire digital communication path (10) from going around to the four-wire digital communication path. A two-wire to four-wire conversion circuit characterized in that a network (14) is provided in a loop canceling line section (15) where the influence of impedance on the pure resistor (13) is least.
JP6240187A 1987-03-19 1987-03-19 Two-wire/four-wire conversion circuit Granted JPS63229995A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6240187A JPS63229995A (en) 1987-03-19 1987-03-19 Two-wire/four-wire conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6240187A JPS63229995A (en) 1987-03-19 1987-03-19 Two-wire/four-wire conversion circuit

Publications (2)

Publication Number Publication Date
JPS63229995A true JPS63229995A (en) 1988-09-26
JPH0533880B2 JPH0533880B2 (en) 1993-05-20

Family

ID=13199076

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6240187A Granted JPS63229995A (en) 1987-03-19 1987-03-19 Two-wire/four-wire conversion circuit

Country Status (1)

Country Link
JP (1) JPS63229995A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02246656A (en) * 1989-03-20 1990-10-02 Toshiba Corp Telephone system
US5172411A (en) * 1990-03-27 1992-12-15 Siemens Aktiengesellschaft Two-wire/four-wire converter
US5175763A (en) * 1990-03-27 1992-12-29 Siemens Aktiengesellschaft Two-wire/four-wire converter

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02246656A (en) * 1989-03-20 1990-10-02 Toshiba Corp Telephone system
US5172411A (en) * 1990-03-27 1992-12-15 Siemens Aktiengesellschaft Two-wire/four-wire converter
US5175763A (en) * 1990-03-27 1992-12-29 Siemens Aktiengesellschaft Two-wire/four-wire converter

Also Published As

Publication number Publication date
JPH0533880B2 (en) 1993-05-20

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