JPS63229519A - Flag bit setting circuit - Google Patents

Abstract

PURPOSE:To simplify the production of a program by limiting the changing direction of a flag bit only in a single direction where a reset state is changed to a set state or vice versa. CONSTITUTION:When an enable signal is supplied to a ZS flag bit setting circuit 2, '1' is set at the circuit 2. When a flag bit is active, a zero flag bit set at a Z flag bit setting circuit 31 can be changed just in a single direction where '1' is changed to '0'. For instance, many data are compared with a prescribed one and the flag bit is set or reset as long as the coincidence is obtained from said comparison. When the noncoincident data are once produced, the flag bit is changed to a reset or set state. Hereafter the reset or set state of the flag bit is held despite occurrence of the coincident data. Thus the occurrence of noncoincident data can be discriminated after all comparison processes are ended and a program can be shortened.

Description

[Detailed Description of the Invention] [Summary] A control signal that can set a mode in which the direction of change of a flag bit that can be checked by a central processing unit can only be changed in one direction from a reset state to a set state or from a set state to a reset state. A flag bit setting circuit controlled by a generating means, which compares, for example, a large number of random address data with predetermined data, and when all of them meet a predetermined condition (for example, if they all match). You can easily create a program that jumps to a predetermined address (when the

[Industrial application field]

The present invention relates to a flag bit setting circuit that can be checked by a CPU.
This invention relates to a zero flag bit setting circuit that calculates the difference using LU) and sets it to 1 or O depending on whether the two data match (that is, the difference is zero). .

[Conventional technology]

Traditionally, as a means for the CPU to compare two data and determine the result, the two data are sent to an arithmetic logic unit (
ALtJ) calculates the difference, and if the two data match (that is, the difference is zero), the zero flag bit is set to 1 by the output of the arithmetic logic unit; If the two data do not match (that is, the difference is not zero), the zero flag bit is set to 0 by the output of the arithmetic logic unit, and the zero flag bit is set to 0 depending on whether the zero flag bit is 1 or 0. It is known to configure the computer so that the CPU can determine the result of the calculation.

FIG. 3 shows an example of such a zero flag bit setting circuit, in which Pl and P2 are P channel transistors, N1
．． N2 is an N-channel transistor, and 1 to I5 are inverters, among which inverters r3. I4 constitutes a latch circuit. The A L [
The zero determination result of J is supplied to the gates of the transistors P2 and N1 via the inverter (1). Also, the zero flag change input (which becomes high level when you want to change the zero flag) is supplied to the gate of the transistor P1 via the inverter I2. and directly to the gate of transistor N2 to turn on these transistors.

Therefore, when the result of the calculation of AI and U is zero (the two data match), the AL
The high level output from U is made low level by inverter ■1, transistor P2 is turned on, and transistor N is turned on.
1 is turned off and high level data is sent to inverter 1.
3, and is input to a latch circuit consisting of r4. Therefore, the high level data is inverted to low level and latched by the latch circuit, and the latched data is further inverted to high level by the inverter 5, and the zero flag becomes "1".

On the other hand, when the result of the calculation of the ALU is not zero (the two data do not match), the ALU
The low level output from the inverter 11 is made high level, transistor N1 is turned on, and transistor P2
is turned off, the low level data is inverted to high level and latched in the launch circuit, and further inverted to low level by inverter 5, and the zero flag becomes 0.
”.

[Problem that the invention seeks to solve]

However, according to such conventional technology, for example, a large amount of random address data is compared with predetermined data, and when all of them meet a predetermined condition (for example, when they all match), a jump is made to a predetermined address. For example, the format of the program is as follows.

Here, #O is the immediate value data, and iX p tY #
iZ, . . . iW indicate data stored at each address in the memory.

That is, first, immediate value data #0 and random address data iX are compared, and if they match (that is, if the zero flag bit is 1), the next comparison process (CMP #
0, iY), but if they do not match (ie, if the zero flag bit is 0), jump to a predetermined address.

Next, when the above two data match, immediate value data #0 and random address data iY are compared, and if they match (if the zero flag bit is 1), the next comparison process (CMP #O, iZ), but if they do not match (that is, if the zero flag bit becomes 0), jump to a predetermined address. In this way, if all the comparison results up to that point match, the process proceeds to the next comparison process, but if any comparison result shows a match, the process jumps to a predetermined address from there. Then, only if all the comparison results of the last comparison process (CMP #O, iW) match, the target program FiN
Jump to D, and if any of the comparison results do not match,
Jumping from there to a predetermined address is as described above.

Therefore, each time a comparison process is performed, if the comparison result does not match (if the zero flag bit becomes O), it is necessary to add an instruction (JNZ) to jump to a predetermined address, which increases the length of the program. It ends up.

The present invention was made to solve this problem, and creates a mode in which the direction of change of flag bits (for example, zero flag bit) that can be checked by the CPU is limited to only one direction: from reset to set or from set to reset. This makes it possible to create a program such as the one described above in a relatively short amount of time.

[Means for solving problems]

In order to solve the above problems, the present invention provides a control signal generating means that limits the direction of change of the flag bit that can be checked by the central processing unit to only one direction from the reset state to the set state or from the set state to the reset state. (
The ZS focus setting circuit (FIG. 1) provides a flag bit setting circuit in which the direction of the change is controlled.

[Function] According to the above configuration, for example, a large amount of data is compared with predetermined data, and as long as they match, the flag bit is set or reset, and once mismatched data occurs, the flag bit is set or reset. After changing the bit to the reset or set state, even if matching data occurs, the reset or set state of the flag bit is maintained, so all comparison processing is performed to detect the occurrence of mismatched data. It can be identified after the program is finished, and the program as described above can be created more simply.

〔Example〕

FIG. 1 shows the positioning of a zero flag (Z flag) bit setting circuit as an embodiment of the present invention. Arithmetic logic unit (ALU) 1 receives two input data (data A and B) from a predetermined bus. is input, predetermined arithmetic processing is performed, and the result of the arithmetic operation is returned to the bus. Here, when the ALU performs arithmetic processing, the values of the two input data A and B are compared to see if they match, and the comparison result is stored in the zero flag bit provided in the condition code register 3. It is set in the setting circuit 31.

In addition to the zero flag bit setting circuit 31, the condition code register 3 is provided with a carry bit setting circuit 32, an interrupt disable bit setting circuit 33, etc., and the contents set in each of these setting circuits are stored in the CP.
It is supplied to the discrimination circuit of U. And the input data A, B
If the values match (that is, the subtraction result is zero), the Z flag bit setting circuit 3 is set by the output of the ALU1.
(corresponding to 1 bit of the register) is set to 1. On the other hand, if there is a mismatch (that is, the subtraction result is not zero), the Z flag bit setting circuit 3 is set by the output of the ALU 1. Clear the zero flag bit to 0.

Reference numeral 2 denotes a ZS flag bit setting circuit (for example, a launch circuit), and when the enable signal EN is input to the ZS flag bit setting circuit 2, 1 is set in the ZS flag bit setting circuit 2. te8亥ZS
When the flag bit becomes active, the zero flag bit set in the SiZ flag bit setting circuit 3 is set so that it can only change in one direction, for example from 1 to 0 (in some cases, it can only change in the opposite direction). controlled. Note that when the disable signal DIS is input to the ZS flag bit setting circuit 2, the output of the ZS flag bit setting circuit 2 is cleared to O, and the zero flag bit set in the Z flag bit setting circuit 3 is set to the AL.
Controlled by the UI as usual.

FIG. 2 shows one embodiment of the zero flag bit setting circuit 31 according to the present invention, and the difference from the circuit shown in FIG. 3 is that the Zs flag bit setting circuit 2 is different from the circuit shown in FIG.
P-channel transistor P whose gate is supplied with the output of
This is the point where 3 was added.

Therefore, when the ZS flag is set to "1", the P
The channel transistor P3 is turned off, and therefore the zero flag (Z flag), which was once set to the low level "0", cannot be set to the high level "1".

Note that when the Zs flag is reset to “0”,
The transistor P3 is turned on and controlled normally according to the zero determination result of the ALU.

In this way, by controlling the zero flag bit set in the Z flag setting circuit 3 so that it can only change in one direction, for example from l to 0, the program of the above format can be shortened as follows. .

That is, each comparison process (CMP #0. iX ~ CMP
#O.

iW) depending on the comparison result (depending on whether it is a match or a mismatch)
, the zero flag bit is set to 1 or 0, but if mismatching data occurs even once in the sequential comparison process and a condition to clear the zero flag bit to O occurs, then the zero flag bit becomes 0. After that, the zero flag bit remains 0 even if matching data occurs (that is, even if the ALUI would normally set the zero flag bit to 1), the zero flag bit remains 0, so all After the comparison process is completed, it can be determined whether even one mismatched data has occurred up to that point.

Therefore, as in the prior art, each time a comparison process is performed, if the comparison result does not match (if the two flag bits are 0), an instruction (JN
If the Bz flag bit is 0 after all comparison processing is completed, it is assumed that there is mismatched data and jumps to a specified address (JNZ). It is only necessary to add 1, and only if the Htj Z flag bit is 1 (that is, if all comparison results match), the next step is to jump to the target program FiND.

〔Effect of the invention〕

According to the present invention, a large amount of random address data is compared with predetermined data, and when all of the data meet predetermined conditions, (
For example, it is possible to easily create a program that jumps to a predetermined address (when all the addresses match).

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the positioning of a zero flag bit setting circuit as an embodiment of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the zero flag bit setting circuit in FIG. 1, and FIG. FIG. 2 is a diagram showing an example of a zero flag bit setting circuit in the prior art. (Explanation of symbols) 1: Arithmetic logic unit (ALU), 2: ZS bit setting circuit, 3: Condition code register, 31: Zero flag bit setting circuit.

Claims (1)

[Claims] 1. Controlled by a control signal generating means that limits the direction of change of the flag bit that can be checked by the central processing unit to only one direction from the reset state to the set state or from the set state to the reset state. Features a flag bit setting circuit. 2. While the control signal is at a specific level, a large number of data are compared with predetermined data, and as long as they match, the flag bit is set or reset, and no mismatched data occurs. According to the first aspect of the present invention, the flag bit is changed to a reset or set state, and thereafter, even if matching data occurs, the reset or set state of the flag bit is maintained.
Flag bit setting circuit described in section.