JPS63228665A - Manufacture of semiconductor storage device - Google Patents

Abstract

PURPOSE:To realize high packing density of elements by providing a recessed element forming region into an oxide silicon film on a silicon substrate and selectively polishing the silicon layer buried therein, CONSTITUTION:A SiO2 film 2 is deposited on a P-type silicon substrate 1 and a projected element region 20 is formed by etching the SiO2 film 2. Next, after a groove 4 is formed by etching the P-type silicon substrate, an insulating film 5 consisting of SiO2 film is formed. Thereafter, an opening 6 is provided to the SiO2 film 2 and the substrate surface is exposed. Next, a silicon layer 7 is deposited by selective epitaxial growth of silicon from the opening 6 and thereafter a polycrystalline silicon 8 is deposited to the entire part. Thereafter, the silicon 8 and silicon layer 7 are polished to make flat the surface. Next, a capacitance insulation film 10 of triple layer structure is formed on the surface of silicon 8, the groove 4 is filled with the polycrystalline silicon 11 and it is insulated by the SiO2 film 12. Next, after an electrode 14 is formed on the gate oxide film formed on the surface of silicon layer 7, the source drain 15 is formed by ion implantation of arsenic to the silicon layer 7. Then, an interlayer insulating film 16 is formed to the entire surface and the Al wiring 17 is formed. Thereby, high packing density can be realized by forming a narrow element isolation region.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a semiconductor memory device.

[Conventional technology]

Semiconductor devices are becoming more dense by miniaturizing the elements, and in particular, dynamic random access memory (DRAM), which is a storage device, is being developed at a remarkable rate with devices with four times the storage capacity being developed every three years. It is developing in One storage element (memory cell) in DRAM consists of two elements: one switching transistor and one charge storage capacitor, and trench capacitors, storage transistors, etc. are being developed to achieve miniaturization. .

For example, M, uneven talent (M, Okam+ura)
The International Electron Device Meeting was held in Washington, U.S.A. in 1985.
DevicesMeeting) Lecture Proceedings 29
．． No. 7, pages 718-721, A THREE-dimensional DRAM cell of stacked switching transistors inS○I (A THREE-
DIMENSIONAL DRAM CELL OF
KE to ST8 5WITCHTNG-TRANSI
In a paper entitled STORlN5ol (SSS)), the structure and manufacturing method of a memory element as shown in FIG. 2 was reported.

That is, on a P-type silicon substrate with plane orientation (100) 21
A 2 μm deep n+ layer was formed on top by ion implantation.
After forming the ion implantation layer 22 and forming a groove with a depth of 3 μm, SiO□/S i s N is deposited on the bottom and side surfaces of the groove.
4/ A capacitive insulating film 23 consisting of three layers of Si○2 is formed, and then a polycrystalline silicon 24 doped with phosphorus is formed.
embed in the groove to form a plate electrode.

Next, after depositing a 5i02 film 25 by the CVD method, an opening to serve as a seed is provided, and a selective epitaxial layer 26 is deposited to a thickness of 0.6 μm only in the opening, and then a selective epitaxial layer 26 is deposited to a thickness of 0.4 μm.
After sequentially depositing 600 polycrystalline silicon and 600 caps 5i02, a recrystallized layer 27 is formed by melting and recrystallizing the polycrystalline silicon using an argon laser.

Next, after removing the cap 5i02 film, boron ions are implanted into the recrystallized layer 27, field oxidation is performed using a selective oxidation method, and a gate oxide film with a thickness of 500 nm is formed. Form a transistor. Next, after forming the word line 28, the PSG interlayer insulating film 2
After 9 deposition, bit lines 30 are formed to complete the structure and memory element shown in FIG.

[Problem that the invention seeks to solve]

In the conventional semiconductor device manufacturing method described above, since selective oxidation is used to isolate the switching transistors, it is difficult to form isolation regions with a width of 1 μm or less.

In addition, in order to form a single crystal silicon layer on an insulating film, two methods are used: selective epitaxial growth and laser recrystallization technology.
New technologies are needed, but these technologies are not reliable enough. Further, there is a problem in that the use of high-temperature processes such as laser recrystallization and selective oxidation during the manufacturing process causes thermal diffusion of impurities, making it difficult to miniaturize. SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned problems and provide a high-density semiconductor device in which a narrow element isolation region can be easily formed.

[Means for solving problems]

A method of manufacturing a semiconductor memory device according to the present invention includes the steps of: forming an insulating film with a concave region in a predetermined portion on a semiconductor substrate to form an element formation region; A step of etching the substrate to form a groove and then forming an insulating film on the bottom and side surfaces of the groove, and etching the insulating film in other predetermined parts in the element formation region to form an opening and expose the surface of the substrate. a step of epitaxially growing a semiconductor selectively from the opening to form a semiconductor layer in the element formation region that is thicker than the insulating film surrounding the element formation region, and then forming a conductor layer over the entire surface; The method includes a step of selectively polishing and planarizing the conductor layer and the semiconductor layer.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIGS. 1(a) to 1(h) are a plan view and a cross-sectional view of a semiconductor chip shown in the order of manufacturing steps for explaining one embodiment of the present invention.

First, as shown in FIG. 1(a) and FIG. 1(b), which is a cross-sectional view taken along the line AA' in FIG. ○2 Deposit film 2,
Etch the SiO□2 film in the desired area by approximately 0.15 μm using lithography technology and dry etching technology,
A convex element region 2o whose bottom and side surfaces are surrounded is formed in the SiO□ film 2. This element formation region 20 has a concave shape of 5i0
The two are separated by a membrane 3.

Next, Fig. 1(C) and the first
As shown in Figure (d), the S
iO□ film 2 Next, the P-type silicon substrate was etched by 3 μm to form grooves 4, and then the entire surface was thermally oxidized to a thickness of approximately 10 μm.
An insulating film 5 made of a SiO□ film of 0.0000000000000000 is formed.

Next, FIG.
As shown in Figure (f), the 5i02WA2 in another predetermined portion within the element formation region 20 is etched again to form an opening 6 and expose the surface of the silicon substrate.

Next, as shown in FIG. 1(g), 5i02C(! 2
/ HC! ! / Use H2 mixed gas, 900'
Silicon is epitaxially grown selectively from the opening 6 under the condition of C50 Torr, and a silicon layer 7 thicker than the convex Si02 film 3 is deposited in the element forming region 20, followed by a SiH4/PH3/H2 mixture. Using gas at 640℃2 Torr to a thickness of about 1000mm
First polycrystalline silicon 8 is deposited on the entire surface.

Next, as shown in FIG. 1(h) and FIG. 1(i), which is a sectional view taken along the line DD', a convex 5i0
Using the second film 3 as a stopper, the first polycrystalline silicon 8 and the silicon layer 7 are polished to planarize their surfaces.

Next, as shown in FIG. 1(j), the surface of the first polycrystalline silicon 8 is thermally oxidized by about 60 people using a conventional technique.
0 silicon nitride film was deposited and further thermally oxidized to 20
A capacitor insulating film 10 having a three-layer structure made of a SiO2 film is formed, and then the trench 4 is filled with a first polycrystalline silicon 11 and its surface is insulated with a 5i02 film 12.

As shown in FIG. 1(k), the surface of the silicon layer 7 is thermally oxidized to form a gate oxide film 13, and then a gate electrode (word line) 14 is formed in a desired region on the gate oxide film. After that, arsenic is ion-implanted into the silicon layer 7 to form the source/drain 15. Next, interlayer insulation is applied to the entire surface.
After depositing 5 (16) and forming a contact hole, At'
A dynamic random memory is completed by forming wiring (bit line) 17.

As described above, in this example, a convex element formation region is formed in the 5i02 film, and the silicon layer 7 buried therein is
By selectively polishing the convex 5i02 film 3, a narrow element isolation region made of the convex 5i02 film 3 can be easily formed.
By making the step of the 02 film 3 equal to the required minimum thickness of the source/drain, parasitic capacitance can be reduced and soft errors caused by α rays can be prevented.

In the above embodiments, the epitaxial growth conditions and the first polycrystalline silicon deposition conditions are specified, but the conditions are not limited to these values, and any conditions that provide similar results may be used. Further, in the above embodiment, 5i02 was used as the insulating film for defining the element region, but other insulating films such as Si3N4 may be used. Further, as a method for forming the recesses in the insulating film forming the element region, there is also a method such as performing selective oxidation twice. Furthermore, although silicon was selectively epitaxially grown in the above embodiment, other semiconductors such as Ge and GaAs may be used.

〔Effect of the invention〕

As explained above, the present invention provides a concave element formation region in a silicon oxide film on a silicon substrate, and selectively polishes the silicon layer embedded therein, thereby easily creating a flat narrow element isolation region. This has the effect of increasing the density of the device. Furthermore, by making the step difference in the silicon oxide film equal to the thickness of the source and drain, parasitic capacitance can be reduced and soft errors caused by alpha rays can be prevented.

[Brief explanation of drawings]

FIGS. 1(a) to (k) are a plan view and a cross-sectional view of a semiconductor chip shown in order of main manufacturing steps to explain an embodiment of the present invention, and FIG. 2 is a perspective view of a conventional semiconductor memory device. 1...P-type silicon substrate, 2...S i 02 film,
3... Convex 5i02 film, 4... Groove, 5... Insulating film, 6... Opening, 7... Silicon layer, 8... First polycrystalline silicon, 10...・Capacitive insulation film, 11...
Polycrystalline silicon, 12...5i02 film, 13... Gate oxide film, 14... Gate electrode (word line), 15
...source/drain, 16...interlayer insulating film, 17
. . . AffWl line (bit line), 21 . . . P-type silicon substrate, 22 .
...5i02 film, 26... selective epitaxial layer,
27... Recrystallization layer, 28... Word line, 29...
Interlayer insulating film, 30... bit line.・"Susumu Uchihara, patent attorney?" Figure 1, shadow 1, mengyu 2 indentations

Claims (1)

[Claims] forming an insulating film with a concave region on a predetermined portion of the semiconductor substrate to form an element formation region; etching the insulating film and the semiconductor substrate at a predetermined portion within the element formation region to form a groove; forming an insulating film on the bottom and side surfaces of the substrate, etching the insulating film at other predetermined portions in the element formation region to provide an opening and exposing the surface of the substrate, and selectively forming the substrate surface through the opening. A step of epitaxially growing a semiconductor to form a semiconductor layer in the element formation region that is thicker than the insulating film surrounding the element formation region, and then forming a conductor layer on the entire surface, and selectively polishing the conductor layer and the semiconductor layer. 1. A method of manufacturing a semiconductor memory device, comprising the step of planarizing.