JPS63227112A - Clock signal supply device for cmos scf circuit - Google Patents

Abstract

PURPOSE:To obtain a filter circuit having a high performance by controlling a timing between P and N channel MOS transistors by a timing circuit, and feeding back an output signal of the filter circuit to a timing control circuit, in a clock signal supply device of a switched capacitor filter circuit. CONSTITUTION:In a switched capacitor filter (CMOS.SCF) circuit 2 provided between a signal input terminal 1 and a signal output terminal 3, a CMOS switch consisting of P and N transistors is contained, and it is opened and closed by clock signals from a first SCF clock signal line 9 and a second SCF clock signal line 10. To a feedback amplifier 4, an output signal of the circuit 2 is inputted and its output terminal is connected to an input terminal of a timing control circuit 8 through a signal line 5, and the circuit 8 controls a timing of the clock signals applied to first and second clock input terminals 6, 7, in accordance with an output signal of the amplifier 4. Thereafter, this control result is outputted to the signal line 9 and 10.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to an SCF circuit having a CMOS switch.
The present invention relates to a clock signal supply device for a CMOSSCF circuit, and more particularly to a clock signal supply device for a CMOS SCF circuit for constructing a low-noise, stable SCF circuit.

[Prior Art] Conventionally, in the clock supplied to this type of 0MO35CF (switched capacitor filter) circuit, in order to reduce the intrusion of clock noise into the signal path, P
Channel MOS transistor clock and N channel M
The circuit is configured so that the clock for the O8 transistor has a complementary relationship.

Furthermore, in order to reduce the effects caused by this slight mismatch in complementarity, the voltage slope at the clock change point is made gentler.

[Problems to be Solved by the Invention] The conventional CMOSSCF circuit described above uses a circuit that generates a fixed complementary clock.
There is a problem in that it cannot cope with initial manufacturing variations in the balance between the P-channel MOS transistor and the N-channel MO8 transistor of the OS switch and temperature variations.

This invention was made in view of such circumstances, and
It is an object of the present invention to provide a clock signal supply device for a CMOS SCF circuit that can avoid the influence of the balance fluctuation of the CMOS switch.

[Means for Solving the Problems] A clock signal supply device for a CMOS SCF circuit according to the first invention of this application is a clock signal supply device for a CMOS SCF circuit that supplies a clock signal to an SCF circuit having a CMOS switch. Switch P
A timing control circuit that controls timing between a clock signal for a channel MOS transistor and a clock signal for an N-channel MOS transistor, and a feedback amplifier that feeds back an output signal of the SCF circuit to the timing 1IilH11 circuit. do.

Further, a clock signal supply device for a CMOSSCF circuit according to the second R of this application includes a second SCF circuit into which a clock signal from the timing control circuit is input,
The feedback amplifier is characterized in that it feeds back the output signal of the second SCF circuit to the timing control circuit.

C work #11 Conventionally, the output offset voltage of the CMOSSCF circuit was not desirable, but in this invention, this S
The clock timing is feedback-controlled by actively utilizing the output offset voltage of the CF circuit. This provides an optimal lock signal.

That is, the DC output offset voltage of the SCF circuit has a correlation with the phase and complementarity of the clock, and the offset is theoretically zero in the optimal state. This invention has been made with attention to this point, and includes an output offset (1'R light) of the SCF circuit or an output offset (1'R light) of the second SCF circuit connected to the output terminal of the timing control circuit. 2 invention). The feedback amplifier and the timing control circuit constitute a feedback loop, and the clock timing control circuit controls the clock timing so that the output offset of the SCF circuit or the second SCF circuit becomes the output potential.

[Example] Next, an example of the present invention will be specifically described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the first invention. Reference numeral 1 is a signal input terminal of the CMOSSCF circuit 2, and reference numeral 3 is a signal output terminal of the CMOSSCF circuit 2. This 5CF (switched capacitor filter)
Circuit 2 has a CMOS switch that receives a first SCF clock signal #! 9 and second S
It is opened and closed by a clock signal input from the CF clock signal line 10.

The feedback amplifier 4 receives the output signal of the CMOSSCF circuit 2, and its output terminal is connected to the input terminal of the timing control circuit 8 via the output signal line 5 of the feedback amplifier 4.

The timing control circuit 8 outputs the timing between the clock signals applied from an appropriate clock source (not shown) to the first clock input terminal 6 and the second clock input terminal 7 from the output of the feedback amplifier 4. Control according to signals. Then, the timing control circuit 8 outputs the control result to the first scF clock signal line 9 and the second SCF clock signal 810.

In the device configured in this manner, the output signal of the timing control circuit 8 is transmitted to the CMOSSC via the first SCF clock signal line 9 and the second SCF clock signal line 10.
It is input to F circuit 2.

The timing control circuit 8 controls the clock timing to the SCF circuit 2 based on the output signal of the feedback amplifier 4 so that the output terminal 3 of the CMOS SCF circuit 2 has a DC zero potential. The feedback amplifier 4 also has a frequency compensation tr1 function for improving the stability of the feedback loop of the timing control circuit 8, the SCF circuit 2, the feedback amplifier 4, and the timing control circuit 8.

FIG. 2 is a block diagram showing an embodiment of the second invention. In FIG. 2, the same parts as in FIG. 1 are given the same reference numerals, and their explanations will be omitted. The second CMO8SCF circuit 11 has its input terminal 13 equivalently grounded, and outputs only a DC offset voltage to its output terminal. This second 0MO
The 3SCF circuit 14 is prepared as a dummy circuit for the CMOSSCF circuit 2, and the CMOS switch used therein has a structure equivalent to that of the CMOSSCF circuit 2. This CMOS switch connects the first SC
It is opened and closed by the clock signal input from the F clock signal 1a14 and the second SCF clock signal line 15.

First and second clock signal lines 14.15 are connected to first and second clock signals 19.10, respectively.

The output signal @112 of the second SCF circuit 11 is connected to the input terminal of the feedback amplifier 16.

The feedback amplifier 16 operates so that the DC offset voltage output of the second CMO8SCF circuit 11 becomes zero.
The timing control circuit 8 is feedback-controlled via the feedback amplifier output signal line 17.

The timing control circuit 8 controls the timing between the clock signals applied to the first clock input terminal 6 and the second clock input terminal 7 according to the output signal of the feedback amplifier 16. The control result is the first SC
F clock signal line 9 and second SCF clock signal line 1
Output to 0.

In the device configured in this way, the clock signals from the timing control circuit 8 are commonly transmitted via the first SCF clock signal lines 9 and 14 and the second SCF clock signal line 10.15. , are input to the CMOSSCF circuit 2 and the second CMOSSCF circuit 11. The timing of this clock signal is controlled so that the DC offset voltage of the second CMOSSCF circuit 11 becomes zero.

Therefore, the clock is supplied to the SCF circuit 2 at optimal timing. Here, timing control circuit 8→second S
The stability of the feedback loop consisting of the CF circuit 11 → feedback amplifier 16 → timing control circuit 8 is as follows.
This is ensured by appropriately selecting the transfer functions of the second CMOSSCF circuit 11 and the feedback amplifier 16.

In this embodiment of the second invention, the offset of the second SCF circuit 11 is used for the signal used for feedback, and the CMOSSCF circuit 2 is not included in the feedback loop. Therefore, in this second embodiment, CMOS
This has the advantage that the degree of freedom in designing the SCF circuit 2 is not hindered. In other words, the CMOSSCF circuit 2 can be freely designed without imposing the condition of feedback loop stability.

[Effects of the Invention (1) As explained above, the present invention has the effect that a high-performance SCF circuit can be easily realized because a clock can always be supplied at an optimal timing by feedback.

In addition, since high-speed SCF circuits require extremely precise lock timing, it was difficult to achieve with conventional SCF circuits, but according to the present invention, precise lock timing is guaranteed by feedback action, so this high-speed SCF circuit requires very precise lock timing. Another advantage is that an SCF circuit can be easily realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a clock supply device for a CMOSSCF circuit according to an embodiment of the first invention, and FIG. 2 is a block diagram of a clock supply device for an 0MO3SCF circuit according to an embodiment of the second invention. 1: Signal input terminal, 2: CMOSSCF circuit, 3: Signal output terminal, 4, 16: Feedback amplifier, 5.17
; Feedback amplifier output signal line, 6: First clock input terminal, 7: Second clock input terminal, 8: Timing control circuit, 9; First SCF output signal line, 10
;Second SCF clock line, 11;Second CMO
SSCF circuit

Claims (2)

[Claims] (1) In a clock signal supply device for a CMOS SCF circuit that supplies a clock signal to an SCF circuit having a CMOS switch, the P-channel MO of the CMOS switch
The present invention is characterized by comprising a timing control circuit that controls timing between a clock signal for an S transistor and a clock signal for an N-channel MOS transistor, and a feedback amplifier that feeds back an output signal of the SCF circuit to the timing control circuit. CMOSSCF
Circuit clock signal supply device. (2) In a clock signal supply device for a CMOS SCF circuit that supplies a clock signal to an SCF circuit having a CMOS switch, the P-channel MO of the CMOS switch
a timing control circuit that controls the timing between the clock signal for the S transistor and the clock signal for the N-channel MOS transistor; a second SCF circuit to which the clock signal from the timing control circuit is input; and the second SCF circuit. A clock signal supply device for a CMOSSCF circuit, comprising a feedback amplifier that feeds back an output signal of the circuit to the timing control circuit.