JPS6322678Y2 - - Google Patents
Info
- Publication number
- JPS6322678Y2 JPS6322678Y2 JP1983008664U JP866483U JPS6322678Y2 JP S6322678 Y2 JPS6322678 Y2 JP S6322678Y2 JP 1983008664 U JP1983008664 U JP 1983008664U JP 866483 U JP866483 U JP 866483U JP S6322678 Y2 JPS6322678 Y2 JP S6322678Y2
- Authority
- JP
- Japan
- Prior art keywords
- external
- lead
- insulator
- external leads
- leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 15
- 239000012212 insulator Substances 0.000 claims description 8
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims description 3
- 239000011347 resin Substances 0.000 description 28
- 229920005989 resin Polymers 0.000 description 28
- 230000015556 catabolic process Effects 0.000 description 2
- 230000003014 reinforcing effect Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP866483U JPS59115653U (ja) | 1983-01-25 | 1983-01-25 | 絶縁物封止半導体装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP866483U JPS59115653U (ja) | 1983-01-25 | 1983-01-25 | 絶縁物封止半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59115653U JPS59115653U (ja) | 1984-08-04 |
| JPS6322678Y2 true JPS6322678Y2 (US20020128544A1-20020912-P00008.png) | 1988-06-22 |
Family
ID=30140147
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP866483U Granted JPS59115653U (ja) | 1983-01-25 | 1983-01-25 | 絶縁物封止半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59115653U (US20020128544A1-20020912-P00008.png) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0419799Y2 (US20020128544A1-20020912-P00008.png) * | 1986-05-22 | 1992-05-06 | ||
| JPH0451489Y2 (US20020128544A1-20020912-P00008.png) * | 1987-03-31 | 1992-12-03 | ||
| KR102192997B1 (ko) * | 2014-01-27 | 2020-12-18 | 삼성전자주식회사 | 반도체 소자 |
| JP6373332B2 (ja) * | 2016-11-24 | 2018-08-15 | 三菱電機株式会社 | パワーモジュールの製造方法 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58209147A (ja) * | 1982-05-31 | 1983-12-06 | Toshiba Corp | 樹脂封止型半導体装置 |
-
1983
- 1983-01-25 JP JP866483U patent/JPS59115653U/ja active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58209147A (ja) * | 1982-05-31 | 1983-12-06 | Toshiba Corp | 樹脂封止型半導体装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59115653U (ja) | 1984-08-04 |
