JPS6322488B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a transfer function estimator that requires few calculations and has fast convergence, and can be used as an echo canceller in telecommunications. First, the role of this type of device will be explained. FIG. 1 is a diagram related to this. EP in the figure
is the echo path, and SEP is the estimated echo path.
SUB is a subtracter that works to subtract the signal at the terminal marked (-) from the signal at the terminal marked (+) in the diagram. S ₁ and S ₂ are samplers that sample signals at regular intervals T seconds. S ₁ and S ₂ work together. FKC is the output of subtractor SUB and I0
Performs high-speed Kalman control operation based on point signals.
This is a fast Kalman controller that calculates the estimated value of EP, SEP. DL ₁ and DL ₂ are T-second delay elements and are connected to FKC.
This is to adjust the delay difference between EP and SEP.
The part that integrates SUB SEP FKC DL ₁ DL ₂ is the transfer function estimator TS. Next, the operation of the transfer function estimator TS will be explained. A signal having a frequency band of 0 to 1/2T (Hz) is input from the signal input point I. This passes through the echo path EP and is sampled by the sampler _S1 with a cycle of T seconds, and after being delayed by T seconds at _DL1 , it enters the subtracter SUB with a positive sign. On the other hand, the signal input from signal emphasis point I is sampled.
It passes through _S2 and becomes a signal sampled at a period of T seconds, and reaches the input point I0 on the signal input side of TS. Point I0
The signal that enters the transfer function estimator TS passes through the T-second delay element DL ₂ , the estimated echo path SEP, and the subtracter.
Enter SUB with negative sign. The output of SUB is output to error output point 0 as an error output. fast kalman controller
FKC minimizes the error in the sense of minimizing the sum of the squares of the outputs of point 0, so that the estimated echo path SEP is optimized. It operates based on the error output. In other words, the transfer function estimator TS converts the estimated echo path SEP into the echo path EP
It works to minimize the error output by approximating as much as possible. Please note that the effects of DL ₁ DL ₂ cancel each other out. This is necessary for the operation of the fast Kalman controller FKC, and its effects will be discussed in the FKC section. The transfer function estimator TS has a sampler S ₂ just before the input and works in sampling mode, but the signal entering the signal input point I is in the range of 0 to 1/2T (Hz) and satisfies the Nyquist sampling condition. Therefore, the above does not result in any reduction of information, and if you want to use the signal at the error output point 0 as a continuous signal, for example when using it as an echo canceller, then after the point 0, 0 to 1/ All you need to do is install a low frequency device that passes 2T (Hz). Next, the conventional fast Kalman control transfer function estimator
The method for configuring the TS will be described with reference to FIG. 2, which is a diagram of its configuration. This conventional method is described by LJUNG, Fast
Calculation of Gain Matrices for Recursive
Estimation Schemes CINT, J.Control, 1978,
It is described in detail in Vol.27No.1 1-19p.
After explaining the conventional method, we will sequentially show how to configure the transfer function estimator TS based on the present invention. Figure 2 shows the conventional TS configuration method. In Fig. 2, in order to completely correspond with Fig. 1, echo path EP,
Samplers S ₁ and S ₂ have also been added. In Figure 2
TDL ₁ and TDL ₂ are tap lengths M ₁ M−1 (M
is an integer that can be given arbitrarily), a tapped delay line, HR, AR, SR, DR, kR are register groups, MUL ₁ to MUL ₁₃ are multipliers, G ₁ is a line concentrator,
1N ₁ 1N ₂ is a reciprocal number generator, I is a unit number generator,
DI ₁ DI ₂ is a dimension intensifier, DD ₁ is an inverse dimension detector, DL ₃ , DL ₄
are T-second delay elements like DL ₁₁ and DL ₂ . In addition, as in Figure 1, S ₁ and S ₂ are samplers that sample the signal every T seconds, EP is the echo path, SEP is the estimated echo path, FKC is the fast Kalman controller, point I is the signal input point, and point 0 is the error. The output point, point EP0, is the input point on the echo path side, and I0 is the input point on the input side. The operation of the conventional system shown in FIG. 2 at time i will be described below. First, the estimated echo path SEP will be explained. Tapped delay line TDL ₁ is transfer function estimator
The input signal at time i (i is a time variable that takes an integer value) at input point I0 on the input side of TS is
If g _i An input vector x _i is generated. register group HR
stores the tap vector h _i of M elements, which is the state of the estimated echo path SEP. Multiplier MUL ₁ is a part that mutually multiplies corresponding elements of x _i and h _i .
G ₁ is the part that sums up the MUL ₁ output, and _is
The two parts of G ₁ perform the operation y^ _i =x _i ^T h^ _i (2) to generate the scalar quantity y _i . In this application, T represents the transposition of a matrix. Estimated echo path
The SEP output is y^ _i given by equation (2). The error e _i of this transfer function estimator is the signal y _i in which the estimated transfer function EP output is delayed by T seconds and the above SEP output.
It is the difference from y^ _i and is given by e _i =y _i −y^ _i (3). The update of h^ _i is performed as follows by the action of the multiplier MUL ₁₃ and the adder AD using the M-element vector k _i which is the output of the k register kR and the scalar quantity e _i described above. In other words, by MUL ₁₃ , we obtain the increment Δh^ _i of h^ _i shown by Δh^ _i =k _i e _i (4). Using this, we obtain h^ _i+1 = h^ _i+1 + Δh^ _i (5 ) Obtain the value of h^ _i at the next time i+1 given as ). Note that the contents k _i of the k register kR are also updated every time. This update is performed in each part of the fast Kalman controller FKC except MUL ₁₃ . This will be described below, but first, for convenience of explanation, a description using the elements of k _i will be shown. That is, k _i is It is. The operation of the fast Kalman controller FKC will be described below. This part inputs the input signal g _i at the input point I0 on the input side and outputs the change information Δh^ _i of the HR register to be supplied to the adder AD. The operation of FKC will be described step by step from input to output. The signal at the input of the T second delay element DL ₃ is that of point I0, g _i . Also, the output u _i of the tapped delay line TDL ₂ is an M-1 dimensional vector, It can be written as Also, the output of the T-second delay element _DL4 is, of course, g _iM . In DL ₃ during FKC, the signal g _i of the time slot immediately before the signal g _{i -1} that is currently being input is required, and DL ₁ DL ₂ is used for time adjustment for this purpose. Now, g _i and u _i are introduced into the dimension multiplier DI ₁ , and u _i and g _iM are also introduced into the DI ₂ . DI ₁ is a part that generates a vector x _i+1 that is one dimension larger than u _i based on u _i given to g _i by equation (3). Note that x _i is given by equation (1) and is the tapped delay line TDL ₁ output vector, and x _i+1 is x _i
This is the state after one time slot. Of course x _i+1 It is expressed as Similarly, the output of the dimension multiplier DI ₂ is x _i given by equation (1). These g _i , x _i+1 , x _i ,
g _iM and subtractor SUB output e _i respectively
Each of the update calculation units A, S, D, and k shown as PTA, PTS, PTD, and PTk operates. These parts are registers AR, SR,
This is the part for updating the contents of DR and kR. The operations of each of these update calculation units are performed in the order described here, that is, in order from top to bottom in FIG. First, the operation of the update calculation unit A, that is, the PTA will be explained.
The inputs of this part are g _i of the T-second delay element DL ₃ input, x _i of the dimension multiplier output, and the aforementioned k _i which is the output of the k register kR. In this case, A register AR is the stored value of AR regarding the previous time slot.
A numerical value called _i-1 is memorized and generated. A _i-1 is is an M-element vector given by Multiplier MUL ₂
By the action of the adder AD ₁ , q _i =g _i +A _i-1 x _i (10) is obtained based on each signal of A i- ₁ , x _i , g _i . q _i is a scalar quantity. Next, _{the multiplier} MUL _{3 and the} subtracter
By the action of SUB ₁ , find the value A _i stored in the A register at this time slot as A _i = A _i-1 − k _i q ^T 〓 (11) and put it in the A register AR to update the A register. . From now on, the AR register generates the current value A _i . The above is update calculation part A
In other words, it is the operation of PTA. Next, the operation of the update calculation unit S, that is, the PTS will be described. The inputs of this part are AD ₁ output q _i , AR output A _i , DL ₃ input g _i and dimension multiplier DI ₂ output x _i . Among these, A _i and x _i are M-element vectors, and the others are scalar quantities. First, the multiplier MUL ₄ and the adder AD ₂ act to generate the value v _i =g _i +A ^T 〓x _i (12) as the output of the adder AD ₂ . This is a scalar quantity. Then multiplier MUL ₅ and adder AD ₃
By the action of S _i =S _i-1 +v _i q _i (13) is calculated and the contents of the S register SR are updated from S _i-1 to S _i which is the contents at the current time. This is the update part S,
This is the operation of PTS. Next, the operation of update calculation unit D and PTD will be described. The input for the operation of this part is the adder AD ₂ output
v _i , S register SR output S _i , A register AR output A _i ,
k register kR output k _i , T seconds delay element DL ₄ output
g _iM is the dimension intensifier DI ₁ output _i+1 and the unit number generator I output which generates the number 1. First, there is an inverter IN ₁ that generates the reciprocal of its input as an output, and a multiplier MUL _6.
Due to the action of , a scalar quantity S _i ^-1 v _i is generated as the MUL ₆ output. S _i ^-1 is the reciprocal of S _i . Then A _i and S _j ^-1 v _i
The product A _i ^-1 v _i is obtained by the action of the multiplier MUL ₇ .
Since A _i is an M-element vector, this quantity becomes an M-element vector. The sum of this and the output of k register kR is taken by adder _AD4 . That is, the output of adder AD ₄ becomes k _i +A _i S _i ^-1 v _i . This is of course an M-element vector. The dimension multiplier DI ₃ constructs a new M+1-dimensional vector _i in which the M-element vector k _i +A _i S _i ^-1 v _i is arranged under the scalar quantity S _i ^-1 v _i of the MUL ₆ output.
In other words, mathematically It can be written as This _i is generated as DI ₃ output. Next, the above _i is divided into two by the action of the dimension reducer DD ₁ to generate an M-dimensional vector m _i and a scalar w _i . here It is given as w _i =f _M+1i (16). D register DR This is the value of the D register at the previous time, and an M-element vector represented by D _i-1 is being generated, but this value D _i-1
Based on the dimension multiplier DI ₁ output x _i+1 and DL ₄ output g _iM , by the action of multiplier MUL ₈ and adder AD ₅ ,
Generates a scalar quantity represented by r _i . Expressed mathematically, it is expressed as r _i =g _iM +D ^T _i-1 x _i+1 (17). Then DR output D _i-1 and DD ₁ output m _i and AD ₅ output r _i to multiplier MUL ₁₀ , subtractor
Due to the action of SUB ₃ , D _i-1 −m _i r _i is generated as the SUB ₃ output. Also, unit value generator I output 1 and AD ₅
Multiplier MUL ₉ based on output r _i and DD ₁ output w _i ,
1 due to the action of subtractor SUB ₂ and reversor 1N ₂
[1-r _i w _i ] ^-1 is generated as _N2 output. 1N ₂ is a part that generates the reciprocal of its input as an output. Next, as the multiplier MUL ₁₁ output [D _i-1 −m _i r _i ]
The product of and [1-r _i w _i ] ^-1 is taken, and this is entered into the D register as a new D _i , and the contents of the D register are updated. That is, it is expressed mathematically as D _i = [D _i-1 −m _i r _i ^T ] [1− w _i r _i ] ⁻¹ (18). Of course, D _i is an M-element vector. The above is the operation of the update calculation unit D PTD. Next, the operation of update calculation unit k and PTk will be described. The inputs to this part are the D register DR output D _i , the dimension reducer DD ₁ output w _i as well as m _i and the output k _i of the k register. The operation of k _i+1 = m _i −D _i w _i (19) is performed by the action of multiplier MUL ₁₂ S and subtractor SUB ₃ , and the value of k register for the next time is calculated.
k _i+1 is found. Of course, as shown in equation (6), k _i is M
It is an original vector. In this way, k _i is updated and the input signal g _i+1 for the next time is awaited. The above is the conventional fast Kalman transfer function estimator TS
The estimated echo path SEP and the operation of the fast Kalman controller FKC in . In this way, the conventional fast Kalman estimator TS uses a sampler every T seconds.
Read the data while operating S ₁ S ₂ , operate the estimated echo path SEP fast Kalman controller FKC, update the H register HR, A register AR, S register SR, D register DR, and k register kR. echo the contents of _the path
Approach EP, resulting in error output point output
Works to reduce e _i . Note that the initial value of each register can generally be arbitrary, but generally let h ₀ k ₀ be a 0 vector, A ₀ be a scalar with a 0 value, and D ₀ be a 0 vector.
For S ₀ , it is usual to use an arbitrary value δ that is slightly larger than the error power generated inside the echo path EP. In this method, if there are no fluctuations or noises in the echo path EP, convergence will occur after the input g _i corresponding to the number of time slots twice the number of taps M of the tapped delay line TDL ₁ is input. If noise occurs during EP, the convergence speed will be slightly slower. Although the fast Kalman transfer function estimator has a relatively fast convergence speed as described above, it cannot be said that it has a convergence speed that is sufficient for practical use. The present invention is intended to improve the above-mentioned drawbacks of the conventional technology, and its purpose is to suppress the calculation speed per adjustment to about twice that of a conventional high-speed Kalman transfer function estimator, while increasing the convergence speed to a value of about 10 times. The objective is to provide a transfer function estimator that has improved to
A feature of the present invention for achieving this purpose is that in a fast Kalman-type transfer function estimator, an adder ADC ₂
By configuring the transfer function estimator by placing a complex conjugate value generator immediately after it, and by changing other parts of the device to handle complex time functions, it is possible to operate properly even under complex signal input. There is a fast Kalman type complex transfer function estimator that can perform this. This will be explained in detail below. Before describing the application of the band division method, which is a main part of the present invention, an improvement to the conventional fast Kalman transfer function estimator shown in FIG. 2, which is a part of the present invention, will be described. FIG. 3 is a diagram of a complex fast Kalman transfer function estimator that forms part of the present invention. In FIG. 3, P ₁ ...P ₄₈ are defined. This is mainly used to show the relationship between the figures following FIG. 4 and FIG. 3. FIG. 3 is a diagram in which a conjugate complex number generator C inserted between P ₂₅ P ₂₆ is added to the configuration of FIG. 2, which is superficially a conventional diagram. FIG. 3 will be explained below. Everything that was previously stated with respect to the conventional scheme of FIG. 2 holds true with respect to the complex fast Kalman transfer function estimator of FIG. However, in this case, all the numbers handled in Figure 3 are changed from real numbers in Figure 2 to complex numbers, all coefficients and signals in each register are made into complex numbers, and multipliers, adders, etc. all perform complex number operations. do. That is, although the apparent changes between FIGS. 2 and 3 are very small, there are actually very large changes. Although the configuration shown in FIG. 3 is not necessary for a transfer function estimator that handles real-time signals such as audio signals, it is necessary to handle complex time functions as in the main part of the present invention that applies band division. If this is not possible, it is absolutely necessary. The newly added complex conjugate value generator C outputs the real part of the input as it is, and outputs the imaginary part with its sign changed. That is, it is a part that generates the conjugate complex number of the input as an output. Also, in order to distinguish it from the conventional configuration shown in Figure 2, the transfer function estimator TS and fast Kalman controller in the conventional configuration are
FKC, estimated echo path SEP, subtractor SUP, and delay elements DL ₁ DL ₂ correspond to each part of the complex type fast Kalman transfer function estimator, respectively. They are expressed as an estimated echo path SEPC, a complex subtractor SUBC, a complex T-second delay element DLC ₁ DLC ₂ , etc. In addition, in order to show that the sampler S ₁ S ₂ handles complex values, the complex sampler SC ₁ SC ₂ is used in FIG.
Shown as Furthermore, in order to indicate that each component of SEPC FKCC handles complex numbers, the letter C is added after each symbol in FIG. 2 in FIG. 3 to indicate that it is a part that handles complex numbers. That is, TDLC ₁ TDLC ₂ are complex tapped delay lines with tap lengths M and M-1, respectively,
HRC ARC SRC DRC kRC are each complex registers, MULC ₁ to _{MULC 13} are complex multipliers, ADC ₁
~ADC ₅ is a complex adder, SUBC ₁ ~ SUBC ₃ is a complex subtractor, GC ₁ is a complex concentrator, DLC ₃ DLC ₄ is a complex T
This is a second delay element. Also, DIC ₁ DIC ₂ DIC ₃ is a complex dimension multiplier, and DDC ₁ is a complex dimension reducer. Also the same
PTAC, PTSC, PTDC, and PTkC are complex update calculation units A, S, D, and k, respectively. INC ₁ INC ₂ is a complex reciprocal generator. The unit numerical value generator of I has the same configuration as in FIG. 2, so the symbol is not changed. Due to this structural change, in the complex type fast Kalman transfer function estimator, equation (13) changes to S _i = S _i-1 + v〓 _i q _i (13)', and equation (14) The left side is Changes to Other expressions can be used as is, but all letters in the expressions must represent complex numbers. That is, equations (1) to (12), (15) to (19) are established as equations representing complex numbers, and equations (13) and (14) are replaced with equations (13)'(14)', respectively. In order to handle complex time functions in this way, it is necessary to introduce a complex conjugate value generator C. Next, the detailed configuration of each part in FIG. 3 is shown in FIG. 4 and subsequent figures.
Although the case where the number of taps M of the tapped delay line is three is shown, M may be arbitrary and the configuration shown here does not impair the arbitrariness of the number of M. FIG. 4 is a detailed diagram of a composite form of the complex T-second delay elements DLC ₁ to DLC ₄ . This diagram happens to coincide with the diagram of the entire complex T-second delay element. The complex form is a system that collectively represents the real and imaginary parts, which are the constituent elements of a complex number, whereas the divided form is a system that represents these elements separately. The lead wires for transmitting complex numbers are shown as single lines as in the representation in FIG. That is, each solid line consists of two lines, a real number line and an imaginary number line. In Figure 4, DLC is T
Represents a complex delay line in seconds. FIG. 5 shows the same part as FIG. 4 in a divided representation. The dotted line represents a lead line for real numbers, and the dashed line represents a lead line for imaginary numbers. The part marked DL in FIG. 5 is a T-second delay line for real numbers. In this way, we will use both of these complex and divided forms depending on the need for accurate description and ease of expression. As can be seen from FIG. 5, DLC ₁ to DLC ₄ can be realized by shift registers operating with a T second clock. Figure 6 is a detailed diagram of the composite form of TDLC ₁ .
Since the value of tap M is 3, _P5 consists of 3 points. These points are designated as P ₅₁ P ₅₂ P ₅₃ in order of decreasing delay as shown in the figure. Figure 7 is the same
This is a split representation of TDLC ₁ . DLCDL was explained in the sections related to Figures 4 and 5. Figure 8 is
FIG. 3 is a detailed view of the composite form of TDLC ₂ . P ₁₀ is made up of two points. These are also designated as P ₁₀₁ P ₁₀₂ as shown in the figure in order of decreasing delay. As shown in FIGS. 6 and 7, when P _i (i is an integer) consists of a plurality of lead wires, a subscript is added after i to indicate it in detail. Figure 9 shows a complex multiplier
FIG. 2 is a diagram showing the configuration of MULC ₁ in a composite form.
Each complex multiplier MULC _{1i (} i=
1, 2, and 3) are each a single complex multiplier, and if the configuration of, for example, MULC ₁₁ is written in a divided form, it becomes as shown in FIG. In Figure 10, MUL ₁₁₁ ~
MUL ₁₁₄ is a single real multiplier, ADM ₁₁ ADM ₁₂ is a real adder, and SIM ₁₁ is a normal sign inverter. These can be constructed from the same hardware as currently used electronic desktop calculators. FIG. 11 is a diagram showing the complex line concentrator GC ₁ in a divided form. G ₁₁ and G ₁₂ are ordinary real adders. Figure 12 shows a complex adder
The structure of ADC ₂ and complex register HRC is shown in divided form at the same time. AD ₂₁₁ to _{AD 232} are single adders HR ₁₁₁₁ to _{HR 1132} are each 1 character RAM
(RANDOM ACSESS Memory).
Figures 13 and 14 are the composite form of the subtractor SUBC, respectively.
This is a description of the divided form. Here, the part marked SUBC is of course a complex number subtracter, and the part marked SUB is a real number subtracter. The sign of +- here is +
Indicates that the value obtained by subtracting the signal value input from the terminal marked - from the signal value input from the terminal marked - is output. In order to deepen our understanding of complex numbers and to show the situation of complex operations that are actually performed, we have described operations based on real number division using the notation of the divided form. Figures 5 and 7 show delay calculations using real number division for complex number calculations, and Figure 10 shows the delay calculations shown in Figure 9.
11 shows an operation method using real number division for complex number multiplication, FIG. 11 shows an addition method, and FIG. 14 shows a calculation method using real number division for subtraction. This seems to have provided a detailed explanation of complex number operations other than the real number division operations of the complex conjugate generator shown as C and the complex reciprocal generators of IN ₁ and IN ₂ . Except for the explanation regarding C, explanations will be given in complex form. Figures 15 and 16 are complex multipliers, respectively.
It is a detailed diagram of DIC ₁ DIC ₂ . This consists only of connections between terminals. Figure 17 shows the multiplier MULC ₂
FIG. MULC ₂₁ to MULC ₂₃ are complex multipliers, and GC ₂₁ is a complex adder. Figure 18 is an adder
It is a diagram of ADC ₁ . It can be seen that ADC ₁ consists of one complex adder. Figure 19
This is a detailed diagram of MULC ₃ . MULC ₃ is MULC ₃₁ ~
It consists of MULC ₃₃ single complex multiplier. Figure 2
0 is a detailed diagram of the subtractor _SUBC1 . this is
It consists of three complex subtracters SUBC ₁₁ to SUBC ₁₃ . Next, a detailed diagram of the ARC is shown in FIG. 21. This consists of three complex registers, ARC ₁ to _{ARC 3} . The above is a detailed diagram of each part of the complex update calculation unit A and PTAC. Next, a detailed diagram of each part constituting the complex update calculation unit S and PTSC will be shown. FIG. 22 is a detailed diagram of MULC ₄ . It consists of complex multipliers MULC ₄₁ to MULC ₄₃ and an adder GC ₄₁ . FIG. 23 is a detailed diagram of adder ADC ₂ . This is a single adder
Consists of ₂ ADCs. FIG. 24 is a detailed diagram of the complex conjugate value generator C drawn in divided form. SC
is a sign inverter that changes the sign of the input signal and generates it at the output. FIG. 25 is a detailed diagram of multiplier _MULC5 . It consists of one complex multiplier MULC ₅ . FIG. 26 is a detailed diagram of adder _ADC3 .
This also consists of one adder _ADC3 .
FIG. 27 is a detailed diagram of the S register SRC. This consists of one complex register SRC.
FIG. 28 is a detailed diagram of the complex inverter INC ₁ , which is described in divided form. MULI ₁₁ to MULI ₁₄ are real multipliers, and SQ ₁ is a square root generator that generates the square root value of the input as an output, which can be realized using the same method used in electronic desktop calculators. IN ₁₁
is a reciprocal value generator that generates the reciprocal of an input value as an output, and this can also be realized using the same method used in electronic desktop calculators.
SCI ₁ is a sign inverter and has the same configuration as that used in the complex conjugate value generator of FIG. 24, and can be realized by changing the sign bit in an analog circuit or an inverting amplifier in a digital circuit. In the entire 1N ₁ circuit shown in Figure 28, for the input value at point P ₂₆ having the value (a + jb), the output is at point P ₃₀ .

[Expression] Generates the value. Figure 29 is a detailed diagram of the complex multiplier MULC ₆ .
Consists of one MULC ₆ . FIG. 30 is a detailed diagram of the complex multiplier _MULC7 . It consists of three complex multipliers MULC ₇₁ to MULC ₇₃ . FIG. 31 is a detailed diagram of the complex adder ADC ₄ , which consists of three complex adders ADC ₄₁ to ADC ₄₃ . FIG. 32 is a detailed diagram of the complex dimension multiplier DIC ₃ . This consists only of connections between terminals. FIG. 33 is a detailed diagram of the complex dimension reducer _DDC1 . This also consists only of connections between terminals. FIG. 34 is a detailed diagram of the complex multiplier _MULC8 . This consists of complex multipliers MULC ₈₁ to MULC ₈₃ and adder GC ₈₁ . FIG. 35 is a detailed diagram of the complex adder ADC ₅ . This is a single adder
It consists of ADC ₅ . Figure 36 shows a complex multiplier
This is a detailed diagram of MULC ₉ . It consists of a single complex multiplier MULC ₉ . Note that the unit number generator I is a part that generates a value of 1, and can be constituted by a power supply in an analog circuit, and a ROM (Read Only Memory) that stores a value of 1 in a digital circuit. FIG. 37 is a diagram of the complex subtracter _SUBC2 . SUBC ₂ consists of a single complex subtractor SUBC ₂ . FIG. 38 is a detailed diagram of the reversing device IN ₂ , drawn in a divided form. MULI ₂₁ ～
MULI ₂₄ is a real multiplier, SQ ₂ is a square root generator,
IN ₂₁ is the reciprocal generator. SCI ₂ is a sign inverter. FIG. 39 is a block diagram of the complex multiplier MULC ₁₀ . This consists of complex multipliers MULC ₁₀₁ to MULC ₁₀₃ . FIG. 40 is a block diagram of the complex subtracter _SUBC3 . This is three complex subtractors SUBC ₃₁
~ Consists of SUBC ₃₃ . Figure 41 shows a complex multiplier
FIG. 2 is a configuration diagram of MULC ₁₁ . This is a complex multiplier
It consists of MULC ₁₁₁ to MULC ₁₁₃ . Figure 4
2 is a configuration diagram of the D register DRC. this is
It consists of three registers DRC ₁ to DRC ₃ .
This concludes the detailed explanation of the configuration of each part of the complex update calculation unit D and PTD.
We will explain each part of PTk. FIG. 43 is a detailed diagram of the complex multiplier MULC ₁₂ .
It consists of a single complex multiplier MULC ₁₂₁ to MULC ₁₂₃ . FIG. 44 is a detailed diagram of the complex subtracter _SUBC3 . This is three single complex multipliers
Consists of SUBC ₃₁ to _{SUBC 33} . Figure 45 is k
FIG. 3 is a detailed diagram of register kRC. It consists of three single complex registers _kRC1 to _kRC3 . This concludes the detailed explanation of each part in Figure 3.
Any part can be realized using conventionally known hardware. Conventional transfer function estimator in Figure 2
TS can only handle real-time input, and since the internal coefficients are real numbers, the echo path EP has real impulse characteristics, and it only works when the input signal input from signal input point I is a real-time function. do. However, the complex type fast Kalman type transfer function estimator that forms part of the present invention operates even when one or both of the above conditions are not satisfied, and the complex estimated echo path SEPC cannot estimate the impulse characteristic of the echo path EP. I can do it. Complex fast Kalman transfer function estimator TSC
In Fig. 3, which is a diagram regarding ) When a band-limited signal with a narrower bandwidth of 2π/NT (radians/second, N is a certain natural number) comes in, the
The tap interval for TDL ₁ C and TDL ₂ C is now NT seconds instead of the original T seconds. Here, a band-limited signal is a signal whose behavior within the band does not matter, but whose influence outside the band is zero. The above facts will be proven below. The frequency characteristic of a transversal filter with a tap interval of NT seconds repeats the same characteristic with a period of 2π/NT (radian/second). By the way, if this transversal filter has complex coefficient values and its real and imaginary coefficient values can change independently, it can change from -π/NT (radian/second) near DC to π/NT (radian/second). The frequency domain characteristics of can be arbitrarily given using the sampling theorem. Therefore, due to the above-mentioned periodicity, it is possible to arbitrarily determine the characteristics over a bandwidth of 2π/NT (radians/second) at any position on the frequency axis for a complex coefficient value transversal filter with a tap interval of NT seconds. I can do it. Therefore, for a band-limited signal whose bandwidth is limited to 2π/NT (radians/second), this complex coefficient transversal filter with a tap interval of NT seconds can provide arbitrary transfer function characteristics. For the above reasons, TDL ₁ C, which is the delay for the transversal filter in Figure 3,
TDL ₂ C may be a tap interval of NT (seconds). This concludes the proof. By the way, a transversal filter with a tap interval of NT of real coefficients does not have the properties described here, because such a transversal filter has a frequency centered at 2πi/NT (radians/second, i is an integer) This is because it has only symmetrical characteristics, so it is not possible to give any characteristic to any part on the frequency axis. Now, let's consider the operation of the configuration shown in FIG. 46 based on the above knowledge. TSC as TSCN in Figure 46
What is followed by N is the Kalman-type complex transfer function estimator TSC, which is a delay element array with a tap interval NT that is N times the sampling interval T seconds of the sampler.
It is a "complex type fast Kalman transfer function estimator with a tap interval of NT seconds" with TDLC ₂ . similarly
FKCCN and SEPCN are respectively "complex fast Kalman controllers with a tap interval of NT", and SEPCN is a "complex estimated echo path with a tap interval of NT seconds". Figure 4
6, SC ₁ and SC ₂ are complex samplers every T seconds, and EPC is a complex echo path. The names of the points are in accordance with FIG. 1. FILN is a bandpass filter that has a bandwidth of 2π/NT (radians/second) and is located at an arbitrary position on the frequency axis. In view of the above points, the estimated echo path SEPCN with tap interval NT is determined by the bandpass filter FILN.
Since it is possible to give arbitrary characteristics in the passband of the complex adder ADC in this configuration,
TSCN including SEPCN so that the output is 0,
Complex type fast Kalman controller with tap interval NT
It can be converged under the control of FKCCN. In other words, in such a configuration, SEPCN can be converged to become an equivalent circuit of EP. It should be noted in particular that in this case the convergence value of SEPCN is
This means that if the position and bandwidth of the FILN passband on the frequency axis are the same, it will be the same regardless of the characteristics of the FILN in the passband. This is because SEPCN spans the entire passband of FILN.
This is because it has to work as an equivalent circuit of EP, and in such a case, there is only one possible state for SEPCN. That is, regardless of whether the FILN's bandpass characteristic on the frequency axis is rectangular or parabolic. The convergence values of SEPCN are the same. It is immediately obvious that FIG. 46 is equivalent to the following FIG. 47. In other words, increase the number of FILN to two,
Move the complex sampler S to a place beyond the junction to _{the two} directions and the echo path EP direction, and then move the FILN to one side.
and swap the positions of EP, then complex sampler S ₂
By switching the positions of and FILN, the configuration shown in FIG. 47 is obtained. The former substitution is due to the interchangeability of the linear system, and the latter substitution, as in this case, is such that the input to the signal input point I is in the frequency band handled by this sampling system -π/T ~ π/T ( radians/second). The main part of the present invention is a synthesis of the knowledge described in detail above, and one form thereof is shown in FIG. That is, FIG. 48 is a diagram of one type of the present invention. This figure shows the handling frequency band of this system determined by a complex sampler S ₁ S ₂ with a sampling interval of T seconds.
FIG. 3 is a diagram of one type of a band division fast Kalman type transfer function estimator that operates by dividing π/T to π/T into N parts. Figure 4
In 8, FILN0j (j is an integer of 1...N) is a bandpass filter with a rectangular frequency amplitude characteristic (no phase characteristic) and a passband width of 2π/NT (radian/second), and these characteristics FILN01,
Represented by FILN0j and FILN0N, Fig. 49a, b,
They are shown in c. TSCN01,...TSCN0N are complex type fast Kalman type transfer function estimators, and are exactly the same as each other, and are also the same as TSCN in Figs. 46 and 47, and in the configuration of Fig. 3.
The tap interval for TDL ₁ C and TDL ₂ C is NT. In Figure 48, the TSCN group is one of them.
In order to represent TSCN01, its constituent elements are shown divided into SEPCN01, FKCCN01, and ADC01. However, SEPCN01 is the complex estimated echo path of the 01st tap interval NT, FKCCN0
1 is a complex fast Kalman controller with tap interval NT at the 01st, and ADC01 is also a complex adder at the 01st. SUM, which is a newly introduced part in FIG. 48, is a summator that takes the sum of N signals. Needless to say, in the figure, SC ₁ and SC ₂ are complex samplers that sample signals every T seconds, and EPC is a complex echo path. Note that the input point on the echo path side of each TSCN0j is called EPO0j, the input point on the signal input side is called IO0j, and the error output point is called O0j. Now, the configuration shown in FIG. 48 is a parallel arrangement of complex fast Kalman type transfer function estimators that work independently.
Since the convergence of each of them is guaranteed, this entire configuration also results in convergence. That is, no error output is generated at the error output point 0j of each TSCN0j, and therefore no output is generated at the output point O of the summator SUM. The operation of the configuration shown in FIG. 48 after convergence will be examined below. The signals exiting the echo path EPC and sampled by the complex sampler SC ₁ are branched to FIL0, respectively.
j, ADC0j, (j=1...N) band filter,
They pass through a complex adder and are added by a summator SUM.
Since the sum of the transfer functions of FILN0j, (j=1...N) is the transfer function of the through circuit, the circuit must be cut off before the signal _S2 generated at the SUM output point O through the path just described. As can be easily seen, this is the output of the complex echo path EPC itself.
When TSCN0j (j=1...N) is in a convergent state, the signal generated at the above point O, FILN0j and SEPCN0
It can be said that the signals generated at point O as the signal sum of the cascaded paths of j (j=1...N) are equal, the two signals cancel each other out, and no signal is generated at point O after all. Therefore FILN0j and SEPCN0
It can be said that the transfer function of the circuit in Fig. 50, in which j cascade-connected circuits are connected in parallel for j, is equal to that of EPC. In Fig. 50, point IN is the input point of this configuration, and point OUT is the output point of this configuration. It is. In this way, the configuration of Fig. 48 becomes the echo path at the time of convergence.
A transfer function as an estimated value of the transfer function of EP is physically given in FIG. 50, and an echo cancellation effect is obtained. The purpose of the transfer function estimator according to the present invention is to reduce the number of calculations. Now, let us compare the number of computations between the configuration of one type of the present invention shown in FIG. 48 and the conventional configuration shown in FIG. 2. For now, we will use a bandpass filter.
Without taking into consideration the number of operations for FILN0j (j=1...N), the complex transfer function estimator is
In the configuration of Figure 2, the total number of calculations for TSCN0j (j = 1...N) is calculated using a fast Kalman-type transfer function estimator.
Find out the number of calculations for TS. First, consider the configuration shown in FIG. Now let the maximum duration of the impulse characteristic of the echo path EP be MT seconds. However, M is a certain positive integer. From this, the number of taps of the tapped delay lines TDL ₁ and TDL ₂ in FIG. 2 is M. The number of multiplications required for one adjustment operation of the fast Kalman transfer function estimator is the number of taps in the case of real numbers.
In the case of a 10 times complex number, real number multiplication of 40 times the number of taps is required. In this case, for the operation of TS,
For 10M operations of all TSCN0j (j=1...N), 40M real number multiplications are required, taking into consideration the reduction in the number of taps and the need for a complex number Kalman controller. By the way, it is known that the degree of convergence per adjustment operation is inversely proportional to the number of taps. That is, the band-split fast Kalman transfer function estimator using the present invention is N times as large as the conventional fast Kalman transfer function estimator (N is the number of band divisions as described above).
It has a convergence speed per adjustment operation of .
In this sense, if N is set to 4 or more, a transfer function estimator can be provided that requires fewer calculation steps per same degree of convergence than the conventional type. This is an advantage of the invention. just
Although consideration must be given to the number of computations required for waveforms such as FILN(ij) and the deterioration of efficiency due to increasing the number of sequences, as will be described shortly, in any case, by selecting a large N, the band-split fast Kalman form of the present invention can be used. We can find areas where a transfer function estimator is more useful. This completes the explanation of one method of configuring the present invention and its effects. Next, another method of configuring the present invention will be described. If this configuration is drawn along the lines of FIG. 48, it will become as shown in FIG. 51. That is, FIG. 51 is another example to which the present invention is applied. This configuration is the same as FILN0 in the configuration shown in Figure 48.
N bandpass filters from 1 to FILN0N are
FILN11...FILN2N increases to 2N bandpass filters, and accordingly, the complex transfer function estimator TSCN
The number of items also increases to 2N. Each FILN
The complex transfer function estimator corresponding to (ij) (i=1, 2, j=1...N) has the same configuration as in FIG.
Numbering is done as TSCN(ij). The structure shown in FIG. 51 is not particularly different from that in FIG. 48, but FILN (i, j) (i = 1, 2, j = 1...N)
The characteristics of FILN(0,j) (j=1...
N) is significantly different from that of Figures 52 and 53.
It has a gentle shape as shown in the figure. The band-pass filters of the FILN (1, j) (j=1...N) series shown in FIG.
...N) are collectively referred to as a series 2 bandpass filter. Each bandpass filter belonging to series 1 and series 2 is a bandpass filter with a bandwidth of 2π/NT (radian/second), so as mentioned above, NT
For this reason, TSCN(i,j) (i=1,2,j
= 1...N) is a complex transfer function estimator with delay element arrays with intervals of NT (seconds), which are equal to each other and
It is structurally equivalent to TSCN0j (j=1...N) in FIG. The first series of bandpass filters and the second series of bandpass filters that share the same frequency band have their amplitude characteristics mutually matched, and when their transfer functions are added, they have flat frequency characteristics in their common passband. It shall have the following characteristics. It is assumed that these phase characteristics do not exist.
Therefore, the sum of the transfer functions of 2N bandpass filters FILN11 to FILN2N results in a through circuit as shown in FIG. 54. Taking these things into consideration, the transfer function of the structure of FIG. 55 becomes equal to that of the echo path EP after the complex transfer function estimators TSCN11 to TSCN2N converge, and the transfer function of the structure of FIG. A transfer function as an estimated value of the transfer function is physically given in FIG. In FIG. 55, point IN indicates the input point of this configuration, point OUT indicates the output point, and SUM indicates the summator. Also, of course, FILN(ij) (i=1,2,j=1...N)
SEPCN(ij) (i=1, 2, j=1...N) are the complex transfer function estimators TSCN(ij) (i=1,
2, j=1...N), and a complex estimated echo path. The convergence state of the configuration in Figure 51 is for each TSCN.
Since the number of TDL ₁ C taps in the configuration is equal to each other, this configuration is similar to that of the configuration shown in FIG. 48, and is N times faster than the conventional type. The feature of the configuration in FIG. 48 is that the bandpass filter FILN(ij) (i=1, 2, j=1
...N) has a gentle frequency amplitude characteristic, the tap length of the transversal filter constituting this can be reduced from the approximately 80N tap required in the configuration of Fig. 48.
It is reduced to 16N taps. Although FIG. 51 shows an example using two series of bandpass filters, 3
Using the above series of bandpass filters, it is also possible to design such that the sum of the transfer functions of the shared portion of the passband of each bandpass filter becomes flat. Previously, in the description of a real number type transversal filter, for example, let the tap interval be T (seconds).
In the case of As mentioned above, there is only one example in which this restriction is not a constraint. That is, in the configuration of FIG. 48, if EP has real-time impulse characteristics and the signal at signal input point I is a real number, the conventional transfer function estimator shown in FIG. 2 is used instead of the complex transfer function estimator. , only N/2 pieces need to be used instead of N pieces. However, in such a case, the tap interval of TDL ₁ TDL ₂ must be selected to be NT/2, which is 1/2 of the complex number form, and the number of taps, which affects the number of calculations, is doubled. When these conditions are met, the restriction that the frequency characteristics are symmetrical about the center of 4πi/NT (radians/second) (i is an integer) is the position shown in Figure 49, that is, 2πi/NT ~ 2π(i+1 )/NT (radians/second) (i=-N/2 to -1), each estimated echo path may have arbitrary characteristics. This also applies to the case shown in FIG.
This does not apply to bands shifted from the positions in FIGS. 49 and 51, such as the frequency range in . That is, the Kalman type transfer function estimator corresponding to an arbitrary position such as the frequency range in FIG. 53 must be of complex number type. In this sense, a complex number transfer function estimator is absolutely necessary in order to apply the bandpass filter FILN(2,j) (j=1...N) having a short tap length to the configuration shown in FIG. Note that the bandpass filter corresponding to the conventional transfer function estimator is a bandpass filter with real coefficients. Since the method using such a conventional type increases the number of taps and cannot construct the entire structure shown in FIG. 51, it will not be discussed further here nor will the details of the structure be shown. In Fig. 52, a is the gain characteristic of FILN11, b
indicates the gain characteristic of FILN1j, and c indicates the gain characteristic of FILN1N. Also, in Fig. 53, a is the gain characteristic of FILN21, b is the gain characteristic of FILN2j, and c is the gain characteristic of FILN2N.
S in FIG. 54 shows the gain characteristics of FILN11~
It shows the sum of all gain characteristics of FILN2N. The main parts of the present invention, centering on the configurations shown in FIGS. 48 and 51, have been described in detail above.
=1...N) will be described below. FILN(i,
The structure of j) (i=0, 1, 2, j=1...N) is as shown in FIG. The structure shown in FIG.
It is a transversal filter with taps (L is an integer), and in the same figure, T is of course a delay element of T seconds, _i,j,l (i=0,1,2,j=1...N,l= 1
...L) is a bandpass filter FILN(i,j) (i=
0, 1, 2, j=1...N). SUM is of course a summator. Also, let the input terminal of FILN (i, j) be a point g, and the output terminal be g _i,j . As mentioned above, the value of L is about 80N for FILN (0, j), FILN
For (i,j) (i=1,2), approximately 16N is required. The values of weights _0,j,l (j=1...N, l=1...L) for a bandpass filter with rectangular frequency characteristics are: given as. However, A is L/2 or an integer closest to it. Also _i,j,l (i=1,2,j=1...
This is an example of the value of N, l = 1...L), and the first series bandpass filter FILN is configured using this coefficient.
(i, j) and that of the second series FILN (2, j) each have cosine squared amplitude characteristics as shown in Figures 52 and 53, and these amplitude characteristics also overlap each other, and their transfer function can be When added, the circuits that have flat frequency characteristics in the common pass band and the sum of the transfer functions of the first series and the second series are equal to the through circuit shown in FIG. 54 are expressed by the following equations (21) and (22), respectively. ) is given by The above is for each bandpass filter FILN(i,j)(i
=0, 1, 2, j=1...N). The details of the band-split fast Kalman-type transfer function estimator have been described above. The present invention is characterized in that the degree of convergence per number of adjustments is greater than that of conventional high-speed Kalman type transfer function estimators, and that the number of calculations required until convergence is small. FIG. 3 shows its entire configuration, and FIGS. 4 to 45 show its details. The configuration of the complex fast Kalman transfer function estimator is ultimately expressed by Equations (1) to (12)
(13)'(14)'(15 to 19) are performed. From point I, the circuit in Figure 3 is of a type in which adjustment is made for each input sample, but when adjustment is made for each of multiple samples (assumed to be m samples, where m is an integer of 1 or more), the circuit The format of is shown in Figure 3.
It will be slightly different from . In this case, the reciprocal number generators 1N ₁ and 1N ₂ do not take the reciprocal of a scalar quantity, but rather obtain an inverse matrix. In that case, q _i g _i v _i w _i r _i, which was a scalar quantity in FIG. 3, becomes an m-element vector. However, equations (1)~(12)(13)′(15)~
The formats of equations (17) and (19) are kept as they are, and equations (14) and (18) can be read as the specification for taking the reciprocal with -1 added to the right side as the specification for taking the inversion of the matrix. After all, it can be used as is. Note 1
The calculation of the inverse matrix in this case in N ₁ 1N ₂ can be easily performed because the method of calculating the inverse matrix is well known. Although the above changes have been made, other points remain the same, so a description thereof will be omitted. The present invention provides a basic configuration of a complex fast Kalman type transfer function estimator, a method of configuring a band division fast Kalman type transfer function estimator obtained by combining this with a band division method,
It consists of the configuration method of the input wave device at this time. According to the present invention including these factors, it is possible to perform transfer function estimation that performs effective and rapid convergence.

[Brief explanation of the drawing]

FIG. 1 is an example of the configuration of a conventional transfer function estimator, FIG. 2 is an example of the configuration of a conventional fast Kalman control transfer function estimator, FIG. 3 is an example of the configuration of a complex fast Kalman transfer function estimator according to the present invention, and FIG. The configuration diagram of the delay element, FIG. 5 is a divided representation diagram of the delay element, and FIG.
TDLC ₁ complex form detailed diagram, Fig. 7 is a divided form expression diagram of TDLC ₁ , Fig. 8 is a complex form detailed diagram of TDLC ₂ , Fig. 9 is a complex multiplier MULC ₁ complex form configuration example, Fig. 10 is
An example of a divided type configuration of MULC ₁ , Figure 11 is an example of a divided type configuration of a complex line concentrator, Figure 12 is an example of a divided type configuration of a complex adder and complex register, and Figures 13 and 14 are examples of a combined type and divided type configuration of a subtracter. , Figures 15 and 16 are configuration examples of complex dimension multipliers DIC ₁ and DIC ₂ , and Figure 18 is an adder.
A configuration example of ADC ₁ , Figure 19 is a configuration example of MULC ₃ , Figure 20 is a detailed diagram of subtractor SUBC ₁ , Figure 21 is a detailed diagram of ARC, Figure 22 is a detailed diagram of MULC ₄ , and Figure 23 is adder ADC _2. 24 is a detailed diagram of the divided configuration of the complex conjugate value generator C, FIG. 25 is a detailed diagram of the multiplier MULC ₅ , FIG. 26 is a detailed diagram of the adder ADC ₃ , and FIG. 27 is a detailed diagram of the S register SRC. , Figure 28 shows the complex inverter
A detailed diagram of INC ₁ , Figure 29 is a detailed diagram of the complex multiplier MULC ₆ , Figure 30 is a detailed diagram of the complex multiplier MULC ₇ , Figure 31 is a detailed diagram of the complex adder ADC ₄ , and Figure 32 is a detailed diagram of the complex multiplier DIC. Detailed view of ₃ , Figure 33 is a complex dimension reducer
A detailed diagram of DDC ₁ , Figure 34 is a detailed diagram of complex multiplier MULC ₈ , Figure 35 is a detailed diagram of complex adder ADC ₅ , Figure 36 is a detailed diagram of complex multiplier MULC ₉ , and Figure 37 is a detailed diagram of complex subtracter SUBC _2. 38 is a configuration example of the inverter IN ₂ , FIG. 39 is a configuration diagram of the complex multiplier MULC ₁₀ ,
FIG. 40 is a configuration diagram of the complex subtracter SUBC ₃ , FIG. 41 is a configuration example of the complex multiplier MULC ₁₁ , FIG. 42 is a configuration example of the D register DRC, and FIG. 43 is a configuration diagram of the complex multiplier MULC _12.
A configuration example, FIG. 44 is a detailed diagram of the complex subtractor SUBC ₃ ,
45 is a detailed diagram of the k register kRC, FIG. 46 is a configuration example of a complex transfer function estimator for a signal with a limited band, FIG. 47 is an equivalent circuit diagram of FIG. 46, and FIG. 48
is another configuration example of the present invention, FIGS. 49a, b, and c are examples of characteristics of a bandpass filter, and FIG.
A diagram in which cascade connections of SEPCNs are connected in parallel for j, FIG. 51 is another configuration example of the present invention, and FIGS. 52a and b
53a, b, and c are characteristic diagrams of bandpass filters, FIG. 54 is a through circuit, FIG. 55 is a configuration example that physically provides an estimated value of the EP transfer function, and FIG. 56 is an L-tap transversal diagram. It is a block diagram of a filter. EP; echo path, S ₁ , S ₂ ; sampler, TDL ₁ ,
TDL ₂ ; Delay line with tap.

Claims (1)

[Scope of Claims] 1. An estimated transfer function of the received signal from the received transmission path and the complex echo path is determined from the echo component of the received signal on the transmission transmission path that is generated when the received signal received from the reception transmission path passes through the complex echo path. In a band division fast Kalman type complex transfer function estimator in an echo canceller that sends an error component obtained by subtracting a pseudo echo component created from a first complex delay element DLC ₂ that generates a time delay;
a first complex tapped delay line TDLC ₁ that divides the received signal from the reception transmission line via the complex delay element into a plurality of bands; a complex register HRC that stores tap weight; and a complex register HRC that stores the tap weight; A complex adder ADC for updating, a complex multiplier MULC 1 for multiplying the output of the first tapped delay element by the tap weight, and a complex concentrator GC ₁ for summing the outputs of the complex multipliers for _each band. a complex estimated echo path SEPC consisting of; a second complex delay element DLC ₁ inserted on the complex echo path side to cancel the effect of the first complex delay element; a complex subtracter SUBC that takes the difference between the output from the estimated complex echo path and the output from the complex estimated echo path;
a complex multiplier MULC ₁₃ that multiplies M scalar values corresponding to each tap of the delay line with complex taps and supplies the multiplication result to the complex adder; a third complex delay element DLC ₃ that generates a delay of a predetermined time; and M-1
a second delay line TDLC ₂ with complex taps, which has a number of taps and divides the received signal from the reception transmission path via the third complex delay element into a plurality of bands;
a fourth complex delay element that generates an M-dimensional delay with respect to the output from the second complex tapped delay line;
DLC ₄ , a first dimension increaser DIC ₁ that increases the output of the second complex tapped delay line by one dimension, and an output of the complex tapped delay line from the output of the second complex tapped delay line. With the dimension intensifier DIC ₂ , which obtains
Based on the output from the third complex delay element, the output from the first dimension multiplier, and the output from the second dimension multiplier, a first register registers a first register in a time slot in which storage occurs. a first complex update operation unit PTAC that updates the M-element vector value of PTAC; and a scalar of the output from the third complex delay element and the output of the third complex delay element in the first complex update operation unit. Based on the amount and the M-element vector before updating,
a second complex update operation unit that includes a complex number generator that updates a second M-element vector value in a time slot in which a second register stores and generates the value, and that represents the updated second M-element vector value as a complex number;
PTSC, the output of the complex number generator, the output of the fourth complex delay element, the first and second M-element vector values of the first and second registers, and the fourth M-element of the fourth register. A third register updates a third M-element vector value in a storage-generating time slot based on the vector value, the output of the first dimension multiplier, and the output of a unit number generator that generates the number 1. a third complex update calculation unit PTDC;
a fourth complex update operation unit that updates a fourth M-element vector value in a time slot in which the fourth register stores and generates the vector value based on the vector value of each output before and after the update of the register and the corresponding scalar value;
PTKC, and a complex fast Kalman controller FKCC that operates as a complex time function to obtain a complex transfer function estimate, and further includes a complex fast Kalman controller FKCC that operates as a complex time function to obtain a complex transfer function estimate, and further includes An estimated transfer function of the complex estimated echo path is obtained, the pseudo echo component is created from the estimated transfer function of the complex estimated echo path and the output from the first complex tapped delay line, and and means for subtracting the pseudo echo component from the complex estimated echo path from the echo component from the complex echo path via the complex delay element by the complex subtracter and outputting the result as the new error component. A plurality of estimators are provided corresponding to the number of divided bands, and the sum of the outputs of each of the complex transfer function estimators is sent to the transmission transmission path, and the sum of the outputs of the complex transfer function estimators is sent to the transmission transmission path, and the matrix and vector in the calculation processing in the complex fast Kalman controller are A band-split fast Kalman type complex characterized in that, except for the multiplication process, the complex fast Kalman controller performs arithmetic processing of vector-vector inner product, scalar-scalar inner product, and vector-scalar multiplication. Transfer function estimator.