JPS63224674A - Controller for power converter - Google Patents

Abstract

PURPOSE:To reduce the generation of the distortion of input/output waveforms by varying the period of the generation of pulse patterns controlling a semiconductor element for a power converter. CONSTITUTION:A converter 3 and an inverter 5 as power converters are controlled by one-chip microcomputers 10, 11 as controllers. The microcomputer 10 (11) is constituted of a ROM 103, a RAM 104, an ALU 105, an event setting register 107, a time setting register 108, a holding register 109, an associative memory 110, a timer 111, a comparison section 112, an execution controller 113, etc. A pulse pattern generator controlling transistors for the converters 3, 5 is formed by the microcomputer 10 (11), and the period of the generation of pulse patterns is varied under predetermined conditions. Accordingly, the input/output waveforms of the converters 3, 5 can be changed into sine waves, and the generation of distortion can be reduced, ensuring minimum pulse width to the transistors.

Description

[Detailed description of the invention] [Industrial use bone. Field] The present invention relates to a control device for a power converter, and more particularly to a control device for a power converter that can improve the output waveform while satisfying the minimum pulse width restriction of a main circuit semiconductor element.

[Conventional technology]

As a conventional technology related to power converters, for example,
A current source inverter system described in Proceedings of the National Conference of the Institute of Electrical Engineers of Japan, No. 502 is known. This current source inverter system has 6 GTOs with reverse blocking function.
This is a three-phase current source inverter system that combines a semiconductor element with a series circuit of a diode and a GTO or transistor, a DC reactor, and a capacitor, and is a simple and quiet system. However, since this inverter system is originally designed to generate a sine wave output voltage, it is possible to operate with extremely little noise even when a general-purpose electric motor or the like is connected as a load.
The output current is originally a square wave output, which has the problem of generating torque ripple in the induction motor, which is the load. As a conventional technique for converting this output current into a sine wave, the technique described in Japanese Patent Application Laid-Open No. 60-98876 is known. This conventional technology generates a pulse pattern so that the output current becomes a sine wave, and uses this pulse pattern to control the switching of the semiconductor elements that make up the inverter, and is highly effective in making the output current a sine wave. It has the following.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A power converter according to this kind of conventional technology will be explained below with reference to the drawings.

FIG. 15 is a circuit diagram showing an example of a power converter according to the prior art, and FIGS. 16(A) to (D) are diagrams explaining equivalent output currents of the inverter shown in FIG. 15. In FIG. 15, 1 is a three-phase AC power supply, 2.6 is an overvoltage suppression capacitor, 3 is a current source converter, 4 is a DC reactor, 5 is a current source inverter, and 7 is an induction motor as an example of a load.

In the power converter shown in FIG.
is composed of semiconductor elements such as six GTOs, which are switching elements, converts the AC power of the three-phase AC power supply 1 into DC, and supplies the DC power to the current source inverter via the DC reactor 4. The current source inverter 5 is composed of six switching devices such as semiconductor elements such as GTO, and converts the DC power supplied from the current source inverter 3 into an arbitrary voltage.
It converts into three-phase AC power of any frequency and supplies it to the induction motor, which is the load. The equivalent output current I of the current source inverter 5 in the power converter described above is shown in FIG.
As shown in A), it needs to be a sine wave, and in order to realize this, the current source inverter 5 controls a semiconductor element such as a GTO using a pulse pattern based on a PWM modulated pulse train, and the pulse current i is controlled by the current source inverter 5. The average current is controlled so that it becomes an equal value output current I having a sinusoidal waveform. FIG. 16(B) shows an enlarged view of this equivalent output current near the electrical angle zero degree, and PWMIII? to obtain such an equal output current. 11, the pulse current 10 is the first
This is shown in Figure 6 (C). As can be understood from FIG. 16(C), when the value of the equivalent output current ■ is close to zero, the pulse current 10 must be a very narrow pulse current, especially when the output frequency of the inverter is For very low frequencies, continuous narrow pulse currents are required.

In such a conventional technique, as long as a pulse current with a very narrow width can be obtained near zero of the equivalent output current I, the equivalent output current can be made into a sine wave. For this purpose, it is necessary to control a semiconductor element such as a GTO whose switching is controlled so that it is turned on only for a very narrow period of time.

However, in general, semiconductor devices such as GTOs and transistors used in converters, inverters, etc. have a minimum pulse width limit that does not allow the pulse width to be made any narrower, depending on the rating of the device. "Drive Electronics" Denkishoin p. 279). This minimum pulse width is generally about 30 μsec to 100 μsec to avoid element destruction. Therefore, in the above-mentioned conventional technology, when the inverter 5 outputs AC power with a very low frequency, the pulse current 10 cannot be made equal to or less than the above-mentioned pulse width, and as shown in FIG. 16(D), , the pulse current iI must have a pulse width of 30 μsec to 100 μsec or more. Therefore, the equivalent output current I of the inverter 5 cannot be reduced below a certain level, and a sine wave cannot be achieved. This phenomenon occurs near the zero cross of the equal value output current ■ for all three-phase outputs of the inverter 5, and it also affects other phases, so the induction motor 7, which is the load, Torque shock will occur in the vicinity.

In the above, we have explained the influence of the output of the minimum control pulse width of the semiconductor elements constituting the inverter, but a similar problem also exists with the converter, and in this case, the input terminal waveform of the converter is It deviates from the sine wave every time, causing harmonic current to be generated in the power supply.

[Problem that the invention seeks to solve]

As mentioned above, the conventional technology does not take into account the influence of the minimum control pulse width limit of the semiconductor elements that make up the power converter, resulting in the problem of distorting the input and output waveforms of the power converter. There was a point.

An object of the present invention is to provide a control device for a power converter that can accurately convert input and output waveforms of the power converter into sine waves.

[Means for solving problems]

According to the present invention, the above object is achieved by making variable the generation cycle of a pulse pattern that controls a semiconductor element constituting a power converter.

C Effect] The pulse pattern generating device that controls the semiconductor elements constituting the power converter is controlled so that the generation period of the pulse pattern changes according to predetermined conditions. This makes it possible to convert the input and output waveforms of the power converter into sinusoidal waves, thereby significantly reducing the occurrence of distortion in the input and output waveforms while ensuring the minimum pulse width for the semiconductor element.

〔Example〕

EMBODIMENT OF THE INVENTION Hereinafter, one embodiment of the control device for a power converter according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 1, 31 to 36 are current source converter 3
51 to 56 are six transistors that are switching elements that constitute the current source inverter 5, 8 is a DC current detector, 9 is the primary current command 17 and the output of the converter 3 Comparators 10 and 11 are one-chip microcomputers for controlling the inverter and converter that supply pulse patterns to 12 transistors (these one-chip microcomputers 10 and 11 are the same (The detailed explanation will mainly be given regarding the one-chip microcomputer 10.)

12 is an input terminal for the primary current command 17 given to the one-chip microcomputer 11 for converter control, and 13.14 is a frequency command w given to the one-chip microcomputer 10 for inverter control.
i and the input terminal for the phase command θ1, 15 is the input line for the power synchronization signal given to the one-chip microcomputer for converter control, and the other symbols are the same as in the case of FIG. 15.

In the embodiment of the present invention shown in FIG. 1, a converter 3 and an inverter 5 that are power converters are controlled by a one-chip microcomputer 10.11 that is a control device. Internal bus 102
, R that stores programs, pulse width data tables, etc.
OM103, RA used as temporary memory and register
M104, ALU 105 that executes calculations, etc., output port 106, event setting register 107 that sets an event to output a predetermined pulse pattern (event) to the output port 106, and time setting for when to enable this event. a time setting register 108, a holding register 109 that connects and holds the contents of both setting registers 107□ 108, an associative memory 110 in which several sets of setting data set in this holding register 109 are sequentially and cyclically stored; A timer 111 that outputs the actual time, a comparison section 112 that compares the time determined by this timer 111 with the set time contents in the associative memory 110 and generates an output when these times match, and a trigger from the comparison section 112. The receiver is composed of an execution controller 113 and the like that outputs and controls set events to the output controller 106.

Next, the operation of this embodiment will be explained using a flowchart. However, here, a case where inverter control is performed will be explained as an example.

FIGS. 2 and 3 show a large two-dimensional system for carrying out the present invention.
2 shows a flowchart for performing two processes.

FIG. 2 shows the events that occur in the output capo 106, that is,
Event calculation processing program F10 for determining pulse pattern
It is a schematic flowchart of 0O.

First, in the processing FI100, frequency command Wz1 phase command θ8
is read from the input boat 101. This frequency command Wf,
The phase command θ'' is obtained from information from an encoder provided in the induction motor 7, which is a load, and from a speed command generator (not shown).
When calculating within 0, there is no need for the processing FI 100 to read the input port 101. Next, this frequency command w
i is integrated for a certain period of time and every interrupt interval Δt, which will be described later, and added to the phase command θ9 to obtain the total phase θa in process F1200. Next, among the six modes in which the electrical angle 360' is divided into 60° increments, which mode should be used to output the pulse pattern in the total phase θte obtained this time? In other words, the output is determined according to the total phase θ. Process the event F
Find it at 1300. Note that the relationship between the overall phase θ and the six modes will be detailed later. Finally, interrupt interval Δ1. During this period, the pulse pattern is changed, and processing F1400 performs a process of determining the time until the change by referring to a data table according to the value of the overall phase θ7. By this process, register 10
This means that the two items to be set in 7 and 108 are the event content and event change time.

FIG. 3 shows an event setting processing program F2000 that sets the two items obtained by the above-mentioned event calculation processing program F1000 in the associative memory 110 for output boat control.
This is a schematic flowchart, and next, this event setting process will be explained.

The event calculation processing program F100O has determined which transistors should be turned on and off during the current interrupt interval Δt1 and their times, but if that data is scheduled as is in the associative memory 110, it will not be possible for the main circuit transistors of the inverter 5 to The on-pulse width and off-pulse width may not satisfy the element rating. Therefore,
In this event setting processing program F2000, pulse width data is first examined in processing F2100. When the pulse width data is larger than the limit value Lim1t, normal schedule processing F2200 is executed to set information on transistors to be turned on and off and their times obtained in event calculation processing F100O in associative memory 110. In addition, in process F2100, the pulse width data is set to the limit value LiI.
If it is smaller than IIit, in process F2300, the pulse width data is recalculated, the interrupt interval Δt is reviewed, and the data after the review is used to schedule the associative memo I7110, and the current interrupt interval Δt2 is Finish processing the section.

Figure 4 shows the two processing programs F100O and F mentioned above.
2000 is a diagram illustrating how time passes when 2000 is activated, and this will be described below.

The event setting processing program F2000 is activated in synchronization with the first timer interrupt T2O00 that occurs every interrupt interval Δt. On the other hand, the event calculation processing program F10
0O is activated by the second timer interrupt T1000 that occurs prior to the first timer interrupt T2O00, and completes the event calculation process before the event setting process program F2000 is activated. The reason why the processing of the event calculation processing program F100O is completed immediately before starting the event setting processing program F2000 is to enable the latest data to be used by the event setting processing program F2000.

When the above-mentioned processing program F2000 finishes setting the predetermined event and setting the time, the associative memory 110 and execution controller 113 in the one-chip microcomputer 10 take over output control, and the main processor section including the ALU 105 controls the output. The user is freed from processing and can perform other processing.

Next, the determination of the pulse pattern in the process F1300 of the event calculation process program F1000 described above will be explained.

FIG. 5 is a flowchart showing details of process F1300, and FIG. 6 is a diagram explaining the firing states of transistors 51-56 in modes M1-M6 in FIG. In the case of inverter control, it is sufficient to change the pulse pattern every 60 electrical degrees and repeat six sets of modes that go around 360 degrees. Therefore, in process F1300, process F12
Processing F that divides the overall phase θ, obtained at 00, into 60 degree increments
1310 to F L350 are performed, modes M1 to M6 are selected according to the magnitude of θ7, and the firing states of transistors 51 to 56 are set according to the selected mode.

FIG. 6 shows that in each of modes M1 to M6,
Interrupt interval Δ1. A transistor that is always turned on until the first event (described later) occurs and then turned off; a transistor that is turned off until the second event (described later) occurs and then turned on. A specific example of a combination of transistors and transistors that fire after the occurrence of a second event is shown. Therefore, if the overall phase θa is known, the mode can be determined and the transistor to be turned off and turned on can be specified. In addition, if the total phase θ7 is in a range other than 0 degrees to 360 degrees, add or subtract 360 degrees to change the total phase θa from 0 degrees to
It is necessary to pull back into the 360-degree area, and an area check for this purpose is performed at the beginning of process F1300.

When the above-described process F1300 is completed, the transistors to be turned off can be identified, but it has not yet been determined when to turn off those transistors. Therefore, it is necessary to determine the time during which the transistor is turned off, that is, the time at which the first event occurs and the time at which the second event occurs, and the process for determining this time is the process F1400 of the event calculation process program F1000. The timing of turning off and turning off the transistor in this process F1400 can be determined in such a way that a waveform close to a sine waveform is obtained as the output current of the inverter 5. 5in (θt 120°), 5i
n(θ.

-240°) to the ratio of the peak value to the interrupt interval Δt.

This can be done by bone grafting. In other words, the first
The time j Ell and TEzn until the occurrence of the second event (changing the pulse pattern) are calculated using the following formula (1) as a function of the total phase θ7, and are tabulated. By doing so, the total phase θi is calculated. Can be searched.

LEI, 1=Δt,・5in(θT, 240
°) L E2r+= El! In+Δj +Sinθ Ding Figure 7 Ding Mi7 (This is an example of a table showing the time until the first and second event occurrences, calculated according to equation 11. In the figure, the overall phase θ is 60 degrees in each mode. Shown as values normalized to range.This table is
This is shown as an example of controlling the inverter 5, and since the inverter 5 only needs to operate as a simple switch, it can be controlled using the data in the table as is. When controlling a voltage source inverter, it is necessary to search the table and then process the data in consideration of two amplitudes and the like.

As described above, the transistor 51 constituting the inverter 5
Now that we have decided how to control each of 56 and 56, when setting an event, we set "1" for ignition and "O" for extinguishment in the registers in the one-chip microcomputer 10. By setting each transistor 51 to 5
6 vanishing arcs will be controlled.

FIG. 8 shows examples of the aforementioned operation modes M1-M6 and boat output signals 351-S56 from the output boat 106 applied to the transistors 51-56.

This boat output signal S51 to S56 causes the inverter 5 to
The switching of the transistors 51 to 56 is controlled, and the inverter 5 supplies three-phase AC power to the induction motor.

The process for obtaining such boat output signals 351 to S56 is the process F2200 of the stage setting process program F2000 already explained with reference to FIG. 3, and the details of this process F2200 will be explained.

FIG. 9 is a flowchart showing the event setting process in one timer interrupt interval from time t0 to t0+Δh in FIG. , the process proceeds by performing many steps in series.

In the flowchart shown in FIG. 9, when an interrupt occurs at time t0, in process F2410, the transistor 55, which is always turned on in this mode M1, and the transistor 53, which is turned on until the first event occurs, are immediately turned on. Two sets of event sets and time sets are performed for each transistor so that an arc signal is generated. That is, the port P corresponding to transistors 55 and 53 of output port 106
5. Set the event to generate “1” in P3,
Next, as a time set, a predetermined time td is added to the current time t0 and set in a predetermined register. transistor 55.5
3, the ignition occurs immediately, so a sufficiently small value is selected for the predetermined time.

As a result, the event and time are set in the associative memory 110, and after a predetermined time t4 has elapsed, a "1" position signal is output to the transistors 55 and 53.

In process F2420, assuming that the operating mode has changed from the previous time due to a sudden change in the phase command θ1, etc., a process is performed to confirm the extinction of the transistor that should be in the extinction state in this mode M1. This process F2420 uses the associative memory 110 like the process F2410, but here, since the event is extinction, the transistors 51, 52, 54 .
56 corresponding to ports PL, P2. P4. 0″′ to P6
An event is set so that 10+1° occurs, and a time is set at 10+1°.

Next, in process F2430, time t0+tEI.

Schedule processing is performed so that the transistor 53 is turned off. The event is an event set that causes "O" to be generated at the port P3 corresponding to the transistor 53 of the output port 106, and the time set is tO+tElr+. At this point, the baud for transistor 53 F3 has multiple events within the same interrupt interval, including firing after a predetermined time td and extinguishing after a time jEln until the first event occurs. This means that it has been scheduled separately.

Further, in process F2440, setting of ignition of the transistor 51 is performed in place of extinguishing of the transistor 53 in process F24.
30 is performed in the same manner. Note that here, transistor 5
3 and the transistor 51 are turned on at the same time. However, in order to prevent overvoltage to the load, the current source inverter wraps the "1" period, and the voltage source inverter creates a non-lap period, so tEI,... Processing time F243
It is also possible to change between 0 and F2440.

Next, process F2450. At F2460, at the second event occurrence time point tO''jEZn, in order to perform a schedule for turning off the transistor 51 and a schedule for turning on the transistor 52, event setting and time setting are performed in the same manner as in other processes. In this way, the one-chip microcomputer 10 calculates the total phase θA, determines which transistors should be turned on and off based on the total phase θA, and determines the time period for which the transistors should be turned on and off. The inverter 5 is controlled by performing a process of scheduling the transistor to be used and its time at every interrupt interval Δt1.

10 and 11 are detailed flowcharts of the event setting processing program F2000 explained in FIG.
This will be explained below.

As shown in FIG. 10, the event setting processing program F2000 first performs processing F1310-F135 to determine in which range of 60 degrees the overall phase θ7 determined by the event calculation processing program F100O falls.
0 in the same manner as in the pulse pattern determination process explained in FIG. 5, and the total phase θ determined by this process is
, event setting processing for each 60 degree range E2000 to E25
Execute 00. Here, as in FIG. 9, θa is 0.
For example, if θ7 is in the range of 60°,
The event setting process E2000 will be explained with reference to FIG.

First, in process E2001, it is determined whether θ7 is in the first half or the second half of the 60 degree interval. Total phase θa is 0
(If θT<30', the transistor with the narrow control pulse width is 51, so the determination process E2
At 002, (j EZn-tEl, . . . ), that is, the period during which the transistor 51 is on is compared with the limit value L 1m1t. (LEtn LEIn)) If Limit, interrupt interval Δt, time data tEll
'll j E2
2007 will be executed. Judgment process E2002
If it is determined that (tczn −LEtn )<Lim1t, in process E2003, Lim1t and (LEtn
Find the ratio A of tEl7).

Thereafter, in processes E2004 to E2006, tE is performed.

tE2n+ Δt, respectively, are calculated by multiplying them by A, and each value is calculated as A−jEln l A' jEZn l A・Δt
, and set the value of (ttza tt+++) to Li
After securing the time equal to the m1tO value, the schedule process of process E2007 is executed.

If the overall phase θa is θT>/30' in the determination process E2001, the transistor 53 is turned on! 1? Wholesale pulse width is narrow. Therefore, in the determination process E2012, the time tEI++ during which the transistor 53 is on is
and the L imi L value. Judgment process E2012
in.

If it is determined that tEIr+:)Limit, the normal schedule processing E 2007 is executed and ttan
If it is determined that < L 1m1t, process E201
3, calculate the ratio between Limlt and j Eln, execute the above-mentioned processes E2004 to E2006, and obtain tEln. Secure only the L1m1tO value as the value and process E2007.
Executes scheduled processing.

In the event setting process E2000 described above, process E20
01→E2002→E2007 route 1 and processing E2
Route 2 of 001-E2012-E2007 has the interrupt interval Δt and the time data LEIn + jE
This is normal schedule processing that does not reconsider 2+, and processing E2001- E2002-E2003 → E2
004 → E2005 → E 2006 → E2007 route 3 and processing E2001- E2012-E2013 →
Route 4 of E2004→E2005→E2006→E2007 is a schedule process in which ΔLl+LEtn l tEZn is reconsidered and the on time of each transistor is secured by the Lim1t value.

In FIGS. 12(a) to 12(C), the overall phase θ7 is O.

Figures 13 (a) to 13 (
C) is in the region where the overall phase θ is 306〈θ□〈60°,
Boat output signal 551 given to transistors 51 to 53
An example of the pulse pattern of ~S53 is shown.

In both figures, (in the ideal case where al does not take into account the minimum pulse width of the transistor), (the peak) is simply ensuring the limit value Lim1t for the pulse pattern in (a), and (C) is the case in which the present invention is implemented. As an example, a case is shown in which the interrupt interval Δtl+ and the event occurrence time jEIn+LEtn are reconsidered to ensure the limit value L 1m1t.

As is clear from both figures, in case (2) where the L1m1t value is simply ensured, there is a difference in the ratio of the pulse widths of each boat output signal 851 to S53 compared to the case (al) in the ideal state. However, in case (C) according to the embodiment of the present invention, although the interrupt interval Δt1 is longer, it shows an ideal state (the pulse width ratio is the same as in the case of al).

FIG. 14 shows a transistor 51 whose overall phase θT is from 00.
The pulse patterns of the boat output signals 351 to S56 for the signals 351 to 56 are shown. Interrupt interval Δ1. is Oo
The width of the pulse increases in the vicinity, and the pulse width applied to the transistor 51 is controlled to be kept at a limit value. Thereby, the output current of the inverter 5 is made into a sine wave. In this FIG. 14, the overall phase θ7 on the left side is O.

The area close to is the event setting process E200 explained in FIG.
This means that route 3 of 0 has been executed, and route 1 has been executed for the area on the right.

In addition, in the description of the above-mentioned embodiment, the total phase θ7 is O°~
Although the 60° section is taken as an example, if the total phase θ7 is in another section, it is necessary to change the transistors to be turned on or off as explained in FIG. 6 according to the value of the total phase θa. Needless to say, there is. Therefore, in response to this, the event setting process E2000 explained using FIG.
It is necessary to prepare five other types of processing similar to the above, that is, processing E2100 to E2500 shown in FIG.

According to the above-described embodiment of the present invention, the output of the inverter can be made into a sine wave down to an extremely low frequency range without being subject to the minimum pulse width restrictions of the semiconductor elements constituting the inverter. As a result, for example, if the present invention is applied to a current source inverter, the torque ripple of an induction motor that is a load can be directly reduced, and when applied to a voltage source inverter, the torque ripple of an induction motor that is a load can be directly reduced. can be reduced.

Furthermore, it is also possible to apply the present invention to a converter, and in this case, the waveform on the AC side, that is, the power supply side, will be almost completely converted into a sine wave, so it will be possible to apply the present invention to external devices such as phase advance capacitors. A clean converter that does not flow harmonic current can be realized.

In the example described above, the pulse width data value t! ,.

An example in which a sine function is introduced to calculate 1E□7 has been explained.

In this case, it is possible to convert the output into a sine wave by simply performing proportional calculation processing.

On the other hand, by comparing the triangular carrier wave and the linear modulated wave, pulse width data (It□,

Tzz. It is also possible to obtain By such a method, if the pulse pattern generation period and the pulse width are reconsidered by weighting as in the embodiment of the present invention, it is possible to realize a sinusoidal output of the inverter also by such a method. be able to.

In the above-mentioned embodiment, a one-chip microcomputer was used to generate the pulse pattern for controlling the inverter, but by adopting such a configuration, it is possible to simplify the circuit and improve reliability. It becomes possible.

Furthermore, in the above-mentioned embodiment, an example was shown in which the output of the inverter is controlled to have a sine waveform, but if necessary, it is also possible to output a triangular wave represented by a linear function, for example.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to virtually eliminate the influence of the minimum pulse width limitation of semiconductor elements constituting a power converter, and to make the input/output characteristics of the power converter almost ideal. can do.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIGS. 2 and 3 are flowcharts of an event calculation processing program and an event setting processing program that explain the operation of FIG. 1, and FIG. 2 and 3. Figure 5 is a flowchart showing the details of the pulse pattern determination process in Figure 2. Figure 6 shows the transistors in each mode in Figure 5. 7 is a diagram explaining the table for determining the time to turn off the transistor, FIG. 8 is a diagram showing an example of the pulse pattern given to the transistor, and FIG. Flowchart showing details of process F2200 in the figure, first
Figures 0 and 11 are flowcharts showing details of the entire processing program in Figure 3, and Figures 12 (a), (b), (
C1, FIGS. 13(a), (b), and (C) are diagrams showing examples of pulse patterns of port output signals 351 to S53, and FIG. 14 is a diagram showing examples of pulse patterns of boat output signals 351 to S56. FIG. 15 is a block diagram showing an example of the prior art, and FIG. 16(A). (B), (C), and (D) are diagrams explaining the equivalent output current. 1---Three-phase AC power supply, 2.6--Overvoltage suppression capacitor, 3-1--Current source converter, 4--DC reactor, 5--11 111 current type inverter, 7-...-induction motor, 3
1-36.51-56---1--transistor, 8
-・-DC current detector, 9-・-・-Comparator, 10,1
1...--One-chip microcomputer, 101-----
Each person's capo, 102--Internal bus, 10
3------ROM, 104--RAM, 1
05--ALU, 106--Output port, 10
7・−・−・−Event setting register, 108・−−11−
1-time setting register, 109--Holding register, 110--Associative memory, 111--Timer, 112--Comparing unit, 113--Execution controller. 2nd cause Figure 3 Figure 6 Figure 9 Figure 11 Figure 12 Figure 13 (a) Figure 15

Claims (1)

[Claims] 1. A power converter comprising a plurality of switching elements constituting a main circuit of the power converter, and a control device that generates a switching pulse pattern for turning on and off these switching elements, wherein the control device A control device for a power converter, characterized in that a pulse pattern generated by the device is a predetermined function, and the pulse width and pulse pattern generation period are changed under predetermined conditions. 2. The power converter control device according to claim 1, wherein the predetermined function is a sine wave function. 3. The power converter control device according to claim 1, wherein the predetermined function is a linear function. 4. The power converter control device according to claim 1, wherein the predetermined condition is a condition in which the pulse width reaches a predetermined limit value. 5. The power converter control device according to claim 4, wherein the predetermined limit value is a minimum pulse width at which the switching element operates normally. 6. The power converter control device according to claim 1, wherein the power converter is an inverse converter. 7. The power converter control device according to claim 1, wherein the power converter is a forward converter. 8. The power converter control device according to claim 1, wherein the control device is constituted by a microcomputer.