JPS6322106B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a technology for compensating for cross-polarization interference caused by the shared use of orthogonal polarizations in wireless transmission, and particularly to a cross-polarization compensation circuit.

Radio communications in the microwave band are rapidly developing, centering on terrestrial communications and satellite communications. The demand for wireless communications is expected to further increase in the future due to the expansion of mobile communication services, and along with the development of sub-millimeter wave and higher frequency bands, the idea of so-called frequency reuse of currently used frequency bands with high practical value is being developed. It's increasing. CCIR (Consultative Committee on International Radiocommunications)
The Recommendation for FM Radio Frequency Deployment ~6GHz specifies the use of orthogonal polarization. Also,
In satellite communications as well, INTELSAT (International Telecommunication Satellite Organization) is expected to commercialize technology for sharing orthogonal polarization in the 4 to 6 GHz band, which has been used with single polarization on V-series satellites.

In order to achieve this shared use of orthogonal polarization, it is important to improve the polarization characteristics of antennas and power supply equipment, as well as develop cross-polarization compensation circuits that compensate for deterioration of polarization characteristics during radio wave propagation due to rain, etc. This has become an issue.

Originally, free space is independent for two orthogonal polarized waves, and it is a transmission line that can transmit both polarized waves simultaneously, but in actual propagation paths, there is anisotropy in the medium such as rain, and it is necessary to use orthogonal polarized waves. If this method is adopted, the coupling between polarized waves due to the generation of cross-polarized waves will cause interference between different polarization channels.

Cross polarization compensation technology automatically compensates for such coupling between polarized waves by providing a compensation circuit within an antenna feeder or wireless device.

Conventionally, microwave band communication has centered on analog transmission centered on FM, so the cross-polarization compensation method described above also restores orthogonality by installing a variable phase shifter and attenuator around the antenna feeder. A number of methods have been well researched and put into practical use, such as methods that eliminate interference between different polarized waves by providing an interference wave compensation circuit in the intermediate frequency band.

In recent years, digital transmission has come into use even in the microwave band, and there is a demand for proposals for more efficient cross-polarization compensation methods that take advantage of the characteristics of digital transmission.

An object of the present invention is to provide a cross-polarization compensation circuit that performs a cross-polarization compensation method in a baseband band based on demodulated baseband signal information in digital transmission.

According to the present invention, digital transmission for shared orthogonal polarization can be performed through a currently used antenna system for single polarization and intermediate frequency equipment.

Currently, the beam width of satellite antennas is considerably wider than that of terrestrial microcircuits, and global beam antennas use asymmetric beams to increase effective transmission power. Due to Yong et al., high orthogonal polarization discrimination cannot be expected.

In such a transmission system, the present invention is significantly superior to the conventional system, and is more economical in that it does not require any modification to the existing transmission system. Even when signals from multiple stations are received in a time-division manner using the same antenna, as in TDMA, cross-polarization compensation can be performed for each transmitting station individually.

The present invention provides a method for wirelessly transmitting first data and second data, which are independent digital signals, using first and second polarized waves that are orthogonal to each other.
a prediscrimination circuit that estimates and identifies second data; a memory circuit that selects and provides a readable/writable memory element corresponding to each discrimination value of the prediscrimination circuit; a subtracter that subtracts the contents of the storage element being sorted and provided from first data; a final identification circuit that estimates and identifies the first data from the output of the subtracter; and outputs an input-output difference of the final identification circuit. an error detector that outputs a correction value obtained by correcting the output of the currently selected storage element according to the output of the error detector; At the same time as writing to the memory element, the identification value of the output of the pre-identification circuit is written on the signal point arrangement plane with the origin as the center.
2π/M·N (N is an integer from 0 to (M-1)) The above-mentioned memory elements are respectively stored in (M-1) memory elements corresponding to other (M-1) identification values obtained by rotation in radians. and a storage circuit control circuit that reads a value obtained by multiplying the correction value by exp{j2π/M・N}, and from the output of the final identification circuit, it is determined that the first A cross-polarization compensation circuit is characterized in that it obtains first data from which interference of second data with respect to data of the first data is removed.

Next, the present invention will be explained in detail with reference to the drawings. First, the prior art will be explained with reference to FIGS. 1a and 1b to 7.

Reference numbers 4000,400 in Figures 1a and b
1,4002 and 4003 and 4100,410
1, 4102 and 4103 respectively indicate four signal points of a quadrature phase modulation signal on an orthogonal (IQ) phase plane.

Figure 1a shows the first data desired to be received in the first polarization, and Figure 1b shows the second data, which is another digital signal transmitted in the orthogonal second polarization. . If cross-polarized interference occurs in the transmission path, the signal obtained by synchronously detecting the first polarized wave will be the four signal points shown in Figure 1a and the lower-level interference component shown in Figure 1B. The result is a signal in which four signal points are superimposed.

Figure 2 a and b are diagrams showing this superimposed signal. Figure 2 a shows a signal in which the interference component is superimposed with the first data in the same phase, and Figure 2 b shows a signal in which the interference component is superimposed with a phase difference of 45 degrees. It shows.

It can be seen from FIGS. 2a and 2b that the interference component contained in the first data is a constant value specific to the identification value of the second data. Therefore, if the identification value of the second data is obtained, a constant value unique to this value is used as an interference component, and the same interference can be eliminated by subtracting it from the detected signal of the first polarization that has received cross-polarization interference. It turns out that it can be removed. The above is the operating principle of the cross-polarized interference component.

FIG. 3 is a block diagram showing an example of a cross-polarized interference compensation circuit, in which detected signals of first and second polarized waves are applied to terminals 100 and 101, respectively. Therefore, second data as shown in FIG. 2 is superimposed on the terminal 100 as an interference component.

The detected signal of the second polarization input from the terminal 101 is converted into an estimated identification value of the second data by the next pre-identification circuit 1. At this time, if the signal distortion of the second data is below a certain level and the noise is not abnormally large, the probability of an estimated identification error is sufficiently small. The obtained estimated identification value controls the signal line selector 34 in the next storage circuit 3, selects one unique to the estimated identification value from among the storage elements 30, 31, 32, and 33, and selects the one unique to the estimated identification value. Connect to output terminal 104.

On the other hand, the first polarized detection signal is added to the subtracted terminal of the subtracter 20, and the value of the memory circuit output terminal 104 connected to the subtraction terminal of the subtracter 20 is subtracted as an interference component. The output of the subtracter 20 is pure first data from which interference components have been removed. This output is then applied to the final identification circuit to obtain the correct estimated identification value of the first data desired to be received. Similarly, cross-polarization compensation circuits of the same type for the second data can be operated simultaneously.

FIG. 4 is a block diagram showing another example of the cross-polarization compensation circuit. When non-regenerative relay is performed in a wireless transmission system, cross-polarization interference occurs multiple times, each with a different transmission path length. Not only that, but its own signal also changes its transmission path length and returns as an interference component.

In such a case, the interference component will be affected by all the values of several symbols before and after the received signal sample value (symbol) corresponding to the first and second data points. Here, if the transmission path is linear, this will be an additive effect. Therefore, the interference component also needs to be recognized as a value unique to the first and second data of K symbols (K is a positive integer) before and after the identification data.

In the embodiment shown in FIG. 4, when K=1, the identification value H(0) is set for the first data H(kT).
Values of one symbol before and after excluding H(-T), H
(T), V(-T) for the second data V(kT),
The purpose is to associate unique values as interference components with the five symbols V(0) and V(T). Therefore, in the memory circuit 3', reference numerals 1030, 1031,
Five input terminals 103' designated 1032, 1033 and 1034 are provided.

In addition, in order to obtain estimated identification values H^(-T) and V^(-T) of data subsequent to the time to be identified, a pre-discriminator 1' for the first data and one-symbol delay circuits 400 and 402 are used. A subsequent data identification value supply circuit 4 is provided. The estimated identification values H^(-T) and V^(-T) of the data preceding the time to be identified are already determined values, and H^(-T) is the delay circuit 403 and V^(-T). is also stored in the same type of cross-polarization compensation circuit for the second data, so it is supplied to the input terminal 105.

As a result, the output terminal 104 of the memory circuit receives the identification values {H^(-T), H^(T), V^(-T), V^(0).
,
V^(T)} is output. Since block 2 in FIG. 4 is exactly the same as block 2 in FIG. 3, a correct estimated identification value of the first data can be obtained at the output terminal.

FIG. 5 is a diagram showing a subsequent data identification value supply circuit for the general value of K, and shows the input terminals 107, 10.
9, 116 and the output terminal 108 correspond to the input/output terminals in FIG. Output terminal 2000, 20
01,......, (2000+K-1) and 2100,
2101,......, (2100+K) has identification values H(KT), H((K-1)T), H(T) and V(KT),
Since V((K-1T) and V(0) are each obtained, they are added to the input terminal of the memory circuit 3 as an address.

Next, consider a case where the mode of cross-polarization interference changes. At this time, it is necessary to sequentially change each unique constant in the memory circuit.

FIG. 6 is a diagram showing a configuration in which a function of sequentially changing this unique constant is added to the configuration of FIG. 3. Blocks 1 and 2 in the figure are block 1 and 2 in Figure 3, respectively.
2, and the reference number 3'' is a memory circuit, which changes the contents of the memory element selected by the input terminal 103, which is different from that in FIG. 3, to the value of the input terminal 111 via the signal line selector 35. It is a graphic representation of a normal random access memory (RAM), and in that sense it can be said to be the same as the memory circuit 3 in FIG.

Here, block 5 is a memory content modification circuit,
First, the input and output of the final discriminator are applied to input terminals 102 and 112, respectively, and both terminals are applied to a subtracter 51. The output of the subtracter 51 is an interference component if input noise is ignored. This is a value specific to the identification value obtained by the pre-discriminator 1. Attenuator 52 multiplies the previous interference component by a constant −α such that |α|≪|.

On the other hand, the value of the output terminal 104 of the memory circuit is read into another memory circuit 50, and this value and the output of the previous attenuator 52 are added to the adder 53 and the output terminal 1
Go out to 11.

The value at the output terminal 111 is read into the currently selected storage element in the storage circuit 3 for the next moment. In other words, the signal to the terminal 103 that is applied as an address to this series of operating memory elements 3'' does not change, and the unique value selected by this signal is the output of the subtracter 51, that is, the direction opposite to the compensation residual. It will be corrected.

FIG. 7 is a diagram showing a configuration in which the storage content modification circuit 5 of FIG. 6 is added to the block diagram of FIG. 4, and the other components are exactly the same as FIG. 4. As can be seen from this configuration example, the configuration of the memory content modification circuit 5 is a general configuration and is the same as the configuration shown in FIG.

The above are the peripheral technologies related to this invention.

Next, consider the compensation convergence speed of the compensation circuit shown in the block diagram of FIG. That is, in this example, the memory circuit 3' input terminals 1030, 1031, 1032, 1
033, 1034 are stored, but the unique values of the symbol group obtained by rotating this symbol group by 2π/MN are simply It is easy to think that it is the value obtained by multiplying the unique value of by exp{j2π/M·N}. Based on this idea, if the signal point constellations in each quadrant of the QAM equiphase plane overlap with π/2N rotations, where N is an integer, then out of all the symbol groups, four that have a π/2N rotation relationship The four unique values for each symbol group can be degenerated into one unique value.

As a result, each unique value will be rewritten four times more frequently than before. This increases the compensation acquisition speed by four times.

Furthermore, for the M phase modulation signal, all symbol groups in a 2π/MN rotational relationship have one unique value, so they are rewritten M times as often, and the compensation convergence speed increases M times. Therefore, if we take eight-phase phase modulation as an example, the speed will be eight times faster.

This invention utilizes the above-mentioned principle to apply the correction value obtained by the storage content correction circuit 5 of FIG. The purpose is to increase the convergence speed by sequentially supplying the unique values.

If this is to be done in chronological order, the following functions are required. First, to output a symbol group obtained by sequentially rotating the identification values obtained by the pre-identification circuit by 2π/MN, and then to rotate the unique values by 2π/M・N. To this, exp{j2π/M
・It is to sequentially obtain the values multiplied by N}.

FIG. 8 is an embodiment of a symbol permutation circuit that performs the first function for four-phase phase modulation. 1st
Signal points 4000, 40 of the four-phase phase modulation shown in Figure a
0, 1, 2 for 01, 4002 and 4003 respectively
If an integer of 3 is assigned to the output terminals 7001 and 7002, a modulo of 70, an adder of 4 and a counter of 71 are used to sequentially output terminals 7001 and 7002.
The symbol obtained by 2π/M·N rotation and the rotation parameter N are each output.

FIG. 9 shows an embodiment of a rotation conversion circuit that performs the second function.

If ε=a+jb, ε・e ^j 〓 ^/2 =−b+ja, ε・
e ^j 〓=-a-jb, ε・e ^{j 3/2} 〓=b-ja, so when the real part a and the imaginary part b of the signal ε applied to the input terminal 6002 are applied to the terminals 6019 and 6015, the input Terminal 600 controlled by the signal of terminal 6500
4,6005 and 6006, 6007, 6008,
6009, 6010, 6011, 6012, 60
By switching the connection with 13, the terminals 6004 and 60
ε, εe ^j 〓 ^/2 , ε・e ^j 〓, ε・e ^{j 3/2} 〓 appear at the output terminal 6000 which displays the value of 05 as a complex number.

FIG. 10 shows a block diagram of an embodiment of the present invention, in which a symbol permutation circuit 7 and a rotation conversion circuit 6 are added to the block diagram of FIG. The reference numerals 1, 2, 3 and 5 are therefore the same as in the block diagram of FIG.

Next, the operation of this embodiment will be explained.

First, the estimated discrimination value obtained by the prediscrimination circuit 1 is applied to the symbol substitution circuit 7. Since the value of the counter 71 of this circuit shown in FIG. 8 is initially always set to a value of zero, the output of the adder 70 of modulo 4 is the same as the input, and the output of the adder 70 of modulo 4 is the same as the input.
Values of 1 are equal. The output of terminal 7002 is also zero. A correction value corresponding to the value at the terminal 7001 appears at the output terminal 111 of the memory content correction circuit 5. This value is input to the next rotation conversion circuit 6. At this stage, the counter 71 in the symbol substitution circuit 7
changes from 0 to 1, 2, and 3. Accordingly, values obtained by multiplying the input by e ^j 〓 ^/2 , e ^j 〓, and e ^{j 3/2} 〓 appear at the output terminal 111' of the rotation conversion circuit 6.
At the same time, the value at the terminal 7001 also changes to the identification value rotated by 2π/MN radians. Using this value as an address, the values of the previous output terminal 111' are successively read into the memory circuit 3. In this way, a modified value for one symbol now modifies the unique values for three other symbols.
From this explanation, it can be seen that the symbol replacement circuit 7 and the rotation conversion circuit 6 constitute the storage circuit control circuit.

Therefore, the compensation control convergence speed of this embodiment is four times that of the original block diagram of FIG.

The compensation control convergence speed can be quadrupled in the same manner for the block diagram shown in FIG.

FIG. 11 shows an embodiment in which the storage circuit control circuit described above is operated in parallel processing, and block 6' in the figure is a parallel processing type rotation conversion circuit.
11 is exactly the same as block 3 in FIG. 30, 31, 32, 33, 3 in the diagram
4 and 35. Reference numbers 11001, 11002, 11003 and 11004 in block 6' are the rotation conversion circuits shown in FIG.
terminals 6004, 6005 and 6008, 6009 or 6013, so as to rotate by π/2 or -π/2,
6014 corresponds to the one to which it is fixedly connected.

A memory content modification circuit output is applied to terminal 111, and this value is applied and read into one of storage elements 30'-33' by signal line selector 35'. At the same time, the value obtained by rotating the value at terminal 111 by .pi./2.multidot.N radians is applied to and read from the other three storage elements through the rotation conversion circuit in block 6'.

[Brief explanation of the drawing]

Figures 1a and b are diagrams for explaining the signal points of four-phase phase modulation on the IQ phase plane; Figures 2a and b are diagrams for explaining the synchronous detection signal subjected to cross-polarization interference; 3 and 4 are block diagrams showing an example of a cross-polarization interference compensation circuit, FIG. 5 is a diagram showing a general form of a subsequent data identification value supply circuit, and FIGS. 6 and 7 are block diagrams showing an example of a cross-polarization interference compensation circuit. FIG. 8 is a block diagram showing another example of the compensation circuit, FIG. 8 is a diagram showing a symbol permutation circuit, FIG. 9 is a diagram showing a rotation conversion circuit, FIG. 10 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is a block diagram showing one embodiment of a parallel processing type storage circuit control circuit. In the figure, 1 is a pre-identification circuit, 20 is a subtracter, 21
5 is a final identification circuit, 5 is a storage content modification circuit, 6 is a rotation conversion circuit, and 7 is a symbol replacement circuit.

Claims (1)

[Claims] 1. First data and second data are independent digital signals using first and second polarized waves that are orthogonal to each other.
The transmission code point arrangement on the amplitude phase plane is
In a wireless transmission method using amplitude phase modulation having a rotationally symmetrical structure every 2π/M (M is an integer of 2 or more), a pre-identification circuit that estimates and identifies second data, and each of the pre-identification circuits. a memory circuit that selects and provides a readable/writable memory element corresponding to an identification value; and a subtracter that subtracts the contents of the memory element that is selectively provided based on the identification value output from the pre-identification circuit from the first data; , a final identification circuit that estimates and identifies the first data from the output of the subtracter, an error detector that outputs the input/output difference of the final identification circuit, and an output of the storage element currently selected according to the output of the error detector. a memory content modification circuit that outputs a modified value with modifications made to the above, and a memory content modification circuit that writes the output of the memory content modification circuit to the currently selected memory element, and writes the identification value of the prediscrimination circuit output on a signal point arrangement plane. (M-1) memories corresponding to other (M-1) identification values obtained by rotating 2π/M・N (N is an integer from 0 to (M-1) radians) around the origin a storage circuit control circuit that causes each element to read a value obtained by multiplying the correction value by exp{j2π/M・N}, and detects cross-polarized waves generated in a wireless transmission path whose mode changes from the output of the final identification circuit. A cross-polarization compensation circuit characterized in that first data is obtained by removing interference between first data and second data due to interference.