JPS63220613A - Group delay adjusting device for audio - Google Patents

Abstract

PURPOSE:To prevent generation of a ripple on a group delaying characteristic and to stabilize an image in a reproducing sound field by executing the re-writing control of the coefficient of a digital filter concerning one or above selected in an M pair of whole area passage type digital filters in accordance with the information designated by a characteristic input part. CONSTITUTION:For central angle frequencies thetap1, thetap2...thetapn at plural frequency bands, the difference between mutually adjoining angle frequencies come to equal. All distances r1, r2...rn to line respective poles P1, P2,...Pn and a center are made equal. While respective poles P1, P2,..., Pn are made into the condition in which they are arranged concentricly, the digital filter coefficient in respective filters is set so that the group delaying quantity of plural whole area passage type digital filters can be wholly the same. Thus, a group delaying quantity taug comes to be a constant condition, the general group delaying characteristic of the N-number of whole area passage type digital filters is made into approximately the flat condition and concerning the total frequency band, the group delaying characteristic of the condition without unevenness can be obtained.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention provides an audio group delay adjustment device 1 that is capable of extracting an audio signal such as a PCM audio signal by varying the amount of group delay for each frequency band. The present invention relates to a delay adjustment device configured as described above.

(Prior art) The level difference and time difference (phase difference) between the sounds given to both ears of a listener are greatly related to the listener's sense of left and right direction and the localization of the sound image in a 3D sound field. is well known, and has traditionally been used to change the stereoscopic effect felt by listeners and the sense of localization of sound images in a three-dimensional reproduction sound field created using an electroacoustic transducer. Efforts have been made to vary the amplitude and phase.

By the way, in order to finely change the phase of an audio signal in the form of an analog signal using a phase shifter configured by a combination of circuit elements such as resistors, capacitors, and coils, which has been most commonly used in the past, Since this requires the use of an expensive and complicated phase shifter, such a method is difficult to implement in consumer equipment.

In recent years, digital signal processors (hereinafter referred to as DSPs)
A group delay adjustment device using a DSP (sometimes abbreviated as L,
R, Rabjnar and B, Gold r Th
theory and application of D
digital Signal ProcessingJ
Englewood C11ffs, NJ: Pren
tice-Hall, 1975, pp. 273-279) is being put into practical use, and if this DSP-based group delay adjustment device is used as a phase shifter for audio signals, the above problem can be solved. It is thought that

(Problems to be solved by the invention) By the way, in the conventional group delay adjustment device using DSP,
When constructing an all-pass filter that can obtain a predetermined group delay characteristic, the equiripple method was used to set the coefficients of the digital filter. When an all-pass filter having predetermined group delay characteristics is constructed by setting coefficients, irregularities (ripples) appear on the group delay characteristics.

When signal processing of an audio signal used to form a three-dimensional playback sound field is performed using a conventional group delay adjustment device that has irregularities in the group delay characteristic as described above, the sound image in the playback sound field is Since the sense of localization is unnatural, the emergence of a group delay adjustment device that does not cause the above-mentioned problems has been long awaited.

(Means for solving the problem) The present invention includes a characteristic input section for specifying a desired group delay characteristic, and a characteristic input section for specifying a desired group delay characteristic;
N all-pass digital filters corresponding to different frequency bands (where N is a natural number of 2 or more) are set so that their overall group delay characteristics are approximately flat. M sets (where M is a natural number of 2 or more) of all-pass digital filters in which N all-pass digital filters are one set of all-pass digital filters.
Digital filters that can configure filters = 3
= arithmetic means; the audio group delay adjusting device is configured to include a calculation means, and is configured to adjust the selected value in the M sets of all-pass digital filters according to the information specified by the characteristic input section. To provide a group delay adjustment device for audio, comprising means for controlling rewriting of coefficients of a digital filter so that filter characteristics are changed to equal group delay amounts at input and output for one or more filters. It is.

(Example) Hereinafter, specific contents of the audio group delay adjustment device of the present invention will be explained in detail with reference to the accompanying drawings. Fig. 1 is a block diagram of an embodiment of the audio group delay adjustment device of the present invention, and Fig. 2 shows the adjustment of the group delay amount for each frequency band in a plurality of frequency bands in which the group delay amount should be adjusted. FIG. 3 is a block diagram showing an example configuration of a DSP, and FIGS. 4 and 12 show the characteristics that should be obtained by the operation of the DSP. Various configurations of filters - 4 = A block diagram showing an example, FIG. 5 is a timing chart for explaining the operation of the audio group delay adjustment device of the present invention, and FIGS. 6 and 11 respectively show the central processing unit ( C.P.
FIG. 7 is a flowchart for explaining the operation of U), FIG. 7 is a diagram for explaining the characteristics of the all-pass digital filter, and FIG. 8 is a flowchart for explaining the poles and zeros (mirrors) of the all-pass digital filter. FIG. 9 is a plan view showing an example of a memory map in a coefficient setting section and a coefficient memory, and FIG. 10 is a block diagram showing a specific configuration of a multiplexer and a transmitting section.

In FIG. 1 showing a block diagram of an embodiment of the audio group delay adjustment device of the present invention, 1 is an input terminal for a digital signal, and this input terminal 1 has a predetermined amount of signal in the audio group delay adjustment device. An audio signal (hereinafter simply referred to as a digital signal) is supplied as a digital signal of a predetermined format to which a group delay of .

The digital signal supplied to the input terminal 1 described above is demodulated by receiving sections R and D. PLT is a phase-locked
This phase-locked loop PLL
is used to synchronize the phase of the clock in the digital data obtained by demodulating in the receiving section RD and the clock generated in the receiving section RD. It goes without saying that the input signal may be a serial signal or a parallel signal depending on the configuration of the device.

The signal demodulated by the receiving section RD, for example, an NRZ signal, is sent to a digital signal processor DSPQI, D
Provided to SPrl. Digital signal processor DSPnl-DSPQm, DS P rl-D S
As P rm, for example, one having a configuration as shown in FIG. 3 can be used. Note that the digital signal processor DS shown in FIG.
Pfil~DSPQm.

DSPrl to DSPrm and digital signal processors DSPQ and DSP specifically shown in FIG.
r means that the corresponding input/output terminals in both are given the same symbol a −
It is marked with h.

Digital signal processor DSPQ1 to DSPi
1m operates as an all-pass type digital filter by performing all-pass type digital filter calculation to realize the group delay characteristic set in the characteristic input section CHD for the left channel signal of the stereo signal. and digital signal processor DSPrl~
The DSPrm operates to function as an all-pass digital filter by performing all-pass digital filter calculation to achieve the group delay characteristic set in the characteristic input section CHD for the right channel signal of the stereo signal. However, each of the above-mentioned digital signal processors DSIII to DSP Qm, DSP
rl"D S P rm has the same configuration and the same operation mode, so in the following explanation,
Each digital signal processor DSPQ1 described above
When describing matters common to DSPQm and DSPr1 to DSPrm, the subscripts Ql, ρ2, .

The explanation is given with rl, r2...rm omitted.

The characteristic input section CID for specifying a desired group delay characteristic has a plurality of input terminals for individually adjusting the group delay amount for each of a plurality of frequency bands, as shown in FIG. Characteristic variable selection switch (f 1. f in Figure 2)
2... Above fn, the selection switch for changing characteristics is indicated by an array of m circles in the vertical direction and n circles in the horizontal direction, and in the figure, the ones marked with black circles are (representing the switch being selected and operated) is provided.

DPA is a display section, and this display section DPA performs a predetermined display according to a signal supplied from the central processing unit CPU.
This allows the subcode of the information supplied to the PU to be displayed on the display section DPA.

Central processing unit CPU is read-only memory ROM
and a random access memory RAM, and the group delay amount corresponding to the group delay amount for each frequency band set in the characteristic input section CHD is determined by the input digital signal supplied to the audio group delay adjustment device. In order to generate the group delay amount corresponding to the group delay amount for each frequency band set in the characteristic input section CID described above, the digital
Controlling the signal processor DSP to perform all-pass digital filter calculations, displaying a predetermined display on the display DPA, etc.
Controls the operation of each part of the audio group delay adjustment device.

Further, in FIG. 1, STD is a serial code transfer section, SCG is a clock signal generation circuit, MPx is a multiplexer, TD is a transmission section, and 2 is an output terminal.

In Figure 3, which shows a specific configuration example of a digital signal processor DSP, SDI is a serial data input circuit, IB is an input buffer, NG-RAM is a coefficient RAM, TB is a transfer buffer, and PCI). is the parameter control section, P-RAM is the program RAM, SDO is the serial data output circuit, and SCI is the serial code
Interface, D-RAM is data RAM.

Furthermore, FN-ROM is a constant memory ROM, MUL is a multiplier, ACC is an accumulator, REG is a register with thick, and OB is an output buffer.

Digital signal processor D shown in the third diagram above
The components in the SP, which include a constant memory ROM (FN-ROM), a multiplier MUL, an accumulator ACC, a register with a shifter REG, an output buffer OB, etc., have a well-known circuit configuration and are based on the present invention. Since it is not directly related to the explanation of , a detailed explanation thereof will be omitted.

The program RAM (P-RAM) described above stores in advance a program to be executed by the digital signal processor DSP, and functions as a coefficient memory by storing data such as multiplication coefficients alo to bn2. NC-RAM), these data are supplied to multipliers M and UL.

The serial code interface SCI is equipped with a serial code input terminal C and a serial code output terminal d, and receives clock signals and synchronization signals (LRCK, T, R,
CK bar) to input data (SD, SD') from the serial code input terminal C and output data (SD, SD') from the serial code output terminal d.

The parameter control unit PCD described above has a serial code.
Program RA with data from interface SCI
, M (P-RAM) and the transfer buffer TB, and outputs control signals Ts and Tw specifying the transfer timing and the number of transfers from the transfer buffer TB. g is a trigger input terminal of the parameter control unit PCD.

When a trigger (synchronization signal) input is supplied from the outside to the trigger input terminal g, the parameter control unit PCD of 11jJ u generates a control signal Ts whose transfer timing is determined by the 1 heligate input. Although the configuration is such that the parameter control section P
The CD has a function that allows it to be triggered by data (SD, SD') even if no external trigger input is supplied to the terminal g.

The two digital signal processors DSPβ and DSPr used in the audio group delay adjustment device shown in FIG. Since the terminal g is not used, the terminal g is not used.

The serial data input circuit SDI serially-parallel converts the audio input data from the serial data input terminal a, and sends it to the data RAM (D-RAM) via the input buffer IB.
). f in the figure is a data clock signal BCLK and a channel identification signal LRCK that are supplied to the serial data input circuit SD and the serial data output circuit SDO in order to determine the timing of serial data input and serial data output. This is the input terminal of

FIG. 4 shows an example of a digital filter that can obtain the desired filter characteristics through the arithmetic operation of the digital signal processor DSP in the audio group delay adjustment device of the present invention shown in FIG. This is a diagram showing a specific circuit configuration, and in this figure, 3 is an input terminal, 4 is a unit delay operator, 5 is a multiplication circuit, 6 is an addition circuit, 7 is an output terminal, The filter shown in FIG. 4 has an all-pass filter configuration in which n piquad filter sections FLTI to FLTn having the same configuration are connected in series in n stages.

As is well known, the transfer function I(A(Z)) of the all-pass digital filter as shown in FIG. 4 is expressed by the following equation.

In the case of an all-pass type digital filter, the coefficient ai2 of the coefficients of the digital filter can be set as ko, and in the all-pass type digital filter,
As shown in FIG. 8, Pi and P2 on the two plan views
．． Each pole of P3-Pn-1 and Pn overlaps with the zero (mirror), and the phase characteristic θ(ω) changes to the frequency (normalized frequency) as shown in FIG. 7(b). It is known that ω) monotonically decreases in each piquad filter unit (unit filter), and the group delay characteristic τg(ω) described above is τg(ω) = −dθ(ω)
/dω, so Gdl in FIG. 7(a).

Group delay characteristics represented by Gd2...Gdn are obtained for each piquad filter section FLTI to FLTn.

Therefore, the angular frequency θp1 of the pole Pl of the piquad filter unit FLTI can be made to correspond to the center frequency f1 of the first band frequency of the group delay characteristic shown in FIG. 7(a), Similarly, each piquad filter section F
The angular frequencies θp2 to θpn of the respective poles P2 to Pn of LT2 to FLTn can be made to correspond to the center frequencies f2 to jn of the second to nth band frequencies.

Now, the central angular frequency 0Ply in multiple frequency bands
θP2...Openn is set so that the difference between adjacent angular frequencies is equal, that is, the following equation (1) is satisfied, and each pole Pi, P2...
・The distances rl, r2...rn connecting Pn and the center are all made equal as shown in the following equation (2) % (2), and each pole P1゜P2 ・
・・・・・・Plural all-pass digital filters are arranged so that the group delays of the plural all-pass digital filters are all the same while Pn are arranged on concentric circles.
When the digital filter coefficients in the filter are set, the group delay amount τg becomes constant as τgt in Figure 7, and the overall group delay characteristic of the N all-pass digital filters is approximately flat. This results in a smooth group delay characteristic over the entire frequency band.

Regarding the all-pass type digital filter configured as shown in Fig. 4, each piquad filter section F L Tl'' F is capable of obtaining a group delay characteristic without irregularities in the entire frequency band as described above. L T
An example of the filter coefficient of n, when n=10, is as follows.

FLT filter coefficient 1, a 10 =0.2279777008a 11=
-0,9435036489a 12 = 1.00
00000000b 11 = 0.94350364
89b 12=-0,22797770082,a
20 = 0.2279540615a 21 = -
0,8539270229a 22 = 1.0000
000000b 21 = 0.8539270229
b22=-0,22795406153,a30
=0.2286841630a 31 = -0,6
855207745a 32 = 1, 000000
0000b 31 = 0.6855207745b
32=-0,22868416304,a 4(1-
0,2309500374a 41 = -0,452
8444485a 42= 1.0000000000
b41=0,4528444485 b42=-0,2309500374 5, a 50=0.2332873199a 51=
-0,1723049176a 52=1.00000
00000 b 51=0.1723049176 b 52=-0,23328731996, a 60=
0.2355608216a 61=0.126503
6337 a 62=1.0000000000 b 61= -0,1265036337b 62=
-0,23556082167, a 70=0.239
9302297a 71=0.4180445346 a 72= 1.0000000000b 71= -
0,4180445346b 72=-0,2399
30229710, a 1.0.0=0.2566
032823a 10.1=0.9991342740
a 10,2=1.0000000000b IQ, 1
=-0,9991342740b 10,2=-0,2
566032823 Next, switching of group delay characteristics will be explained with reference to FIG. The switching of the group delay characteristic can be achieved by switching the program of the filter that substantially constitutes the digital signal processor DSP, or by changing the coefficients alO~bn2 of the filter that substantially constitutes the digital signal processor DSP. This can be done by switching the coefficient data, and the control of the switching operation of the group delay characteristic is performed by the central processing unit CP.
Done by U.

In the following description, an example is given in which switching of group delay characteristics is performed by switching coefficient data corresponding to coefficients alo to bn2 of a filter that essentially constitutes a digital signal processor DSP. . Now,
The central processing unit CPU described above is configured to operate according to the flowchart shown in FIG. 6 based on control signals from the read-only memory ROM and the random access memory RAM. First, a characteristic change routine is started at the start, and Bandwidth counter ■ is set (step 100 in FIG. 6). Read the setting value of the band (step 101) and judge whether a change has been made.Step 102).If YES, select the characteristic coefficient.Step 103), and write it in the coefficient setting section (step 102).
Step 104), if NO, read the subcode output from the receiver RD, send it to the transmitter TD as necessary, and display the sampling frequency fs, presence or absence of emphasis, and synchronization of the phase-locked loop P L L on the display DPA. Information such as misalignment is displayed (step 106).

Then, increment the band counter I (step 1
07) L. If the number of bands does not exceed N, the process returns to step 101; if it does, the process returns to step 100 (YES in step 107).

In this way, the coefficients of the digital filter are rewritten for each AAA filter provided for each frequency band. When the characteristic variable selection switch in the characteristic input section CHD is not selected, the digital filter coefficient of the corresponding unit filter FLTi is a
io==1. ail=o, ai2=o.

bi 1 = O, bi 2 = o, and the unit filter has filter characteristics such that the group delay amount at the input and output is equal.

Thereby, one digital signal processor D
The amount of group delay in the multiple all-pass digital filters configured by the operation of SP is such that there is no ripple in the amount of group delay in each frequency band and it smoothly connects to the amount of group delay in adjacent frequency bands. It can be calculated as

A more specific explanation is as follows.

That is, the central processing unit 1cPU is, for example, R823.
2C serial format, the digital signal processor D is sent via the serial transfer unit STD in Figure 1.
When digital filter coefficient data is sent from serial code input terminal C of SP, the digital filter coefficient data is sent to transfer buffer TB via serial code interface SCI and parameter control unit PCD in FIG. It will be done.

FIG. 9(a) shows an example of a map of the transfer buffer TB, and in FIG. 9(a), addresses O to 3
The digital filter coefficient data alo is stored in the memory part of , and the digital filter coefficient data a11 is stored in the memory part of addresses 4 to 7, and so on. Digital·
The coefficient data of the filter is stored sequentially and is stored at address (4
The storage area specified by X (5n, -1)) - (4
An example in which n2 is stored is shown.

In addition, (b) of FIG. 9 is an example of a map of the coefficient RAM (NC-R, AM), and in (b) of FIG. 9, the coefficients of the digital filter are stored in the memory area of addresses O to 1. Data alO is stored, and digital filter coefficient data all is stored in the storage portions of addresses 2 and 3, and so on, the digital filter coefficient data is sequentially stored in the storage portions specified by the sequential addresses. It is stored at address (2X(5n -1)) ~ (2X(5n
An example is shown in which coefficient data bn2 of a digital filter is stored in the storage portion designated by -1)+1).

The map of the transfer buffer TB illustrated in FIG. 9(a) and the coefficient RAM (NC
-RAM) map, the address of the storage part where the coefficient data of the same digital filter should be stored is different when the coefficient data of each digital filter is 32 bits (8 bits x 4). In this case, the transfer buffer TB has 8 bits 1. Coefficient RAM (NC-
This is because the illustration is based on an example in which a RAM (RAM) with a storage capacity of 16 bits per address is used.

The address described above is specified in the third serial data of the 4-byte instruction set as shown in (i) of FIG. 5, and the coefficient data of the digital filter described above is specified as (i) of FIG. It is specified by the fourth serial data of the 4-byte instruction set as shown in .

If the word length of the coefficient data of the digital filter is 32 bits as in the example described above, the coefficient data of the digital filter is sent in four parts of 8 bits each. Note that the first code 1 and the second code 2 of the serial data of the 4-byte instruction set shown in (i) of FIG. 5 are for chip enable, which It is used to distinguish whether to select a digital signal processor DSP, etc.

The CRS bar in (h) of FIG. 5 is a start signal that informs the start of serial code transfer, and the start signal CRS bar for starting the serial code transfer is sent from the serial code transfer section STD to the input terminal of the serial code interface SCI. is applied to the

The digital filter coefficient data sent to the transfer buffer TB of the digital signal processor DSP is triggered by an external synchronization signal together with the digital filter coefficient data that has already been sent. Five words are sent to RAM (NG-RAM) for each unit filter. Then, the coefficient data of the digital filter is stored in the coefficient RAM (NC-RAM).
) Next to step 104 in FIG. 6, the synchronization signal is sent from the serial transfer unit STD to the code 1. Provided encoded in code 2 (step 105)
.

Note that the digital signal processor DSP described above
The clock signal that determines the program instruction cycle of
Data clock signal BCL generated in receiving section RD
Clock signal fg with a frequency 128 times K ((
g)) is used, the clock signal fg of which is supplied to the clock input terminal f.

SCG in FIG. 1 is a clock signal generation circuit that generates a clock signal with a frequency corresponding to the transfer rate of the serial transfer unit STD, and the clock signal generated by the clock signal generation circuit SCG described above is digital.・Signal processor DSP serial code interface SCI serial code timing signal input terminal e
supplied to

The 2M digital signal processor DSP shown in the audio group delay adjustment device shown in Figure 1 realizes the group delay characteristic set in the characteristic input section CID for the left channel signal in the stereo signal. M sets of digital signal processors DSPQI to D that perform all-pass digital filter operations to function as all-pass digital filters;
E3PQm performs all-pass type digital filter calculation to realize the group delay characteristic set in the characteristic input section CHD for the right channel signal of the stereo signal, and functions as an all-pass type digital filter. M sets of digital signal processors DSPr
Each set of digital
The signal processor DSP operates in the manner described above, and when the characteristic variable selection switch in the characteristic input section CID is not selected,
The coefficients of the digital filter provided for each frequency band of the digital filter of the corresponding unit filter FLTi are aio==1. ail=o, ai2=0. bil=o.

bi2=o, and the unit filter has filter characteristics such that the group delay amount at the input and output is equal.

By the way, each set of digital signal processors DSP in the above-mentioned 2M sets of digital signal processors DSP is to be constructed by each set of digital signal processors DSP described above. Assuming that the overall group delay characteristic of the filter is approximately flat and has no unevenness in all frequency bands, a constant group delay amount τgt as shown by gt in Fig. 7 can be obtained. In order to do this, the distances rl, r2 connecting the poles P1, P2...Pn and the center under the conditions of equations (1) and (2) mentioned above are
...rn must all be set to the same specific value, resulting in the N all-pass digital signals used to impart group delay to the signal in the audio group delay adjuster. The group delay amount of the digital signal processor DSP that constitutes the filter is set to a specific value.

Therefore, if there is one digital signal processor (DSI) used to impart a group delay to the signal in the audio group delay adjustment device, then the group delay applied to the signal by the audio group delay adjustment device is Although the adjustment range of the delay amount is limited to a relatively narrow range, in the audio group delay adjustment device of the present invention, M sets of digital signal processors are used for each of the left channel signal and the right channel signal. DSPflll～DSP
Q m and M sets of digital signal processors D
Since SPr1 to DSPrm are used, the audio group delay adjustment device of the present invention can widen the adjustment range of the group delay amount to be given to the signal.

Now, in FIG. 5 showing a timing chart of the audio group delay adjustment device (system) shown in FIG. The calculation result of the coefficient data of the digital filter is outputted, and the multiplexer MPX shown in Fig. 1 outputs the result of the calculation of the coefficient data of the digital filter, and the time division signal of the left and right channels (format (a) in Fig. 5) and the output from the digital signal processor DSPr are output. After that, the signal is converted into a digital audio interface format in the transmitting section TD, which has an audio data modulation function and a transmitting function, and then sent to the output terminal 2.

Note that the digital data transmitted from the input terminal 1 through the digital audio interface format I- is demodulated into NRZ in the receiving section RD as serial digital audio data ((a) in FIG. 5), and is converted into digital audio data. tL is applied to each input terminal a of the signal processors DSPQl and DSPrl, and the above-mentioned receiver RD demodulates timing signals such as channel identification signals T, RCK, WCK, etc., and converts them into 2M sets of digital signals.・Processors DSPQ1-DSPQm, DSPfl
By supplying r-DSPrm and the transmitter TD, each of the above components can operate in synchronization with each other.

FIG. 10 shows a specific configuration example of the multiplexer MPX and the transmitter TD.
By sequentially and alternately turning on and off the changeover switches SWQ and SWr in accordance with the channel identification signal LRCK, the left channel signal and the right channel signal are sequentially and alternately supplied to the transmitter TD on the time axis. I in the diagram
NV is an inverter.

In the description of the embodiments so far, it has been explained that an all-pass type digital filter having a configuration in which n piquad filter sections having the same configuration are connected in cascade as shown in FIG. 4 is used, but the present invention In implementing the above, an all-pass type digital filter may be used that has a configuration in which n pi-quad filter sections with the same configuration are connected in parallel, and as described above, n pi-quad filter sections with the same configuration When using a configuration in which filter sections are connected in parallel,
An all-pass type digital filter can be realized by scaling the digital filter coefficient data while being careful about overflow.

In addition, in the description of the embodiments so far, an all-pass type digital filter configured with a second-order IIR as a unit filter has been described as an example, but the explanation is not limited to this. Alternatively, the configuration of the all-pass digital filter may be changed depending on the bandwidth and frequency, such as a mixed configuration in which a first-order IIR and a second-order IIR are used as a unit filter. Needless to say, it can be modified and used.

It should be noted that the digital signal processor DSP to be used is not limited to the configuration described above, and in short, the digital signal processor DSP is an embodiment of programmable digital signal calculation means. It's not too much. Further, in the embodiments so far, a digital signal input and digital signal output system has been described, but the implementation of the present invention is not limited to such a system type. For example, an AD converter, an AD converter, Of course, the present invention can also be applied to a system that uses a DA converter on the output side to provide analog signal input and analog signal output.

FIG. 11 is a flowchart in which the group delay characteristics are switched in a different manner from the group delay characteristic switching manner already described with reference to FIG. The switching operation performed under the control of the central processing unit CPU will be described with reference to the flowchart shown in FIG. First, the characteristic change routine is started at the start, and the bandwidth limit is set (11th
Figure step 200). Read the set value of band (band) (step 201), increment the band counter I (step 202), and if the value of bandwidth counter I does not exceed N, proceed to step 2 like N in step 203.
Return to step 01 and read the setting value of band (band) (step 201), and if the value of band power untae exceeds N (
If YES in step 203), it is determined whether a change has been made or not. If YES in step 204), the multiplier M
It is sent to the UL (MUL in Figure 4) several times.

Next, the optimum characteristic program for the aforementioned changes is selected (step 206) and sent to the digital signal processor DSP (step 207), and coefficient switching is started (step 208) to gradually level the output data. The coefficients cf increasing in value are sent one after another to the multiplier MUL (MUL in FIG. 4), and the process returns to step 200.

If there is no characteristic change (No in step 204), the sixth
Step 10 in the flowchart shown in the figure
The same display as in case 6 is performed (step 210) and the process returns to step 200.

The reason for changing the program as described above is that each digital signal processor DSP has a configuration shown in FIG. In the case of a configuration in which one set of M sets of all-pass filters are connected in cascade, and in the case of a configuration in which M sets of all-pass filters FLI to FLm are connected in parallel as illustrated in FIG. This is because, since the optimal word length for each case is different, it may be desirable to change the program for each case.

In FIG. 12, MUL is a multiplier and ADD is an adder. Also, when M sets of all-pass filters are connected in parallel as shown in FIG.・Signal processor DSP
The decision as to whether to assign someone to take charge of this can be made from the viewpoint of equalizing the calculation time.

(Effects of the Invention) As is clear from the above detailed explanation, the audio group delay adjustment device of the present invention includes a characteristic input section for specifying a desired group delay characteristic, and N (where N is 2 or more). N all-pass digital filters each corresponding to a different frequency band (a natural number) are set so that their total group delay characteristics are approximately flat. The filter is configured to include digital filter calculation means that can configure M sets (where M is a natural number of 2 or more) of all-pass digital filters, each of which is a set of all-pass digital filters. The audio group delay adjusting device adjusts the group delay at the input and output of one or more selected MJfl all-pass digital filters according to the information specified in the characteristic input section. Since the audio group delay adjustment device of the present invention includes means for controlling rewriting of the coefficients of the digital filter so that the filter characteristics are changed to the same filter characteristics, the audio group delay adjustment device of the present invention has a plurality of coefficients. all-pass digital
The digital filter coefficients of multiple all-pass digital filters are set so that the group delay amount of the filters is all the same, and the overall group delay characteristic of the multiple all-pass digital filters is approximately flat. If the characteristic variable selection switch in the characteristic input section is not selected, the corresponding unit filter F L T The digital filter coefficients of i are aj, o=1, ail=o, ai2=o, bi 1=
O.

bi2=o, and the unit filter has a filter characteristic in which the group delay amount at the input and output is equal, and ripples occur in the group delay amount in each frequency band in multiple all-pass digital filters. Without,
Because it can be calculated as something that smoothly connects to the group delay amount in the adjacent frequency band, this problem occurred when completely rewriting the group delay characteristic designed using equiripple approximation as in the conventional example mentioned above. No ripple occurs,
Furthermore, the state of connection between adjacent frequency bands becomes smooth, and therefore the localization of the sound image can be made natural.

In addition, 2M sets of digital signal processors DSP
each set of digital signal processors DS in
Let P be a condition in which the overall group delay characteristic of the N all-pass digital filters to be constructed by each of the above digital signal processors DSP is approximately flat and there is no unevenness in the entire frequency band. When configured as having group delay characteristics, the above-mentioned (1) and (2)
Pole PI under the conditions of the formula, P2... Distance '111rl connecting Pn and the center.

Since all of r2...rn must be set to the same specific value, N all-pass digital
By setting the group delay amount of the digital signal processor DSP that makes up the filter to a specific value,
Digital signal processor DS used to impart group delay to a signal in an audio group delay adjustment device
If P is one, the adjustment range of the group delay amount given to the signal by the audio group delay adjustment device is limited to a relatively narrow range, but the audio group delay adjustment device of the present invention Now, since M sets of digital signal processors DSP121 to DSPQm and M sets of digital signal processors DSPrl to DSPrm are used for the left channel signal and right channel signal, respectively, the audio signal processor of the present invention With the group delay adjustment device, the amount of group delay to be given to the signal can be adjusted over a wide range. According to the group delay adjustment device for audio of the present invention, the above-mentioned conventional problems can be solved. All points can be resolved satisfactorily.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the audio group delay adjustment device of the present invention, FIG. 2 is a front view of a characteristic input section, FIG. 3 is a block diagram showing an example configuration of a DSP, and FIGS. 1
2 is a block diagram showing the configuration of a filter to be obtained by the operation of the DSP, FIGS. 5 and 11 are timing charts for explaining the operation of the audio group delay adjustment device of the present invention, and FIG. 6 is a central processing A flowchart for explaining the operation of the device (CPU), FIG. 7 is a diagram for explaining the characteristics of the all-pass digital filter, and FIG. 8 is for explaining the poles and zeros (mirrors) of the all-pass digital filter. FIG. 9 is a diagram showing an example of a memory map in a coefficient setting section and a coefficient memory, and FIG. 10 is a block diagram showing a specific configuration of a signal combining section and a transmitting section. l...digital signal input terminal, 2...output terminal,
3...Input terminal, 4...Unit delay operator, 5...
Multiplication circuit, 6... Addition circuit, 7... Output terminal, RD
...Receiving section, PLL...Phase locked loop, DSPQ. DSPr...Digital signal processor, CI
D...Characteristics input section, DPA...Display section, CPU...
・Central processing unit, ROM...read-only memory, RAM...random access memory, STD...
・Serial code transfer unit, SCG...clock signal generation circuit, MPX...multiplexer, TD...
Transmission section, SDI...serial data input circuit, I
B...Input buffer, NG-RAM...Coefficient RAM
, TB...transfer buffer, PCD...parameter control unit, P-RAM...program RAM, SDO...
・Serial data output circuit, SCI...serial code interface, D-RAM...data RA
M, FN-ROM... ROM for constant memory, MUL
... Multiplier, ACC... Accumulator, REG.
...Register with shifter, OB...Output buffer, BC
LK...data clock signal, LRCK...channel identification signal, FLTI~FLTn...n of the same configuration
piquad filter section, MUL... multiplier, A
DD...Adder, JP-A RU63-220613 (12) Procedural official document = (spontaneous) 1985 Patent Application No. Slt9gg No. 2, title of invention Group delay adjustment device for audio 3, case of person making amendment Relationship with Patent Applicant Location: 3-12 Moriya-cho, Kanayō-ku, Yokohama-shi, Kanagawa Prefecture Name (432) Victor Company of Japan 4, Agent Address: 3-4-19-915, Higashishina-yo, Tokyo Parts Ward Correct the number. (2) Page 25 of the specification, lines 11-12 “Data...
・Correct +3CLKJ to "sampling pulse frequency". (3) ``Signal synthesis section'' on page 39, line 7 of the specification is amended to ``Multiplex J.'' Name: Group delay adjustment device for audio 3, relationship with the case of the person making the amendment Patent Applicant Address: 3-12 Moriya-cho, Kanayō-ku, Yokohama, Kanagawa Prefecture Name (432) Victor Company of Japan Co., Ltd. 4, Agent 6; Target of correction

Claims (1)

[Claims] A characteristic input section for specifying the desired group delay characteristic, and N all-pass digital filters each corresponding to N different frequency bands (where N is a natural number of 2 or more) calculate their overall group delay characteristic. N all-pass digital filters are set to have a substantially flat state.
an audio group configured to include digital filter calculation means capable of configuring M sets (where M is a natural number of 2 or more) of all-pass digital filters; A delay adjustment device, which according to the information specified by the characteristic input section described above,
For one or more of the M sets of all-pass digital filters selected above, the coefficients of the digital filters are controlled to be changed to filter characteristics such that the group delay amounts at the input and output are equal. An audio group delay adjustment device comprising: