JPS632194A - Output buffer circuit for memory - Google Patents

Abstract

PURPOSE:To increase the speed for reading without increasing the drive capability of a transistor (TR) especially by providing a bias circuit keeping an output of the titled output buffer circuit to a voltage nearly equal to a threshold voltage of the post-stage circuits. CONSTITUTION:When an address signal is changed, an equalizing signal is generated from an address transition detector 5 with a delay of several nsec to equalize a bit line and a data line of a memory circuit 3. Further, switching MOSFETs Q3, Q4 of the output buffer circuit 6 are conducted. Since MOSFETs Q5, Q6 keep the level of an output terminal of the output buffer circuit 6 to 1.5V being a level equal to an input threshold voltage Vth of a TTL circuit, the output terminal level is brought quickly to 1.5V by the operation of the bias circuit. When the equalizing signal falls, the MODFETs Q3, Q4 are both turned off and the bias circuit comprising the MOSFETs Q5, Q6 is made inoperative.

Description

[Detailed description of the invention] The present invention will be described in the following order.

A. Industrial field of application B1 Overview of the invention C3 Prior art [Figure 3 D0 Problems to be solved by the invention [No. 4,'! jIJ5 Figure] E1 Means for solving the problem F0 Effect G, Actual h1 example [Figures 1 and 2] H9 Effects of the invention (A, Industrial application field) The present invention relates to an output buffer circuit for a memory, In particular, the present invention relates to a novel output buffer circuit that enables high-speed data reading.

(B. Summary of the Invention) The present invention provides a bias circuit that attempts to maintain the output of the output buffer circuit at a voltage approximately equal to the threshold voltage of the circuit at the subsequent stage in the output buffer circuit of the memory, so that the equalization signal is Therefore, when the address transition occurs, the bias circuit is activated by the equalization signal generated along with the transition, and the bias circuit is activated before the data signal is input to the output buffer circuit. The output voltage of the output buffer circuit is set to a value substantially equal to the threshold voltage of the subsequent circuit. When the equalize signal disappears, the bias circuit becomes inoperable, and when the data signal is subsequently input to the output buffer circuit, the threshold voltage changes to a voltage corresponding to the data signal. Therefore, the time required to reach a readable state can be shortened.

(C, Prior Art) [FIG. 3] FIG. 3 shows a conventional output buffer circuit for static RAM. In the figure, a is a sense amplifier that amplifies a data signal read from a memory cell (not shown). b is an inverter that inverts the output of sense amplifier a, C is an output buffer circuit, and is a complementary MO
Consists of an S inverter circuit. Qp is a P-channel MOSFET constituting the inverter circuit, and Qn is also an N-channel MOSFET. Complementary MOS
An inverter generally operates by receiving a power supply voltage of 5V (or 6V). In addition, the circuit connected to the output terminal of the output buffer circuit as a logic circuit at the subsequent stage of the memory has a T
There are many TLs. The TTL threshold voltage vth is generally set to 1.5V. CJi4
1 is the capacitance on the load side of the output buffer circuit.

(D. Problem to be solved by the invention) [Figures 3 and 4
By the way, as mentioned above, the power supply voltage of the output buffer circuit is generally 5■, and as shown in Figure 4, when the output is "high", the output voltage is 5■, and the output is "low". '' means that the output voltage is Ov. and,
The voltage that is half of the power supply voltage Vcc is 2.5
v, and the threshold voltage vth of the subsequent circuit
If the voltage is 2.5V, the time required to change the data from "low" to "high" and vice versa is the same and relatively short. I can do it easily on time.

However, as mentioned above, TTL is often connected as a subsequent circuit of the output buffer circuit;
The threshold voltage vth of L is generally designed to be 1.5V. Therefore, the output of the output buffer circuit is
The time required to switch from "low" to "high" is the time required for the output voltage to change from Ov to 1.5■. On the other hand, the time required for the output of the output buffer circuit to switch from "high" to "low" is the time required for the output voltage to change from 5V to 1.5V. Therefore, even if the time required for the output to switch from "low" to "high" can be shortened, from "high" to "high"
It is difficult to shorten the time required to switch to "LOW".

The readout time of the output buffer circuit is determined not by the shorter length but by the longer length, so
In the end, it is half of the power supply voltage of the memory output buffer circuit.
In the past, if the value of Vth did not match the threshold voltage vth of the subsequent circuit, this was a major cause of lengthening the read time of the output buffer circuit.

Therefore, it has been considered to increase the driving capability of the N-channel MO3FETQn that constitutes the complementary MOS inverter. This is because switching the output from the "high" state to the "low" state means discharging the charge stored in the capacitor C2 on the load side through the N-channel Qn, and the N-channel Qn further discharging the charge. This is because if the reading is performed quickly, the reading time can be shortened. However, doing so creates a very big problem. FIG. 5 is for explaining the problem, and the problem will be explained according to this figure. In the same figure, d is an IC on which a memory is formed.
An output buffer circuit C also exists in a part of l'A I Cd. e is a package that houses the ICd and is made of resin. Incidentally, the power terminal and ground terminal of the ICd are led out of the package e through a connect wire and a lead, and are connected to the anode and cathode of the power source through a socket and wiring on a printed wiring board. Therefore, an inductance L exists between the power supply terminal and ground terminal of ICd and the anode and cathode (genuine ground) of the power supply, although it is small. Ll, Ll is the inductance between the power supply terminal and ground terminal of ICd and the external lead of package e, and L
3. L4 is the inductance between the lead and the anode and cathode (ground) of the power supply, and the sum of Ll and L3, and the sum of Ll and L4 that matters here, is generally 30 to 40n.
It is H. 30 to 40 nH is generally a negligible small value, but the capacitor Cλ of MOSFETQn
If the MOSFETQn is rapidly discharged, a non-negligible back electromotive force is generated, and as a result, the level of the source of the MOSFETQn becomes higher than the ground level by the amount of the back electromotive force. The back electromotive force ΔV is expressed by the following formula.

ΔV-L-N-di/dt In this formula, L: L2+L4, N: the number of ports connected to the output terminal, and here, let's actually apply this formula to the numerical values. Then, take the above average and 35nH,
N can be l, 4, or 8, but since the question is what will happen in the worst case, it is 8, and di is 40mA.
Since this is a common sense value, dt is set to 0.04, and dt is set to 5 ns since the read time of the output buffer circuit is approximately 5 ns. Then, the back electromotive force ΔV reaches about 1v.

In other words, when the load capacitance CIL is discharged at high speed by the MOS FETQ n with increased driving capability, a back electromotive force of 1V is generated due to the stray inductances L2 and L4, and the MOS
The source of FETQn is better than ground! ■ also becomes a high potential. Therefore, the potential of the source of the N-channel MO5FETQn' forming the address buffer circuit receiving the address signal also rises by 1 volt. By the way, the front stage of the memory is also generally a TTL circuit, and the address signal voltage is set to VIL = 0.6V, VIH = S, 4V, and even if the memory is 2.4V, it must be treated as "high". It won't happen. Further, the threshold voltage vth of MOSFETQn' is about 1V. However, if the source of MOSFET Qn' becomes high in IV and a voltage of 2.4V is applied to the gate, the gate
The source-to-source voltage is only 1.4v. That is, v
Only a value that is 0.4 vM higher than th (ffi) is added between the gate and source. Therefore, MOSFETQn
Not only does the driving ability of ' become substantially lower, but it also becomes difficult to maintain a state corresponding to the address signal (currently "high"), resulting in a problem that malfunctions are likely to occur.

Therefore, it is not preferable to try to increase the read speed by increasing the driving capability of the output buffer circuit Qn and making the discharge speed for the load capacitance very high.

Therefore, an object of the present invention is to increase the read speed without particularly increasing the driving ability of the transistors forming the output buffer circuit.

(E. Means for Solving the Problems) In order to solve the above problems, the output buffer circuit of the memory of the present invention attempts to maintain the output of the output buffer circuit at a voltage approximately equal to the threshold voltage of the circuit at the subsequent stage. The present invention is characterized in that it includes a bias circuit that operates the bias circuit, and switching means that operates the bias circuit when an equalization signal is generated.

(F. Effect) According to the output buffer circuit of the memory of the present invention, when the address transitions, the bias circuit is operated by the equalization signal generated accordingly, and the output buffer circuit is activated before the data signal is inputted to the output buffer circuit. The output voltage of the circuit is made approximately equal to the threshold voltage of the subsequent circuit. Then, when the equalization signal disappears,
After the bias circuit becomes inoperable, when a data signal is input to the output buffer circuit, the output voltage changes from a voltage approximately equal to the threshold voltage to a voltage corresponding to the data signal. Therefore, the time required to reach the voltage corresponding to the data signal can be shortened.

(G. Embodiment) [FIGS. 1 and 2] Hereinafter, the output buffer circuit of the memory of the present invention will be explained in detail according to the illustrated embodiment.

FIG. 1 is a circuit diagram showing one embodiment of the output buffer circuit of the present invention. In the figure, 1 is an address buffer that receives an address signal, 2 is an address decoder, 3 is a memory circuit, 4 is a sense amplifier that amplifies the data signal read from the memory circuit 3, and 5 is an address buffer that detects the transition of the address signal. Dish detector 6 is an output buffer circuit according to an embodiment of the present invention. OR is an OR circuit that receives an equalize signal and an output disable signal from the address partition detector 5. INVI is the first inverter and sense amplifier 4
Inverts the output of NOR is a NOR circuit that receives the output of the first inverter INVI and the output of the NOR circuit NOR. I NV2 is the second inverter, OR circuit OR
Inverts the output of NAND is a NAND circuit, and the first
The output of the inverter INV1 and the second inverter INv
It receives the output of 2.

Ql and Ql are MOSFETs that constitute a complementary MOS inverter that forms the main body of the output buffer circuit 6;
Ql is P-channel MOSFET, Q2KN
The channels w' and t are MO5FETs.

MOSFETQl is driven by the output of the NAND circuit NAND, and MOSFETQ2 is driven by the output of the NOR circuit NOR.

Q3 and Q4 are switching MOSFETs, and Q3 is N
Chacine/l/MOSFET, Q4 is P channel MO
This is an SFET that switches the power supply voltage applied to the bias circuit described below.

Q5 and Q6 are MOSFETs that constitute the bias circuit.
Q5 is an N-channel MOSFET, Q6 is a P-channel MOSFET, and their drains and gates are connected to each other, and the gates and drains are also connected, and the connection point is connected to the MOSFETQ.
It is connected to the output terminal of an inverter consisting of I and Ql, and the next stage TTL circuit (not shown) is connected to this output terminal. These MOSFETs Q5 and Q6 are designed so that the level of the output terminal can be made approximately equal to 1.5 V, which is the input threshold voltage of the TTL circuit at the subsequent stage.

The above MO3FETQ3 (i.e., N-channel M for switching connected between MOSFETQ5 and ground)
MOSFET Q4 (that is, the switching P-channel MO5FET connected between MOSFET Q6 and the power supply terminal) is controlled by the output of the second inverter rNV2.

Next, the operation of the output buffer circuit 6 will be explained according to the time chart shown in FIG.

When the equalization signal is not generated, the output of the OR circuit OR is "low", and the output of the second inverter INV2 that inverts it is "high". Therefore, both MOSFETs Q3 and Q4 are kept in the cut-off state, and the bias circuit consisting of MOSFETs Q5 and Q6 can operate, and the bias circuit does not contribute any 399 to the output voltage of the output buffer circuit 6. Also, MOSFETQ
The input terminal of the NAND circuit NAND that drives l on the side opposite to the side that receives the data signal from the sense amplifier 4 is r high.
Then, the input terminal of the NOR circuit NOH that drives MOSFET Q2, which is opposite to the side that receives the data signal from the sense amplifier 4, becomes "low", and both invert the data signal and drive MOSFETs Q1 and Ql. It is.

Therefore, the inverter made up of MOSFETs Ql and Ql is also maintained in a state corresponding to the content of the data signal output from the sense amplifier 4.

By the way, when the address signal changes, the number of sets n5e
After a delay c, an equalize signal is generated from the address partition detector 5 and equalizes the memory circuit 20 bit line and data line. Furthermore, the switching MO3FETs Q3 and Q4 of the output buffer circuit 6 become conductive. This is because the gate of N-channel MO3FETQ3 becomes "high" and the gate of P-channel MO5FETQ4 becomes "r-low."When both Q3 and Q4 are turned on, the bias circuit consisting of MO5FETQ5 and Q6 becomes operational. Become. And, as mentioned above, MOSF
ETQ5 and Q6 are designed (particularly the gate length, gate width, etc.) to keep the level of the output terminal of the output buffer circuit 6 at 1.5v, which is the same level as the input threshold voltage vth of the TTL circuit. Therefore, the output terminal is quickly brought to 1.5V by the action of the bias circuit. At that time, MOSFETQ5 or Q6 fully demonstrates its amplification function and quickly increases the output terminal to 1.5%.
It functions to bring the potential to v. This is because, if there is an address transition when the output of the output buffer circuit 6 is "low", the gates of MOSFETQ5 and Q6 are initially Ov, and in that state, the switching MOSF
Since ETQ3 and Q4 conduct, the voltage between the gate and source of MO3FETQ5 becomes OV and MOSFETQ5 turns off, while the voltage between the gate and source of MOSFETQ6 becomes 5V (actually lower than that), and the MOSFETQ5 becomes OV.
TQ6 is strongly driven.

Therefore, the deeply gate-biased MOS FETQ
6, the load capacitance C1 is charged very quickly.

Then, as the potential of the load capacitor C2 approaches 1°5V, the gate bias for MOSFET Q6 becomes shallower.
The output terminal will settle to 1.5v.

Conversely, if there is an address transition when the output of the output buffer circuit 6 is "high", then MOSFETQ5
, the potential of the gate of Q6 is initially 5V, and in the sono state, M
When OSFETQ3 and Q4 become conductive, MO3FET
Q5 is strongly driven in response to a gate-source voltage of about 5 .mu., and rapidly discharges the load field .pi.CJ2. Then, as the terminal voltage of the load capacitor C2 approaches 1.5V, the gate bias becomes shallower, and when the potential of the output terminal reaches 1.5V, it settles there. In other words, this bias circuit is different from a bias circuit consisting of an ordinary resistance voltage divider circuit, and is constructed with a complementary MOS inverter, so that the terminal voltage is 5.
Load capacitance CI that is v or Ov! , is a MO3FETQ5 or Q whose driving ability is increased by the voltage difference between its terminal voltage and the desired voltage of 1.5V.
6 to discharge or charge, the output terminal can be brought to the desired voltage (1.5V) very quickly.

Specifically, the output voltage of the output buffer circuit 6 can be kept at 1.5V before the equalization signal falls, in other words, during the equalization period.

And complementary MOS that constitutes the bias circuit
Since the input and output of the inverter are short-circuited and the output is negatively fed back to human input, even if there are slight variations in device parameters such as threshold voltage and channel length, the output voltage of this bias circuit settles relatively accurately at its desired voltage (1.5V), and the bias voltage provided by the bias circuit is stable.

Furthermore, during the equalization period, the gate of MOSFETQl becomes "high" and the gate of MOSFETQl becomes "high".
MOSFETs Ql and Q2 both maintain an off state (so-called output disabled state).

When the equalize signal falls, MOSFETQ3, Q
MO5FETs Q5 and Q6 are both turned off, and the bias circuit consisting of the MO5FETs Q5 and Q6 becomes inoperable and cannot have any effect on the potential of the output terminal. Also, MOSF
ETQl and Q2 become in a state corresponding to the new data signal from the sense amplifier 4. As a result, the output voltage begins to change toward the voltage corresponding to the new data signal. The potential of the output terminal at the start point is T
TL input threshold voltage Vth (1,5V
), so if the output becomes "high" shortly after the equalization signal falls, the voltage will be higher than 1.5■, and conversely, if it becomes "low", the voltage will be lower than 1.5■. . That is, as soon as the equalize signal falls, it becomes possible to identify whether it is "high" or "low" in the TTL circuit.

Comparing the conventional case and the circuit shown in Figure 1 in this regard, in the conventional case, after the equalization signal falls, the output voltage of the output buffer circuit changes from OV or 5V to the voltage corresponding to the new data signal. 1.5V when trying to
It takes time t2 to cross (become readable). On the other hand, in the case of the circuit shown in Fig. 1, the state corresponding to the new data signal can be reached immediately after the fall of the equalize signal, so reading can be performed earlier by the time t2 than in the conventional case. . Therefore, speeding up becomes possible.

Note that a state in which data is temporarily corrupted by the equalize signal, that is, a state in which the output voltage of the output buffer circuit 6 does not indicate the memory contents, occurs, but the data hold time (for example, 5 ns after the address transition occurs) The system is set up so that there is no problem even if such a situation occurs from time to time, and furthermore,
Since the equalize signal rises after the data hold time has elapsed, no problem occurs.

In the above embodiment, the output buffer circuit is made of CuO2.
Although the output buffer circuit is configured using an IC, the present invention can also be applied to an output buffer circuit configured using an NMOSIC. Further, the present invention can be applied not only to output buffer circuits of static RAMs but also to output buffer circuits of general memories.

(H, Effects of the Invention) As described above, the output buffer circuit of the memory of the present invention consists of a pair of field effect transistors connected in series, and negative feedback is applied from the output to the input. A bias circuit that attempts to maintain the output terminal of the output buffer circuit at a value approximately equal to the threshold voltage of the subsequent stage of the output buffer circuit, and a bias circuit that is controlled by an equalize signal and allows application of a power supply voltage to the bias circuit when the equalize signal is generated. The invention is characterized in that it includes switching means for operating the bias circuit.

Therefore, according to the output buffer 7 circuit of the memory of the present invention, 1,
When the address transitions, the bias circuit is operated by the equalization signal generated accordingly, and before the data signal is input to the output buffer circuit, the output voltage of the output buffer circuit is set to a value approximately equal to the threshold voltage of the subsequent circuit. be made into When the equalization signal disappears, the bias circuit becomes inoperable, and when the data signal is input to the output buffer circuit, the voltage corresponding to the data signal changes from the threshold voltage to the voltage corresponding to the data signal. The time required can be shortened. Moreover, since the bias circuit is constituted by a field effect transistor which is an amplification element, the output voltage of the output buffer circuit can be quickly adjusted by utilizing the amplification function of the output transistor. Moreover, since the bias circuit is configured to provide negative feedback to the input side of the output of the inverter using field effect transistors, it is possible to stabilize the bias voltage at the desired voltage even if there are slight variations in the device parameters of the field effect transistors. can.

[Brief explanation of the drawing]

1 and 2 are for explaining one embodiment of the output buffer circuit of the memory of the present invention, and FIG. 1 is a circuit diagram;
Fig. 2 is a time chart, Fig. 3 is a circuit diagram showing a conventional example, Fig. 4 is a time chart of the circuit shown in Fig. 3, and Fig. 5 is a MOS FET constituting a conventional output buffer circuit.
FIG. 2 is a circuit diagram illustrating problems that arise when attempting to increase the speed by increasing the driving ability of the device. Explanation of symbols Q3, Q4...Switching means, Q5, Q6...Bias circuit. Applicant Hideaki Ogawa, Patent Attorney for Sony Corporation Figure 4: Miscellaneous

Claims (1)

[Claims] (1) Consisting of a pair of field effect transistors connected in series, negative feedback is applied from the output to the input, and the output terminal of the output buffer circuit is kept at a value approximately equal to the threshold voltage of the latter stage of the output buffer circuit. an output buffer for a memory, comprising: a bias circuit that is controlled by an equalize signal; and switching means that is controlled by an equalize signal and allows the application of a power supply voltage to the bias circuit to operate the bias circuit when the equalize signal is generated. circuit