JPS63217456A - Fast data transfer system - Google Patents

Abstract

PURPOSE:To improve the reliability of the fast data transfer processing by providing a comparator which compares the quantity of data transferred from the transmission side with the number of data received at the reception side and a check timing generating circuit which decides the comparing timing of the comparator at the reception side. CONSTITUTION:A comparator 5 compares the number of data received from the transmission side, i.e., the value of the length information with the writing frequency received from a writing circuit 3 at a prescribed timing point and outputs an error signal when no coincidence is obtained from said comparison. A check timing generating circuit 6 decides the comparing timing of the comparator 5 and receives the write end information signal from the transmission side when the writing action is through with the data transferred every block. Then the circuit 6 outputs a timing signal for comparison. Thus the drop-out of the transferred data is recognized and the reliability is improved with a fast data transfer system.

Description

[Detailed Description of the Invention] [Summary] In a high-speed data transfer method that can process the writing and reading of transferred data independently and in parallel, the value of the data transfer amount sent from the sending side and the amount received by the receiving side are A comparison circuit that compares the number of data and the timing at which the comparison circuit should be compared J1. A check timing generation circuit is provided on the receiving side to check for missing transfer data and improve the reliability of high-speed data transfer processing.

[Industrial application field]

The present invention relates to a high-speed data transfer method, and particularly to a high-speed data transfer method that enables a receiving side to check for missing data during high-speed data transfer processing, thereby improving the reliability of data transfer. .

[Conventional technology]

between the main system and subsystems or subsystems.
Conventionally, in high-speed data transfer between systems, data transfer is performed by synchronizing the clocks of the sending and receiving sides. In other words, transfer data sent from the sending side is written to a specified block of the storage device provided on the receiving side according to the write clock, and transfer data that has already been written to another specified block is written according to the read clock. It is read out according to the These write clocks and read clocks were often synchronized.

Therefore, there is no possibility that the number of data transferred from the transmitting side and the number of transferred data received by the receiving side differ by one, and there is naturally no means for checking the amount of data transferred. Also, it is natural that the reading side overtakes the writing side, or vice versa, the situation where the writing side overtakes the reading side does not occur.

[Problem that the invention seeks to solve]

When performing high-speed data transfer processing that is even faster than the conventional high-speed data transfer method, the write clock that depends on the sending side and the continuous clock that depends on the receiving side are different and are carried out asynchronously. and the clock is made asynchronous.

Even if transferred data is missing, the receiving side cannot confirm the missing data, and because it is asynchronous, there is a problem with the reliability of data transfer.

Therefore, when there is a difference in the amount of data transferred between the transmitting side and the receiving side, an error signal is generated.

The purpose is to provide a high-speed data transfer method that improves the reliability of high-speed data transfer.

[Means for solving problems]

FIG. 1 shows a conceptual configuration diagram of a high-speed data transfer system according to the present invention, where 1 is a receiving device, 2 is a storage device, and 5 is a receiving device.
6 represents a comparison circuit, 6 represents a check timing generation circuit, 4 represents a read address circuit, and 3 represents a write address circuit.

The storage device 2 is divided into n blocks, and transfer data sent from the transmitting side, that is, write data, is written on the address of the block designated by the write address circuit 3. . Furthermore, the data written in the blocks in the storage device 2 is read out independently, regardless of the write processing described above. In other words, write processing and read processing of the storage device 2 are performed independently and in parallel, allowing high-speed data transfer.

Write address circuit 3 sends a block select signal specifying a block within storage device 2 and its address to storage device 2 . The addresses are updated in sequence according to the transmitter clock (CLD).

Further, the write address circuit 3 calculates the number of times the address is updated each time the address is updated according to the sending clock.

That is, the address written in the block of the storage device 2 is sent to the comparison circuit 5.

The read address circuit 4 sends to the memory device 2 a block select signal specifying a block to be read from the memory device 2 and its address. The addresses are updated in sequence according to the receiving side clock (CL++).

The comparison circuit 5 compares the number of data transfers sent from the transmitting side, that is, the value of the length information, and the number of writes sent from the write address circuit 3 at a predetermined timing, and outputs an error signal when they do not match. It is designed to output .

The check timing generation circuit 6 is a circuit that determines the timing at which the comparison circuit 5 should compare, and when the writing of transfer data for each block is completed, it receives a write completion notification signal sent from the transmitting side, and The timing signal to be compared is output.

[Effect]

The writing and successive output of transfer data to the storage device 2 of the receiving device 1 are performed in independent parallel processing as in the first order.

In the write process, transfer data sent from the transmitting side is sequentially written onto the address of the block specified by the write address circuit 3 and updated by the write clock.

As this write clock, the transmission side clock used for data transfer is used as is.

On the other hand, in the continuation process, the data written on the address of the block specified by the continuation address circuit 4 and updated by the read clock corresponds to the write clock that depends on the sending clock of the write process. are unrelated and are read out in order.

The value of the data transfer amount, that is, the value of the length information, is sent to the comparator circuit 5 from the transmitting side during data transfer, and is set as a reference value, and is updated every time the address is updated in accordance with the transmitting side clock. To.

That is, each time transfer data from the transmitting side is written on the address of a designated block, the value of the number of writes is sent from the write address circuit 3.

When writing of the transfer data for the block is completed, a write completion notification signal is sent from the sending side to the receiving device 1 on the receiving side. Upon receiving the write completion notification signal, the check timing generation circuit 6 immediately outputs a timing signal to the comparison circuit 5. As a result, the comparison circuit 5 compares the value of the length information as a reference value from the sending side and the value of the number of writes sent from the write address circuit 3, and when the two values do not match.

That is, only when the value of the amount of data transferred from the transmitting side and the number of data received by the receiving device 1 on the receiving side do not match, an error signal is output. Based on the presence or absence of the error signal, it can be determined whether the data transfer is being performed correctly.

An embodiment of the present invention will be described below with reference to FIG.

〔Example〕

FIG. 2 shows the configuration of an embodiment of the high-speed data transfer system according to the present invention.

In FIG. 2, numerals 1 and 5 correspond to those in FIG. 1, 7 is a storage device, 7-1 is a #1 block, 7-2 is a #2 block, and 8.9 is a decoder.

10 is a write address counter, 11 is a +1 circuit,
12 is a read address counter, 13°, 14 is a buffer register, 15.16 is a latch circuit, 17.18
19 represents a rising edge detection circuit, 19 represents an OR circuit, and 20.21 represents a synchronization circuit.

The storage device 7 writes the transfer data from the sending side.

It is divided into two blocks: #1 block 7-1 and #2 block 7-2. Therefore, the write address
# of the storage device 7 is determined by the most significant 1 bit of the counter 10.
1 block 7-1 or #2 block 7-2 is specified,
It is configured to generate an address within the program specified by the lower bits excluding the most significant bit. Note that the method of specifying #1 block 7-1 or #2 block 7-2 is the same for the read address counter 12, but its illustration is omitted in FIG. Now 2 For example, write the transfer data sent from the sending side to #1 block 7-1 of storage device 7, and write the transfer data sent from the sending side to #2 block 7-1 of storage device 7.
This will be explained as a mode for reading data already written from 2 onwards.

When transferring data from the sending side to the receiving device 1 on the receiving side,
The value of the data transfer amount is sent from the transmitting side to the receiving device l as length information. The value of this length information is set in the comparison circuit 5 as a reference value.

The transfer data sent from the transmitting side using the transmitting side clock is transferred via the buffer register 13 to the #l block 7-1 obtained by decoding the contents of the write address counter 10 at that time by the decoder 8. Written immediately on the address. Thereafter, the write address counter 10 assumes that the transfer data sent from the transmitting side has been received and sends the write number, that is, the count value (
At first, "1") is sent. Then, a signal is sent to the +1 circuit 11, and upon receiving the signal from the +1 circuit 11, the write address counter 10 increments by current.

Therefore, the address of #1 block 7-1 is updated.

When transfer data is sent from the transmitting side at the next transmitting side clock, the transfer data is immediately written on the updated address of #1 block 7-1. After the write address counter 10 sends the value of the number of writes "2" to the comparator circuit 5, it sends a signal to the +1 circuit 11. Therefore, the write address counter 10 counts up and updates the address of the #1 block 7-1. Similarly, each time transfer data is written to #1 block 7-1, the value of the number of writes sent to comparison circuit 5 also increases.

On the other hand, read address counter 12 and decoder 9
The successive address circuit consisting of the receiving side clock (CL++
), data is read from the designated address of #2 block 7-2.

Store in buffer register 14.

When the data transfer from the transmitting side to the receiving device 1 on the receiving side is completed, a #1 block write completion notification signal is sent from the transmitting side to the launch circuit 15. The rising edge detection circuit 17 detects the presence or absence of the #l block write end notification signal which is applied to the latch circuit 15. When the #1 block write completion notification signal is latched into the latch circuit 15, the rising edge detection circuit 17 outputs a timing signal to be compared to the comparison circuit 5 via the OR circuit 19. As a result, the comparator circuit 5 compares the reference value set in the comparator circuit 5, that is, the value of the length information to be transferred from the transmitting side, and #
The number of transfer data actually written in one block 7-1 is compared with the number of transfer data actually written in one block 7-1, and if the two values are different, an error signal is output as it is assumed that data loss has occurred during data transfer. This makes it possible to check whether data transfer is being performed as desired.

Then, the #1 block write end notification signal latched by the launch circuit 15 is synchronized with the receiving side clock by the synchronization circuit 20, and the #1 block write end notification signal synchronized with the unique clock of the receiving device 1 side is synchronized. It is output as a signal.

The above explanation is exactly the same when writing transfer data from the transmitting side to #2 block 7-2.

When the #2 block write end notification signal is latched in the latch circuit 16, the rising edge detection circuit 18 outputs the OR circuit 19.
A timing signal to be compared is outputted to the comparator circuit 5 via. Further, the synchronization circuit 21 outputs a #2 block write end notification synchronization signal synchronized with the clock specific to one example of the receiving device.

The data written in #1 block 7-1 is then read out regardless of the transmitter clock.

When the number of divided blocks of the storage device 7 is one, for example four, the two most significant bits of the write address counter 10 are assigned to the block select signal. Then, each time the write process to each block is completed, a block write completion notification signal is received.

By having a configuration that generates a timing signal for operating the comparator circuit 5, data loss during data transfer can be checked.

〔Effect of the invention〕

As explained above, according to the present invention, in a high-speed data transfer method that performs high-speed data transfer by asynchronously clocking the clocks on the sending and receiving sides of data transfer, the sending and receiving sides Since an error signal is generated when transfer data is lost between the two, it becomes possible to recognize the loss of transfer data, and the reliability of high-speed data transfer can be improved.

[Brief explanation of the drawing]

FIG. 1 is a conceptual block diagram of a high-speed data transfer system according to the present invention, and FIG. 2 shows the structure of an embodiment of the high-speed data transfer system according to the present invention. In the figure, 1 is a receiving device, 2 is a storage device, 3 is a write address circuit, 4 is a read address circuit, 5 is a comparison circuit, and 6 is a check timing generation circuit. 7 is a storage device, 7-1 is a #1 block, 7-2 is a #2 block, 8 and 9 are decoders, and 10 is a write address.
Counter, 11 is +1 circuit, 12 is read address/
Counter, 13.14 is Vanofa register, 15.1
Reference numeral 6 represents a launch circuit, 17° and 18 represent a rising edge detection circuit, 19 represents an OR circuit, and 20° and 21 represent a synchronization circuit.

Claims (1)

[Claims] A high-speed data transfer method that divides a storage device (2) that stores transfer data sent from a sending side into a plurality of blocks, and processes writing and reading of the data independently and in parallel. At the receiving side, a comparison circuit (5) that compares the value of the data transfer amount sent from the transmitting side and the value of the number of writes of the data written to the specified block of the storage device (2) is installed on the receiving side. and a check timing generation circuit (6) which receives a write end notification signal for the data for each block from the transmitting side and determines the timing to be compared by the comparison circuit (5) based on the write end notification signal.
), and detects a match between the amount of data transferred from the transmitting side and the number of data received at the receiving side.