JPS63215214A - Bit timing comparator - Google Patents

Abstract

PURPOSE:To attain the pull in at a correct bit timing by providing a bit comparison means and a deciding means deciding the coincidence/dissidence of the bit timing of 1st and 2nd data strings at a period of one over an integral number of the frame of the data strings. CONSTITUTION:Suppose that a bit timing difference is caused in the input data strings 11, 12 at a moment, the bit timing difference is detected by a bit comparator 1 and a dissidence detection pulse is outputted to a bit selection circuit 2 as a bit comparison signal 13. The bit selection circuit 2 samples the data strings at a period of one over an integral number of the frame of the input data strings. Then a dissidence deciding circuit 6 applies the decision of coincidence/dissidence from the result of bit comparison to be sampled. As a result, the decision such that the bit timing of the data strings is coincident regardless of being deviated with each other due to light load of the input data strings 11, 12, is reduced and the synchronization is taken in a correct bit timing.

Description

TECHNICAL FIELD The present invention relates to a bit timing comparison circuit, and more particularly to a bit timing comparison circuit that detects bit timing when the same data is transmitted through two routes and synchronous switching is performed.

Conventionally, this type of bit timing comparison circuit compares the bits of data, sends the comparison result as is to the judgment circuit without sampling, and judges whether the bit timing matches or mismatches for each bit. Ta.

In such conventional bit timing comparison circuits, the comparison detection result is not sampled and the match or mismatch is determined for each bit. Therefore, when the transmission information port is reduced and the load signal is light, there is less mismatch information, and the data There is a drawback that it is determined that the bit timings of the columns match even though they are shifted from each other.

The present invention was made in order to eliminate the above-mentioned drawbacks of the conventional method.It is assumed that the input data string is in a light load state and the bit timings of the data strings match when they are shifted from each other. An object of the present invention is to provide a bit timing comparison circuit that can reduce erroneous judgments and perform synchronization pull-in at correct bit timing.

The bit timing comparison circuit according to the present invention includes bit comparison means for comparing bits of first and second data strings whose mutual bit timings are uncertain; The present invention is characterized in that it is provided with a determining means for determining whether or not the bit timings of the first and second data strings match each other at a cycle that is an integer fraction of the frame of these data strings.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, input data strings 11 and 12 are data strings that have been transmitted through extremely different transmission routes, and the mutual bit timing of both data strings is undefined due to the transmission characteristics of these transmission routes. shall be. This embodiment includes a bit comparison circuit 1 that performs bit comparison of these two input data strings 11 and 12, a bit selection circuit 2 that samples and outputs the bit comparison signal 13 from the bit comparison circuit 1, and a bit selection circuit 2 that samples and outputs the bit comparison signal 13 from the bit comparison circuit 1. Bit selection signal 16 from selection circuit 2
and a mismatch judgment circuit 6 which judges whether or not the bit timings match based on the inputs of the bit timings.

Further, the bit selection circuit 2 includes a mismatch bit detection section 3, a frequency division circuit 4 that divides the frequency of the clock 14 into 1/8, and an AND gate 5.

The frame period N of input data strings 11 and 12 is 1536
When the mismatch bit detection section 3 detects a mismatch in bit timing, the bit selection circuit 2 samples the bit comparison signal 13 for every 8 bits, and sends this to the mismatch determination circuit 6 as the bit selection signal 16. Send as.

The mismatch determination circuit 6 uses this bit selection signal 16 to determine whether or not the bit timings match, and sends out the determination result as a determination signal 17.

FIG. 2 is a time chart of one embodiment of the present invention. The figure shows the case where the input data strings 11 and 12 are in an unloaded state with only frame bits. The operation of one embodiment of the present invention will be explained using FIG. 1 and FIG. 2.

If a bit timing difference as shown in FIG. 2 occurs at a certain moment in the input data string 11.12, this bit timing difference is detected by the bit comparison circuit 1, and the mismatch detection pulse is used as the bit comparison signal 13 to select the bit. It is output to circuit 2.

This mismatch detection pulse causes the bit selection circuit 2 to start operating.

In other words, when the mismatch bit detection section 3 inputs this mismatch detection pulse, it drives the frequency divider circuit 4, and the frequency divider circuit 4 outputs an output signal 15 to the AND gate 5 every eight clocks of the clock pulse 14. Outputs “1” to . In the AND gate 5, the bit comparison signal 13 from the bit comparison circuit 1
and the output signal @15 from the frequency divider circuit 4 is performed, and the bit comparison signal 13 is sent to the mismatch determination circuit 6 every time the output signal 15 from the frequency divider circuit 4 becomes "1". The bit comparison signal 13 is sent to the mismatch determination circuit 6 one bit every eight bits.

Since the bit selection circuit 2 is not yet in operation before this mismatch detection pulse is output, the comparison result of the bit comparison circuit 1 is sent as is to the mismatch judgment circuit 6, where it is judged whether there is a match or mismatch. 17 is output. In the bit comparison circuit 1, when the input data strings 11 and 12 are in a light load state, especially in a no-load state, all data bits are "0".
Therefore, when the frame bits of the input data string 11 are input (point A of the sampling timing in FIG. 2), a mismatch detection pulse is output.

When bit selection circuit 2 starts operating, 1 bit is selected every 8 bits.
The sample is sampled bit by bit and the bit comparison result is output, but since all the data bits are rOJ, a coincidence detection pulse is output.

However, at the 192nd sampling, the frame bits of the input data string 11 are again input to the bit comparison circuit 1 (point N of the sampling timing in FIG. 2), so a mismatch detection pulse is output.

In the mismatch determination circuit 6, the number of match detection pulses and the number of mismatch detection pulses within a predetermined time are counted to protect synchronization.

If such sampling is performed, the mismatch detection accuracy will be 1 bit out of 192 bits in a no-load state, but if sampling is not performed, the mismatch detection accuracy will be only 2 bits out of 1536 bits.

In other words, when determining timing mismatch based on mismatch detection information of 1 bit out of 192 bits, the conventional 1
The synchronization protection characteristics against bit errors occurring in the transmission path are improved compared to the case where timing mismatch is determined based on the mismatch detection information of 2 bits out of 536 bits.

The amount of improvement depends on the contents of the mismatch determination circuit 6 that determines timing mismatch, but in this embodiment, the improvement is approximately four times.

In this way, the results of the bit comparison of the input data strings 11 and 12 performed by the bit comparison circuit 1 are sampled in the bit selection circuit 2 at a cycle that is an integer fraction of the frame of these input data strings. The input data string 11.1 is determined by the mismatch judgment circuit 6 based on the result of the sampled bit comparison.
2 is in a light load state and the bit timings of the data strings are shifted from each other, it is possible to reduce the erroneous determination that they match, and to perform synchronization at the correct bit timing.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, as described above, in accordance with the bit comparison between the first and second data streams, the coincidence and mismatch in bit timing of the first and second data streams is determined for an integer number of frames. By making the determination every cycle of 1,
When the first and second data strings are in a light load state and the bit timings of the first and second data strings are different from each other, it reduces the false judgment that they match, and synchronizes with the correct bit timing. It has the effect of being able to do the following.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a time chart of one embodiment of the present invention. Explanation of symbols of main parts 1...Bit comparison circuit 2...Bit selection circuit 3...Unmatched bit detection unit 4...Broadcast circuit 6... ...Discrepancy judgment circuit

Claims (1)

[Claims] Bit comparing means for comparing bits of first and second data strings whose bit timings are uncertain; and a bit timing mismatch between the first and second data strings according to an output from the bit comparing means. A bit timing comparison circuit characterized in that it is provided with a determination means for determining the period of one frame of the data string at a cycle that is an integer fraction of the frame of the data string.