JPS63212240A - Information transmission system for line circuit system - Google Patents

Abstract

PURPOSE:To contrive the improvement of the transmission efficiency by providing a time designation path designating the use of time of a data line to a data line by an information converting circuit at every line circuit. CONSTITUTION:Plural line circuits 20-22 accommodating and connecting communication lines and transmitting/receiving transmission information with the central processing unit 10 of an exchange, and an information conversion circuit 11 provided between the central processing unit 10 and the line circuits 20-22, converting the transmission information into serial information at the central processing unit 10, converting it into the parallel information at the line circuits 20-22 and transmitting/receiving the information individually to/from the plural line circuits are provided. Then the line circuit and the transmission information transmission/reception time with the central processing unit are designated individually by using the information of the time designation line 43 connecting the information conversion circuit 11 and the line circuits 20-22. Thus, the destination address from the transmission information on the data line 42 is not required and one transmission information block is activated for the plural line circuits as well by the time designation line 43.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention provides a system in which a central processing unit of an exchange is connected to a subscriber terminal line,
The present invention relates to an information transmission method for a line circuit system that accommodates and connects trunk lines and the like and exchanges data information with a line circuit that is connected to a switch.

[Conventional technology]

In the conventional line circuit information transmission system, an information conversion circuit that mutually converts parallel information input/output by a central processing unit and serial information input/output by multiple line circuits is connected to an information transmission path between the line circuits. The circuit has a clock path for transmitting clock pulses and a bidirectional transmission path for transmitting data information, and a circuit connected to the data path transmits the transmitted information on the data path and the called party address accompanying the transmitted information. It is identified and taken in as received information, and on the other hand, the called party's address and calling party's address are attached to an empty space and sent as transmitted information.

FIG. 7 is a block diagram showing an example of a conventional system, and FIG. 8 is a configuration diagram showing an example of transmission information transmitted on the data path of FIG.

In FIG. 7, the central processing unit 1) 0 of the exchange is connected via an information conversion circuit 91ft to a line circuit 92 that accommodates and connects communication lines 30, for example, terminal lines for all terminal terminations, relay lines connecting to other exchanges, etc. do. Central processing unit 10
Parallel information is transmitted between the information conversion circuit 91 and the information conversion circuit 91.
Information transmission path 9 between information conversion circuit 91 and line circuit 92
4, serial information is transmitted. That is, the information conversion circuit 91 executes serial-to-parallel conversion of information.

The information transmission path 94 has a clock path 41 and a data path 42, the clock path 41 has a clock pulse at a terminal with a symbol C, and the data path 42 has a terminal that encodes transmission information, and all connected circuits (information conversion circuit 91 and line circuit 92) at the same time. Although FIG. 7 shows the clock pulses being supplied from the information conversion circuit 91 to all of the line circuits 92, a system in which the clock pulses are supplied from a clock circuit (not shown) to the information conversion circuits may also be used. Transmission information on the data path 42 can also be transmitted from the information conversion circuit 91 and the line circuit 92.

As shown in FIG. 8, the transmission information on data path 42 is transmitted with the called party address and the calling party address in place. Therefore, each circuit, such as line circuit 92, constantly intercepts the called party address on data path 42 and captures all information transmitted with the called party address when it matches its own address.

For example, the transmission information outputted by the information conversion circuit 91 includes (b)
There is no control information for relays, lamps, etc. in the line circuit 92, and scan result information is included in the input transmission information.

[Problem that the invention seeks to solve]

As mentioned above, in the conventional line circuit-based information transmission system, the information transmission path for transmitting serial information between the central processing unit and the line circuit is composed of one data path, and the transmitted information is the called party's address. Since the system is configured so that the sender and receiver can be confirmed by accompanying the caller's address, when sending the same information to multiple recipients, or when transmitting information addressed to one recipient address, has important transmission of information,
Even if there are multiple addresses, there is a problem in that the transmission time for the number of called party addresses to be sent is lost, and the transmission efficiency of information that requires transmission time for the number of called party addresses for the number of transmitted information is reduced for short multiple pieces of information. .

[Means for solving problems]

The line circuit system information transmission system according to the present invention includes a plurality of line circuits that accommodate and connect communication lines and transmit and receive transmission information to and from a central processing unit of an exchange, and a plurality of line circuits that are provided between the central processing unit and the line circuit. and an information conversion circuit that converts the transmitted information into serial information in the central processing unit 1 and converts it into parallel information on the line circuit side to send and receive information individually to the plurality of line circuits, The present invention is characterized in that the transmission information transmission/reception timing between each of the line circuits and the central processing unit is individually specified by information on a timing specification path connecting the information conversion circuit and each line circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

1 is a first diagram showing an embodiment of the present invention; FIG. In the figure, the central processing unit IO of the exchange is coupled to line circuits 20 to 22 via an information conversion circuit 1ift. A parallel information transmission system is used between the central processing unit 10 and the information conversion circuit 1), and the information conversion circuit 1) and the line circuit 20
22 is a transmission method using serial information. This serial information transmission path 40 is a clock path 41. It is formed by a data path 42 and a timing path 43.

The central processing unit IO is a control device that plays the central role of the exchange, and is responsible for information conversion. 1) forms a connection control unit that mutually converts serial information input/output by the line circuits 20 to 22 and parallel information input/output by the central processing unit IO. The line circuits 20 to 22 are accommodated and connected to a communication line 30, for example, a terminal line where a terminal is terminated and a relay line IB connected to another exchange, and the information conversion circuit 1) is connected to an information transmission line 40.
As clock road 41. Data path 42 and timing path 43
connected to.

The clock circuit 41 connects the information conversion circuit 1) to all circuits 20 to 2.
2 via terminal C, which ensures that the digital code transmitted on data path 42 is received and transmitted. The data path 42 is the information conversion circuit 1
) and all the line circuits 20 to 22 are connected through a single transmission path through terminals, and the output information from one circuit is a bidirectional path that can be received by all the other circuits. Scheduled route 4
3 are terminals 80, sl, 82, and 82 of the information conversion circuit 1).
-m-- From each line circuit 20, 21, 22, --
- the information conversion circuit 1) is connected to each of the line circuits 20 to 2 using the timing designation path 43;
2 can be controlled.

FIG. 2 is a time chart showing an example of information transmission on the information transmission path of FIG. With reference to FIG. 2 and FIG. 1, transmission and reception of transmission information on a data path using a time designated path will be explained.

Clock circuit 41 connects terminal C to a clock circuit (not shown)
provides clock pulses at a rate that is an integer multiple of the digital symbol rate transmitted on data path 42 from n. In FIG. 1, the clock circuit is built into the information conversion circuit 1), and in FIG.

In FIG. 2, one piece of transmission information is formed by the 4 bits initially associated with the code rlJ on the data path 42 and the 8 bits of data information following the 2 bits of no-signal time. The initial code "l" indicates, for example, that the information conversion circuit 1) is the central processing unit 1.
This means output information received from 0 and outputted, and a signal specifying the reception destination of the transmission information is sent from the information conversion circuit 1) to the terminal S1 of the timing specification path 43.

In the figure, there is a signal only at terminal S1, so terminal S
The line circuit 21 to which 1 is connected picks up the signal from the terminal S,
The information being transmitted is taken from the data path 42 via the terminal. Although transmission signals arrive at the terminals of the line circuits 20 and 22, they do not operate because there is no signal from the terminals SO and S2 of the information conversion circuit 1) at the terminal S.

FIG. 3 is a diagram showing an example of transmitted information. The transmission information consists of 4-bit and 8-bit niblocks,
The 4 bits are formed by 1 and 1 bits in the mode section and 3 bits in the line circuit internal address section.

In the mode section, the code rlJ indicates the output mode from the central processing unit, and the code "0" indicates the input mode to the central processing unit. The intra-line circuit address section is, for example, position information of a relay or a lamp. The 8 bits of the second block are the data information section, which in the output mode is information received to the line circuit, and in the input mode is information transmitted from the line circuit. In the output mode shown in FIG. 2, for example, when the address in the line circuit is alarm lamp information and the data information forms a lamp blinking code, one line circuit 21 specified by the terminal 81 (see FIG. 1)
receives the transmitted information and flashes the alarm lamp.

FIG. 4 is a time chart showing an example of broadcasting. The mode section near the terminal is the output mode. Terminal 5o-81-8
Since the line circuit connected to 3 receives the designation signal via the timing designation path, it receives and takes in the information in the data information section according to the designation of the output mode. Therefore, a broadcast function is established in which the same information is transmitted except for the line circuit connected to the terminal S2.

FIG. 5 is a time chart showing an example of the input mode. Of the terminals δ0-83, only terminal S2 has a timing designation signal, so after receiving the 4-bit signal of the first block, the line circuit connected to terminal S2 switches to transmission and sends 8-bit data information to the data path. Send. For example, when a scanning position is specified in the line circuit address section, the scanning result is sent out as data information.

FIG. 6 is a time chart showing another example in the input mode. The information transmitted at the terminal is the input mode of code O in the mode section. A signal specifying 4 bits of the first block is transmitted to all terminals SO to S7, and 8 bits of the second block are 1 bits.

The data is assigned to each of terminals 5o-87 and designated. Therefore, when scanning within a line circuit requires only one bit of result data, data transmission can be performed with one block of transmission information.

In the above embodiment, the transmission information is 4 bits in the first block.

Although the present invention has been illustrated and described as having 8 bits for the first and second blocks and 2 bits between blocks, the structure of the number of bits and the structure of the blocks are not limited to the above description. Furthermore, although the information structure has been illustrated and explained as input/output mode, address, and data information, this block structure and order do not limit the present invention.

〔Effect of the invention〕

As explained above, according to the present invention, an information conversion circuit that mutually converts input/output parallel information of a central processing unit and input/output serial information of a line circuit is connected to a data path for one data path for transmitting information. By configuring each line circuit to have a timing designation path that specifies when to use the data, a destination address is not required from the transmission information on the data path, and the timing designation path allows one transmission information program to be used in multiple ways. The effect of improving processing efficiency can be obtained by being able to be used for other line circuits.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a time chart showing an example of code transmission on the information transmission path of Fig. 1, and Fig. 3 is an example of the format of one transmission information. 4 to 6 are time charts showing an example of the use of the time designated route, FIG. 7 is a block diagram showing an example of a conventional example, and FIG. 8 is a configuration showing an example of a conventional transmission information format. It is a diagram. 10・°°“°゛Central processing unit, 1)...Information conversion circuit, 20.21.22...Line circuit, 3
0...Communication line, 40...Information transmission path, 41...Clock path, 42...Data path, 43...Time specification Road. Fig. 1 Fig. 2 Fig. 3 L from the center edge: Voca mode To the line circuit f) 1st grade θ; Input L
-do 1 circuit power 1 u/), 1. *Board -1,
Figure 4 Muscle Figure 3 Shoulder-to-shoulder diagram

Claims (2)

[Claims] (1) A plurality of line circuits that accommodate and connect communication lines and send and receive transmission information to and from a central processing unit of an exchange; an information conversion circuit that converts the information into serial information on the side and converts it into parallel information on the line circuit side to send and receive information individually to the plurality of line circuits, and the information conversion circuit and each line circuit are connected to each other. A method for transmitting information in a line circuit system, characterized in that a timing for transmitting and receiving transmission information between each of the line circuits and the central processing unit is individually specified based on information on a connection timing specifying path. (2) Information sent and received between the central processing unit and the line circuit includes a mode section for identifying input information/output information to the central processing unit, and an address within the line circuit. An information transmission system for a line circuit system according to claim 1, characterized in that the method has an address field for designation and a data information field consisting of multiple bits of data information.