JPS63211796A - Manufacture of multilayer laminated board - Google Patents
Manufacture of multilayer laminated boardInfo
- Publication number
- JPS63211796A JPS63211796A JP4480187A JP4480187A JPS63211796A JP S63211796 A JPS63211796 A JP S63211796A JP 4480187 A JP4480187 A JP 4480187A JP 4480187 A JP4480187 A JP 4480187A JP S63211796 A JPS63211796 A JP S63211796A
- Authority
- JP
- Japan
- Prior art keywords
- copper foil
- weight
- parts
- double
- manufacture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 14
- 239000011889 copper foil Substances 0.000 claims description 14
- 238000010438 heat treatment Methods 0.000 claims description 8
- 239000003822 epoxy resin Substances 0.000 claims description 6
- 229920000647 polyepoxide Polymers 0.000 claims description 6
- 239000003795 chemical substances by application Substances 0.000 claims description 5
- 239000000203 mixture Substances 0.000 claims description 5
- 239000003094 microcapsule Substances 0.000 claims description 4
- 238000002844 melting Methods 0.000 claims 1
- 230000008018 melting Effects 0.000 claims 1
- 238000000034 method Methods 0.000 description 5
- RPNUMPOLZDHAAY-UHFFFAOYSA-N Diethylenetriamine Chemical compound NCCNCCN RPNUMPOLZDHAAY-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- QGBSISYHAICWAH-UHFFFAOYSA-N dicyandiamide Chemical compound NC(N)=NC#N QGBSISYHAICWAH-UHFFFAOYSA-N 0.000 description 2
- IMNIMPAHZVJRPE-UHFFFAOYSA-N triethylenediamine Chemical compound C1CN2CCN1CC2 IMNIMPAHZVJRPE-UHFFFAOYSA-N 0.000 description 2
- ULKLGIFJWFIQFF-UHFFFAOYSA-N 5K8XI641G3 Chemical compound CCC1=NC=C(C)N1 ULKLGIFJWFIQFF-UHFFFAOYSA-N 0.000 description 1
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 description 1
- 239000004698 Polyethylene Substances 0.000 description 1
- 239000004793 Polystyrene Substances 0.000 description 1
- 239000002775 capsule Substances 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000009472 formulation Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011256 inorganic filler Substances 0.000 description 1
- 229910003475 inorganic filler Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- -1 polyethylene Polymers 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 229920002223 polystyrene Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、プリント回路が複数層に構成される多層積層
板の製造法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a multilayer laminate having a printed circuit in a plurality of layers.
従来の技術
従来、多層積層板は、両面銅張り積層板を所定の回路に
エツチングした両面プリント配線板を内層回路とし、そ
の回路表面に接着性を高めるだめの黒化処理を施した後
、数枚のプリプレグを介して表面に銅箔を加熱加圧接着
し、一体化したものである。Conventional technology Conventionally, multilayer laminates have been manufactured using a double-sided printed wiring board made by etching a double-sided copper-clad laminate with a predetermined circuit. Copper foil is bonded under heat and pressure to the surface of two sheets of prepreg to form an integrated structure.
発明が解決しようとする問題点
しかし、従来の製造方法においては、表面銅箔の接着の
ためにプリプレグを使用するため、また内層回路表面黒
化処理等の必要から、製造工程が複雑であり、また、表
面銅箔を一体化する工程で積層板にボイドが残らないよ
うにするために、高圧で加圧する必要があり、設備が大
きなものとなっている。Problems to be Solved by the Invention However, in the conventional manufacturing method, the manufacturing process is complicated due to the use of prepreg for bonding the surface copper foil and the need for blackening treatment on the surface of the inner layer circuit. Furthermore, in order to prevent voids from remaining in the laminate during the process of integrating the surface copper foil, it is necessary to apply high pressure, which requires large equipment.
本発明は、ボイドのない多層積層板を、簡単な工程で製
造することを目的とするものである。The object of the present invention is to manufacture a void-free multilayer laminate using a simple process.
問題点を解決するための手段
上記目的を達成するために、本発明は、回路が両面粗化
銅箔よりなる両面プリント配線板を内層回路とする。そ
の表面に、マイクロカプセル化した常温硬化剤を無溶剤
エポキシ樹脂組成物１００重量部に対して１〜２０重量
部配合したものを塗布し、一次加熱によりマイクロカプ
セルを熱溶融させる。その後二次加熱と加圧により前記
塗布面に銅箔を接着一体化することを特徴とするもので
ある。Means for Solving the Problems In order to achieve the above object, the present invention uses a double-sided printed wiring board whose circuits are made of double-sided roughened copper foil as an inner layer circuit. A mixture of 1 to 20 parts by weight of a microcapsulated room-temperature curing agent based on 100 parts by weight of a solvent-free epoxy resin composition is applied to the surface, and the microcapsules are thermally melted by primary heating. The method is characterized in that the copper foil is then bonded and integrated with the coated surface by secondary heating and pressurization.
作用
本発明に使用する常温硬化剤は、ジエチレントリアミン
、トリエチレンジアミン、エチレンジアミンなどである
。これらを封入してマイクロカプセルを形成する材料は
、ポリスチレン、ポリエチレンなどであり、一次加熱の
ときにカプセル壁溶融して、常温硬化剤が露出しエポキ
シ樹脂に作用しセミキュアを行なう。これによって、均
一な絶縁膜が形成され、次の二次加熱と加圧により銅箔
が強固に接着される。Function: The room temperature curing agent used in the present invention includes diethylenetriamine, triethylenediamine, ethylenediamine, and the like. The material used to encapsulate these to form microcapsules is polystyrene, polyethylene, etc., and the capsule wall melts during primary heating, exposing the room-temperature curing agent and acting on the epoxy resin to perform semi-curing. As a result, a uniform insulating film is formed, and the copper foil is firmly bonded by the subsequent secondary heating and pressurization.
常温硬化剤の配合量は、１重量部未満であると、銅箔の
接着時に絶縁膜の均一性が期待できず、内層回路と表面
の回路間で短絡を生じやすい。また、２０重量部を越え
ると、硬化反応が急激となり、ボイドが発生する。If the amount of the room temperature curing agent is less than 1 part by weight, uniformity of the insulating film cannot be expected when adhering the copper foil, and short circuits are likely to occur between the inner layer circuit and the surface circuit. Moreover, if it exceeds 20 parts by weight, the curing reaction becomes rapid and voids occur.
実施例
本発明で使用する無溶剤エポキシ樹脂は、通常の液状エ
ポキシ、固型エポキシを使用すればよいが、塗布すると
きに粘度が１０〜６００ポイズであることが望ましい。Examples The solvent-free epoxy resin used in the present invention may be an ordinary liquid epoxy or solid epoxy, but it is desirable that the viscosity at the time of coating is 10 to 600 poise.
塗布時の粘度が低いと均一な絶縁層が得られず、粘度が
高いとボイドが発生しやすい。無溶剤エポキシ樹脂には
、無機充填剤を配合してもよい。If the viscosity during coating is low, a uniform insulating layer cannot be obtained, and if the viscosity is high, voids are likely to occur. An inorganic filler may be added to the solvent-free epoxy resin.
ピコ−） １００１、シェル化学製）１００重量部に、
ジシアンジアミド４重ｆｉ部、２−−ｒ−チル−４−メ
チルイミダゾール０．６重量部、マイクロカプセル化し
たジエチレントリアミンを第１表に示す量で配合し、９
０℃で５分間撹拌した。回路が両面粗化銅箔よりなる両
面プリント配線板の両表面に、前記配合物を０．２１の
厚さで塗布した。Pico) 1001, manufactured by Shell Chemical) 100 parts by weight,
Four parts of dicyandiamide, 0.6 parts by weight of 2-r-thyl-4-methylimidazole, and microencapsulated diethylenetriamine were blended in the amounts shown in Table 1, and 9
Stirred at 0°C for 5 minutes. The above formulation was applied to a thickness of 0.21 on both surfaces of a double-sided printed wiring board whose circuitry was made of double-sided roughened copper foil.
この塗布面に１８μ厚の銅箔を重ねて１２０℃で一次加
熱してマイクロカプセルを溶融させセミキュアを行なっ
た。その後１５０℃で二次加熱し、５ ｋｇ ／−の加
圧で銅箔を一体に接着して多層積層板を得た。A copper foil with a thickness of 18 .mu.m was placed on this coated surface and was heated primarily at 120.degree. C. to melt the microcapsules and perform semi-curing. Thereafter, it was subjected to secondary heating at 150°C, and the copper foil was bonded together under a pressure of 5 kg/- to obtain a multilayer laminate.
その特性を、第１表に併せて示す。Its properties are also shown in Table 1.
比較例３
上記で使用したエポキシ樹脂１００重量部にジシアンジ
アミド４重量部＝２−エチル−４−メチルイミダゾール
０．３重量部を配合した溶液を平織ガラス布に塗布乾燥
してＢ−ステージとしたプリプレグを用意した。上記で
用いた両面プリント配線板の両表面に、前記プリプレグ
を介して１８μ厚の銅箔を載置し、加熱加圧により一体
化して多層積層板を得た。その特性を第１表に示す。Comparative Example 3 A prepreg prepared by blending 100 parts by weight of the epoxy resin used above with 4 parts by weight of dicyandiamide = 0.3 parts by weight of 2-ethyl-4-methylimidazole was applied to a plain-woven glass cloth and dried to form a B-stage. prepared. Copper foils with a thickness of 18 μm were placed on both surfaces of the double-sided printed wiring board used above via the prepreg, and were integrated by heating and pressing to obtain a multilayer laminate. Its characteristics are shown in Table 1.
第 １ 表
発明の効果
上述のように本発明は、表面銅箔の接着一体化にプリプ
レグを用いないので工程が簡略化され、またボイドの発
生が少ない多層積層板を製造できる点、その工業的価値
は極めて大なるものである。Table 1 Effects of the Invention As mentioned above, the present invention simplifies the process because it does not use prepreg to bond and integrate the surface copper foil, and also has the advantage of being able to manufacture a multilayer laminate with fewer voids, and its industrial advantages. The value is extremely great.
Claims (1)
面に、マイクロカプセル化した常温硬化剤を無溶剤エポ
キシ樹脂組成物１００重量部に対して１〜２０重量部配
合したものを塗布し、一次加熱によりマイクロカプセル
を熱溶融させ、その後二次加熱と加圧により前記塗布面
に銅箔を接着することを特徴とする多層積層板の製造法
。A mixture of 1 to 20 parts by weight of a microencapsulated room-temperature curing agent per 100 parts by weight of a solvent-free epoxy resin composition is applied to the surface of a double-sided printed wiring board whose circuit is made of double-sided roughened copper foil, and A method for producing a multilayer laminate, comprising thermally melting microcapsules by heating, and then bonding copper foil to the coated surface by secondary heating and pressure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4480187A JPS63211796A (en) | 1987-02-27 | 1987-02-27 | Manufacture of multilayer laminated board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4480187A JPS63211796A (en) | 1987-02-27 | 1987-02-27 | Manufacture of multilayer laminated board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63211796A true JPS63211796A (en) | 1988-09-02 |
| JPH0519318B2 JPH0519318B2 (en) | 1993-03-16 |
Family
ID=12701528
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4480187A Granted JPS63211796A (en) | 1987-02-27 | 1987-02-27 | Manufacture of multilayer laminated board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63211796A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003098985A1 (en) * | 2002-05-17 | 2003-11-27 | Japan Science And Technology Corporation | Method for forming multilayer circuit structure and base having multilayer circuit structure |
-
1987
- 1987-02-27 JP JP4480187A patent/JPS63211796A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003098985A1 (en) * | 2002-05-17 | 2003-11-27 | Japan Science And Technology Corporation | Method for forming multilayer circuit structure and base having multilayer circuit structure |
| CN100435603C (en) * | 2002-05-17 | 2008-11-19 | 独立行政法人科学技术振兴机构 | Method for forming multilayer circuit structure and base having multilayer circuit structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0519318B2 (en) | 1993-03-16 |
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