JPS63208226A - Manufacture of multi-chip module - Google Patents
Manufacture of multi-chip moduleInfo
- Publication number
- JPS63208226A JPS63208226A JP4032087A JP4032087A JPS63208226A JP S63208226 A JPS63208226 A JP S63208226A JP 4032087 A JP4032087 A JP 4032087A JP 4032087 A JP4032087 A JP 4032087A JP S63208226 A JPS63208226 A JP S63208226A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- pellets
- mounting board
- magnet
- pellet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000008188 pellet Substances 0.000 claims abstract description 44
- 230000005291 magnetic effect Effects 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 230000002950 deficient Effects 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 7
- 239000003566 sealing material Substances 0.000 claims description 5
- 230000005389 magnetism Effects 0.000 claims description 2
- 230000007547 defect Effects 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 11
- BGPVFRJUHWVFKM-UHFFFAOYSA-N N1=C2C=CC=CC2=[N+]([O-])C1(CC1)CCC21N=C1C=CC=CC1=[N+]2[O-] Chemical compound N1=C2C=CC=CC2=[N+]([O-])C1(CC1)CCC21N=C1C=CC=CC1=[N+]2[O-] BGPVFRJUHWVFKM-UHFFFAOYSA-N 0.000 abstract description 9
- 230000032683 aging Effects 0.000 abstract description 5
- 239000000696 magnetic material Substances 0.000 abstract 2
- 238000005516 engineering process Methods 0.000 description 7
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910017398 Au—Ni Inorganic materials 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 229910003271 Ni-Fe Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000006023 eutectic alloy Substances 0.000 description 1
- 239000003302 ferromagnetic material Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000005415 magnetization Effects 0.000 description 1
- 229910052863 mullite Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/757—Means for aligning
- H01L2224/75733—Magnetic holding means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はマルチチップモジエールにおいて、実装基板上
にマルチに搭載する半導体ペレットの容易な良品への交
換を可能とするマルチチップモジュールの製造方法に関
する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a method for manufacturing a multi-chip module, which enables easy replacement of semiconductor pellets mounted on a mounting board with non-defective products in a multi-chip module. Regarding.
従来の、多数の半導体ペレット（以下、単にペレットと
いう）を単一基板に搭載してなるマルチチップモジュー
ルにあっては、当該ペレット中の一つにでも不良がある
場合、それを良品に交換しようとしても、一旦、搭載後
には、その交換はなかなか容易でなく、仮に、取り外せ
たとしても取り外しの時間に長時間を要したりし、−の
ペレットの不良により製品全体が不良となったり、また
、そのりペア技術には問題が多かった。In conventional multi-chip modules that are made up of a large number of semiconductor pellets (hereinafter simply referred to as pellets) mounted on a single board, if even one of the pellets is defective, it should be replaced with a good one. However, once it is installed, it is not easy to replace it, and even if it is possible to remove it, it takes a long time to remove it, and a defective pellet may cause the entire product to be defective. However, there were many problems with the pair technology.
なお、マルチチップモジュールについて述べた文献の例
としては、１９８０年１月１５日（株）工業調査会発行
ｒＩＣ化実装技術Ｊ Ｐ２２７および日経マグロウヒル
社刊「日経エレクトロニクス４１９８４年９月２４日号
Ｐ２８１があげられる。Examples of documents describing multi-chip modules include rIC Mounting Technology J P227, published by Kogyo Chosenkai Co., Ltd., January 15, 1980, and Nikkei Electronics 4, September 24, 1984 issue, P281, published by Nikkei McGraw-Hill. can give.
本発明は容易なりペア技術を確立し、−のベレットの不
良により製品全体を不良とするような損失を防止し、マ
ルチチップモジュールを歩留良く得ることのできる技術
を提供することを目的とする。The present invention aims to provide a technology that can easily establish a pairing technology, prevent losses that would cause the entire product to be defective due to a defective pellet, and provide a technology that can obtain multi-chip modules with a high yield. .
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかくなるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
本発明では、磁気の作用により、ベレットを基板に仮止
めし、ベレットが不良品であるときは良品に交換できる
ようにし、仮止めしたベレットは封止材料により、基板
に固定し、封止するよ５にした。In the present invention, the pellet is temporarily fixed to the substrate by magnetic action, so that if the pellet is defective, it can be replaced with a good one, and the temporarily fixed pellet is fixed to the substrate and sealed with a sealing material. I gave it a 5.
本発明ではベレットを一旦仮止めする方法をとるので、
当該仮止めの段階で、ベレットが良品であるか不良品で
あるかをチェックして、必要に応じて容易に不良品を取
り外し新たに良品を取り付けることができ、また、封止
樹脂のボッティングなどにより、仮止めしたベレットを
固定し、同時に封止を行なうことができる。In the present invention, a method is used in which the beret is temporarily fixed, so
At the temporary fixing stage, it is possible to check whether the pellet is good or defective, and if necessary, easily remove the defective one and install a new one. For example, the temporarily fixed pellet can be fixed and sealed at the same time.
次に、本発明を、図面に示す実施例に基づいて説明する
。Next, the present invention will be explained based on embodiments shown in the drawings.
第１図に示すように、実装基板ｌの上に多数のベレット
２を搭載する。該ベレット２の裏面には磁性体層３が形
成されており、ベレット２は、実装基板１の裏面に当接
した磁石４の磁気作用により、当該実装基板１０表面に
吸着され、仮止めされている。As shown in FIG. 1, a large number of pellets 2 are mounted on a mounting board l. A magnetic layer 3 is formed on the back surface of the pellet 2, and the pellet 2 is attracted to the surface of the mounting board 10 by the magnetic action of the magnet 4 that is in contact with the back surface of the mounting board 1, and is temporarily fixed. There is.
第２図は、１の実装基板１上に多数のベレット２を仮止
めしている平面図を示す。FIG. 2 shows a plan view in which a large number of pellets 2 are temporarily fixed on one mounting board 1.
実装基板１は、例えばセラミック基板より成り、積層セ
ラミック多層配線基板により構成されている。The mounting board 1 is made of, for example, a ceramic board, and is constituted by a laminated ceramic multilayer wiring board.
ベレット２ば、例えばシリコン単結晶基板から成り、周
知の技術によってこのベレット（チップ）内圧は多数の
回路素子が形成され、１つの回路機能が与えられている
。回路素子の具体例は、例えばＭＯＳ）ランジスタから
成り、これらの回路素子によって、例えば論理回路およ
びメモリの回路機能が形成されている。The pellet 2 is made of, for example, a silicon single crystal substrate, and a large number of circuit elements are formed within the pellet (chip) using well-known techniques to provide one circuit function. A concrete example of a circuit element is, for example, a transistor (MOS), and these circuit elements form, for example, a logic circuit and a memory circuit function.
磁性体層３は、磁場において磁化する性質を有する物質
であれば特に制限はないが、例えば、鉄。The magnetic layer 3 is not particularly limited as long as it is a material that has the property of being magnetized in a magnetic field; for example, it may be iron.
コバルト、ニッケルおよびその化合物のごとく、特にそ
の磁化が磁場の一次式に従わないで強く磁化され、ヒス
テレシス現象を示す強磁性体により構成することが好ま
しい。当該磁性体層３の形成は、例えば、Ｎｉ−Ｆｅ系
合金の蒸着やＦｅ−Ｎｉ系合金よりなる金属板のＡｕ−
８ｉ共晶合金法による貼着など罠より行うことができる
。It is preferable to use a ferromagnetic material, such as cobalt, nickel, and their compounds, whose magnetization is strongly magnetized without following the linear equation of the magnetic field and exhibits a hysteresis phenomenon. The magnetic layer 3 can be formed, for example, by vapor deposition of a Ni-Fe alloy or by Au-Ni on a metal plate made of a Fe-Ni alloy.
It can be done using traps such as attachment using the 8i eutectic alloy method.
磁石４は、磁気を示す物体であれば、電磁石などであっ
てもよい。The magnet 4 may be an electromagnet or the like as long as it is an object that exhibits magnetism.
磁石４は、ベレット２！ｌｃ対し、個々に、実装基板ｌ
裏面に当接するようにしてもよい。Magnet 4 is Beret 2! For each lc, mounting board l
It may also be in contact with the back surface.
第５図に示すように、実装基板ｌに、金属板５を組込む
ようにすることにより、磁石４により、当該金属板５が
磁化され、ベレット２の実装基板１への吸着を強固にす
ることができる。なお、第５図にて、６は接合材料を示
し、例えば金属ロウ材より成る。As shown in FIG. 5, by incorporating the metal plate 5 into the mounting board 1, the metal plate 5 is magnetized by the magnet 4, and the attraction of the pellet 2 to the mounting board 1 is strengthened. Can be done. In addition, in FIG. 5, 6 indicates a bonding material, which is made of, for example, metal brazing material.
ベレット２と実装基板１上の導体パターン７とをボンデ
ィング用ワイヤ８によりワイヤボンディングする。The pellet 2 and the conductive pattern 7 on the mounting board 1 are wire-bonded using a bonding wire 8.
ボンディング用ワイヤ８は、例えば金線より成る。The bonding wire 8 is made of, for example, a gold wire.
ワイヤボンディング後、エージングやテスティングを実
施する。After wire bonding, aging and testing are performed.
もし不良品のベレット２があるときは、良品のベレット
２と交換後に、再びワイヤボンディングする。If there is a defective pellet 2, replace it with a good pellet 2 and then perform wire bonding again.
次いで、エージングと、テスティングを行ない、モジュ
ールの機能が完全であることを確認の上、第３図に示す
ように、実装基板１上に封止用樹脂をボッティングし、
熱硬化させて封止体９を形成する。Next, after performing aging and testing to confirm that the functionality of the module is complete, as shown in FIG. 3, a sealing resin is potted onto the mounting board 1.
The sealed body 9 is formed by thermosetting.
封止用樹脂としては、例えばエポキシ樹脂が使用される
。シリコーンゲルのごとき封止材料であってもよい。For example, epoxy resin is used as the sealing resin. It may also be an encapsulating material such as silicone gel.
ボッティングに際しては、第４図に示すように、例えば
、ムライト材よりなるポツティング枠１０を用い、当該
枠１０内に封止材料（ボッティング液）をボッティング
する。In botting, as shown in FIG. 4, a potting frame 10 made of mullite material, for example, is used, and a sealing material (botting liquid) is potted into the frame 10.
ボッティング枠１０は、実装基体１上に、接着剤１１に
より接着しておく。The botting frame 10 is adhered onto the mounting base 1 with an adhesive 11.
第４図に示すように、ボッティング枠１０上に、接着剤
１２により、キャップ１３を取付けする。As shown in FIG. 4, a cap 13 is attached onto the botting frame 10 using an adhesive 12.
キャップ１３は、例えば金属により構成される。The cap 13 is made of metal, for example.
実装基板１の裏面からは、外部接続用端子（リードピッ
）１４を垂直方向に引き出しし、ビングリッドアレイパ
ッケージに構成する。External connection terminals (lead pits) 14 are drawn out in the vertical direction from the back surface of the mounting board 1 to form a bin grid array package.
リードビン１４は複数格子状に配設され、ペレット２と
当該リードビン１４とは、第４図に示すように、ボンデ
ィング用ワイヤ８、実装基板ｌの表面配線７、および実
装基板１内内部配線１５により電気的に接続される。A plurality of lead bins 14 are arranged in a lattice pattern, and as shown in FIG. electrically connected.
磁石４は、上記ペレット２の封止、固定後に、実装基板
１の裏面から除く。当該磁石４のあった位置に放熱フィ
ン（図示せず）を取着してもよい。The magnet 4 is removed from the back surface of the mounting board 1 after the pellet 2 is sealed and fixed. A radiation fin (not shown) may be attached to the position where the magnet 4 was located.
本発明によれば、その裏面に磁性体層３を有するペレッ
ト２を、その磁性体層３が実装基板１の表面に当接する
ように、当該実装基板１上に、複数、載置し、該実装基
板１の裏面側に磁石４を当接して、当該磁石４の磁気作
用により、当該ペレット２を実装基板１に吸着させて仮
止めするようにし、ワイヤボンディング後、ペレット２
のテスティング（エージング）を行なう。このように、
本発明では、ペレット２は仮止めしであるので、容易に
実装基板１から取り外しすることが可能である。従来は
、ペレット２を、熱硬化樹脂接着剤により熱硬化させて
、ダイボンディングしたり、あるいは、半球状の半田ボ
ール（バンブ）によりボンディングしたりしているので
、当該半田の再溶融などを必要とし、そのりペアがなか
なか困難であったが、本発明では当該仮止めにより、良
品との交換（リペア）が容易に行うことができ、従来の
どと（、ワイヤボンディング後に、−の不良ペレットの
存在により製品全体が不良となるような損失を少なくす
ることができ、マルチチップモジュールを歩留高（製造
することができた。According to the present invention, a plurality of pellets 2 having the magnetic layer 3 on the back surface are placed on the mounting board 1 so that the magnetic layer 3 is in contact with the surface of the mounting board 1, and A magnet 4 is brought into contact with the back side of the mounting board 1, and the pellet 2 is attracted and temporarily fixed to the mounting board 1 by the magnetic action of the magnet 4, and after wire bonding, the pellet 2 is
Perform testing (aging). in this way,
In the present invention, since the pellet 2 is temporarily attached, it can be easily removed from the mounting board 1. Conventionally, the pellet 2 is thermally cured with a thermosetting resin adhesive and then die-bonded, or bonded with a hemispherical solder ball (bump), which requires remelting of the solder. However, in the present invention, by temporarily fixing, it is possible to easily replace (repair) with a good one, and it is possible to easily replace (repair) a defective pellet with a good one after wire bonding. Due to its presence, it was possible to reduce losses that would cause the entire product to be defective, and it was possible to manufacture multi-chip modules at high yields.
本発明では、このように、ペレットを完全に固着させな
くても、その後の封止材料のボッティングにより、実装
基板ｌ上に固定することができ、当該封止材料によりペ
レット２などの封止も行うことができる。In the present invention, even if the pellets are not completely fixed, they can be fixed on the mounting board l by subsequent botting of the sealing material, and the pellets 2, etc. can be sealed with the sealing material. can also be done.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.
本発明の応用として、ベンツ）Ｋ面に硬化温度が、エー
ジング温度より高い熱硬化樹脂やシリコーンゲルな付着
させて、その粘着力で実装基板に仮止めするようにして
もよい。As an application of the present invention, a thermosetting resin or silicone gel whose curing temperature is higher than the aging temperature may be attached to the Benz K surface, and its adhesive force may be used to temporarily fix it to the mounting board.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとうりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
本発明によれば、マルチチップモジュールにおけるリペ
ア技術を確立し、１ケの不良ペレットのために製品全体
が不良となるような事態を容易に回避することができ、
歩留を向上することができた点その工業上の意義は大な
るものがある。According to the present invention, it is possible to establish a repair technology for multi-chip modules, and easily avoid a situation where the entire product becomes defective due to one defective pellet.
The fact that the yield could be improved has great industrial significance.
第１図は本発明の実施例工程を示す断面図、第２図は同
平面図、
第３図は本発明の実施例工程を示す断面図、第４図は本
発明の実施例を示すマルチチップモジエールの断面図、
第５図は本発明の他の実施例を示す要部断面図である。
１・・・実装基板、２・・・半導体ペレット、３・・・
磁性体層、４・・・磁石、５・・・金属板、６・・・接
合材料、７・・・導体パターン（表面配線）、８・・・
ボンディング用ワイヤ、９・・・封止体、１０・・・ボ
ッティング枠、１１・・・接着剤、１２・・・接着剤、
１３・・・キャップ、１４・・・リードピン、１５・・
・内部配線。
第 １ 図
第 ２ 図
第 ３ＥＪ
第 ４ 図
第 ５ 図Fig. 1 is a sectional view showing the process of an embodiment of the present invention, Fig. 2 is a plan view thereof, Fig. 3 is a sectional view of the process of an embodiment of the invention, and Fig. 4 is a multifunctional FIG. 5 is a sectional view of a main part showing another embodiment of the present invention. 1... Mounting board, 2... Semiconductor pellet, 3...
Magnetic layer, 4... Magnet, 5... Metal plate, 6... Bonding material, 7... Conductor pattern (surface wiring), 8...
Bonding wire, 9... Sealing body, 10... Botting frame, 11... Adhesive, 12... Adhesive,
13...Cap, 14...Lead pin, 15...
・Internal wiring. Figure 1 Figure 2 Figure 3EJ Figure 4 Figure 5
Claims (1)
磁性体層を有する半導体ペレットを、 前記実装基板に、当該磁石の磁気により吸着させて、仮
止めする工程 （２）仮止めした半導体ペレットをボンディング用ワイ
ヤによりワイヤボンディングする工程 （３）半導体ペレットの欠陥の有無をテストし、欠陥品
であるときには良品の半導体ペレットと交換し、前記（
１）および（２）の工程を行う、半導体ペレットリペア
工程 （４）ワイヤボンディング後の半導体ペレット組立品を
封止材料により封止し、実装基板に固定する工程 を含むことを特徴とするマルチチップモジュールの製造
方法。 ２、実装基板が、その一部に金属板を組込みして成る、
特許請求の範囲第１項記載のマルチチップモジュールの
製造方法。[Claims] 1. (1) A magnet is brought into contact with the back surface of the mounting board, and a semiconductor pellet having a magnetic layer on the back surface is attracted to the mounting board by the magnetism of the magnet and temporarily fixed. Step (2) Wire-bonding the temporarily fixed semiconductor pellets with a bonding wire Step (3) Test the semiconductor pellet for defects, and if it is found to be defective, replace it with a good semiconductor pellet.
A multi-chip characterized in that it includes a semiconductor pellet repair step (4) in which the semiconductor pellet assembly after wire bonding is sealed with a sealing material and fixed to a mounting board. How the module is manufactured. 2. The mounting board is formed by incorporating a metal plate into a part thereof,
A method for manufacturing a multi-chip module according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4032087A JPS63208226A (en) | 1987-02-25 | 1987-02-25 | Manufacture of multi-chip module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4032087A JPS63208226A (en) | 1987-02-25 | 1987-02-25 | Manufacture of multi-chip module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63208226A true JPS63208226A (en) | 1988-08-29 |
Family
ID=12577318
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4032087A Pending JPS63208226A (en) | 1987-02-25 | 1987-02-25 | Manufacture of multi-chip module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63208226A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08115929A (en) * | 1994-10-14 | 1996-05-07 | Agency Of Ind Science & Technol | Method of bonding and sealing semiconductor element in parallel |
| KR19990040606A (en) * | 1997-11-19 | 1999-06-05 | 윤종용 | Semiconductor chip package |
| DE10325541A1 (en) * | 2003-06-04 | 2005-01-13 | Infineon Technologies Ag | Electronic component, and semiconductor wafer and component carrier for the production of the component |
-
1987
- 1987-02-25 JP JP4032087A patent/JPS63208226A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08115929A (en) * | 1994-10-14 | 1996-05-07 | Agency Of Ind Science & Technol | Method of bonding and sealing semiconductor element in parallel |
| KR19990040606A (en) * | 1997-11-19 | 1999-06-05 | 윤종용 | Semiconductor chip package |
| DE10325541A1 (en) * | 2003-06-04 | 2005-01-13 | Infineon Technologies Ag | Electronic component, and semiconductor wafer and component carrier for the production of the component |
| US7397111B2 (en) | 2003-06-04 | 2008-07-08 | Infineon Technologies, Ag | Semiconductor wafer, an electronic component, and a component carrier for producing the electronic component |
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