JPS63207657A - Information writing device - Google Patents

Abstract

PURPOSE:To reduce a surge voltage itself caused by an optical writing heat, by a method wherein light emitting elements are driven at different timings per group to disperse consumption of an electric current in the pour source with timing. CONSTITUTION:To a signal generation circuit 32, various signals 34-35 to be supplied to a shift register 13 and a latch circuit 16 and three types of ENABLE signals 36-1-36-3 to be supplied to logic gates 17 are supplied. When the writing of information is repeated in a cycle of 625musec, the ENABLE signals 36-1-36-3 are to exist for a period of 125musec respectively with a time- shift of about 3musec. All the logic gates 17 are divided into three groups, and the three types of ENABLE signals 36-1-36-3 are assigned and supplied to the three groups. Therefore, light emitting diodes 7 are so controlled as to be each electrically conducted for a time of 125musec, whereby the three groups of light emitting diodes 7 are so controlled as to emit with a time-shift of 3musec. In this manner, the fluctuation of the voltage of a power source is dispersed and a surge voltage is reduced to a great extent.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to an information writing device that can be used, for example, in a copying machine or printer using a photoreceptor drum, and more particularly relates to an information writing device that uses a light emitting diode or the like. The present invention relates to an information writing device using an optical writing head using an element.

``Conventional technology'' With the spread of Japanese word processors and combi coaters, opportunities to print out sentences, figures, and various data created by these devices have become more common, and various output devices have been developed for this purpose. It has reached the point where

A laser printer is a typical non-impact information writing device that forms an electrostatic latent image on a photoreceptor such as a photoreceptor drum. A laser printer scans the surface of a photoreceptor drum with a laser beam at high speed, and forms an electrostatic latent image of image data by controlling the on/off of the laser beam. The formed electrostatic latent image is developed by a developing device to create a toner image.

The toner image is transferred to the printing paper and fixed.

Laser printers can perform printing operations at high speed. However, an optical system such as a polygon mirror is required for beam scanning, making the apparatus expensive and large. Another disadvantage is that a sophisticated control circuit is required to correct the optical system.

Therefore, an information writing device such as a prink has been developed in which scanning of an optical image on a photoreceptor is performed using a light emitting diode (LED).

FIG. 6 shows the basic structure of a device using this light emitting diode. This device includes a photosensitive drum 1 for forming electrostatic latent images and toner images. Around the photosensitive drum 1, a charger 2, an optical writing head 3,
A developing device 4, a transfer device 5, a cleaning device 6, etc. are arranged.

The charger 2 is used to uniformly charge the photoreceptor drum 1 with a positive or negative charge, and is usually called a charge corotron. The optical writing head 3 has a large number of light emitting diodes 7 arranged in a row on a surface facing the photosensitive drum 1, and each light emitting diode 7 corresponds to a respective printing dot. A drive circuit (not shown) is disposed in the optical writing head 3, so that each light emitting diode 7 is independently controlled to light up. Between the optical writing head 3 and the surface of the photoreceptor drum facing it, a group of converging rod lenses (not shown) are arranged parallel to the optical writing head 3, and the blinking operation of the light emitting diode 7 is repeated in order corresponding to the image information for each line, and the resulting blinking information is supplied to the photoreceptor drum l for each line.

At this time, the photosensitive drum 1 is rotating in the direction of the arrow.

As a result, the surface of the photoreceptor drum 1 is moving in the sub-scanning direction, and as the optical writing head 3 is driven line by line, an electrostatic latent image is formed on the drum surface in a rask scan method. become.

The developing device 4 develops the electrostatic latent image thus formed with toner to create a toner image. The created toner image is transferred onto printing paper 8 by the action of transfer device 5. The transfer device 5 is a corona discharge device like the charger 2, and is usually called a transfer corotron. The printing paper 8 is fed from a paper supply tray (not shown), and after the toner image is transferred, it passes through a fixing section (not shown), where the image is fixed. Printing paper that has been fixed is
Similarly, the paper is discharged onto a paper discharge tray (not shown).

Incidentally, FIG. 7 shows the main part of the circuit configuration of the optical writing head shown in the drawing attached to the application, for example, Japanese Patent Application No. 164072/1982. This optical writing head 3 synchronizes the image signal 11 with the clock signal 12 and sets it in a shift register 13 for each one line.

The image signal set in the shift register 13 is output as parallel data 14, and is latched into a latch circuit 16 by a latch pulse 15.

Now, on the output side of the latch circuit 16, a large number of logic gates 17 are provided corresponding to the output terminals thereof. Each of these logic gates 17 has two input terminals, one of which is supplied with an enable signal 19 from the pulse generator 14 . That is, the pulse generator 18 operates based on the clock signal 21 supplied at the timing when image information is written.
Each logic gate 17 is controlled to be turned on.

The other input terminal of each logic gate 17 has a latch circuit 1
6 corresponding output terminals are connected.

Further, the cathode side of one light emitting diode 7 is connected to the output side of each logic gate 17 formed of a NAND circuit. A power supply terminal 25 is connected to the anode side of these light emitting diodes 7 via a current limiting resistor 24.

Therefore, in this conventional optical writing head, the light emitting diode 7 selectively emits light in accordance with the image signal at the timing when the enable signal 19 is output, and a recording operation for one line is performed. Thereafter, the recording operation proceeds sequentially one line at a time in the same manner.

"Problems to be Solved by the Invention" Now, FIGS. 8a to 8e show fluctuations in the power supply voltage of light emitting diodes H1-85 arbitrarily selected from among all the light emitting diodes 7 constituting the optical writing head. This represents the situation. In this example, only the third light emitting diode H3 is driven during the first drive, and all the light emitting diodes H1 to H5 are driven during the fifth drive.

Two light emitting diodes are driven in each of the second to seventh driving times except for this one. In addition,
In this example, the driving interval each time is 625μSeC, and the energization time of the light emitting diode per time is 125μSeC.
sec.

As can be seen from looking at the driving of the five light emitting diodes H1 to H5, when the power supply circuit (not shown) turns on and off a relatively large current (for example, the fifth light emitting diode
There are times when a small current is turned on and off (for example, the first time). Figure f in the figure shows changes in the power supply voltage, and when a large current is turned on and off, a large surge voltage is generated. Note that in this example circuit, the light emitting diode 7
Since it is driven by +5■, a larger surge voltage is generated when the power is turned off than when it is turned on.

When such a large number of light emitting diodes are controlled simultaneously, noise may cause malfunctions in control integrated circuits and the like due to sudden changes in current consumption of the optical writing head.

To deal with this, a method of electromagnetically shielding the information writing device generation source has been considered, but even in this case, it has not been possible to prevent the light emitting diode from deteriorating due to the surge voltage.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an information writing device that can reduce the surge voltage caused by an optical writing head.

"Means for Solving the Problems" In the present invention, the light emitting elements are driven at different timings for each group, thereby distributing the current consumption of the power supply over time. This prevents sudden fluctuations in the power supply voltage and reduces surge voltage.

"Example" The present invention will be described in detail below with reference to Examples.

FIG. 1 shows the main parts of an information writing device in an embodiment of the present invention. Components that are the same as those in FIG. 7 are designated by the same reference numerals, and their description will be omitted as appropriate.

Now, in this information writing device 31, a signal generating circuit 32 indicated by a broken line is different from that in FIG.

This signal generation circuit 32 includes various signals 34 to 35 supplied to the shift register 13 and latch circuit 16, and three types of enable signals 36-1 supplied to the logic gate 17.
~36-3 are now supplied.

FIG. 2 specifically shows this signal generating circuit. The signal generation circuit 32 includes a 2600-decimal counter 41, a read-only memory 42, and a latch circuit 43. A clock signal 44 is supplied from a clock generation circuit (not shown) to each clock input terminal of the 2600-decimal counter 41 and the line circuit. Here, the clock signal 44 is 41600
It is a continuous pulse consisting of a simple square wave with a frequency of 00 Hz.

The 2600-decimal counter 41 has output terminals QA-QL. Then, for each line where information is written, counting is started at the rising edge of the clock signal 41, and the count value from "0" to "2599" is 625 μm.
It is simply repeated at a cycle of 5 ec (microseconds). 2600
1 output from the output terminal QA-QL of the digit counter 41
The 2-bit count information is supplied as address information to the read-only memory 42, which has a structure of 2600 words x 5 bits. The read-only memory 42 has 12 address input terminals AO-All and 5 output terminals O1-05, and when address information is input,
Based on this, pulse signals 46-1 to 46-5, which change at predetermined timings, are read out. These pulse signals 46-1 to 46-5 are latched by a latch circuit 43, and output as a clock pulse 34, a latch pulse 35, and three types of enable signals 36-1 to 36-, respectively.
It will be output as 3.

FIG. 3 shows the read-only memory 42 shown in FIG.
It represents the contents of The count value as address information supplied to the read-only memory 42 is “
When it changes repeatedly in order from O''' to "2599",
Pulse signal 46-1 output from first output terminal 01
When the address information changes from "0" to "2047", the signals "O" and "1" are alternately changed every time the address information changes. Then, the address information “204
The signal from "8" to "2599" is fixed to signal "0".

As a result, the pulse 34 output from the latch circuit 43 becomes as shown in FIG. 4d. That is, 416
Assuming that the signal waveform of the clock signal 44 with a frequency of 0000 Hz is as shown in FIG.
The count value of the advance counter 41 is as shown in the figure, and each time the clock signal 44 rises twice in the first half of the information write operation for each line, the clock is clocked one pulse at a time as shown in the figure d. will now be output. The clock signal 34 is transmitted to the shift register 13 shown in FIG.
and one line 1024 as shown in FIG. 4C.
The input of the image signal 11 for pixels is performed serially.

On the other hand, the pulse signal 46-2 output from the second output terminal 02 in FIG. 3 has address information "2049".
The signal is "1" when this is the case, and is "0" otherwise. This pulse signal 46-2 is latched by the latch circuit 43 and becomes a latch pulse 35 (FIG. 4f). This latch pulse 35 causes the latch circuit 16 to latch the parallel data 14 (FIGS. 11 and 4e) in the shift register 13, which has already been set for 1 2 minutes. FIG. 4g shows parallel data 47 output from the latch circuit 16. With the latch,
The old data from l lines ago will be replaced with new data.

Now, the third to fifth output terminals 03 to 05 in FIG.
from "2051" to "2570" and "2" respectively.
063” to “2582” or “2075” to “
Pulse signals 46-3 to 46-5 are output, in which the signal is "1" up to 2594" and the signal is "0" in other cases.

These pulse signals 46-3 to 46-5 are also connected to the latch circuit 4.
3 and output as enable signals 36-1 to 36-3, respectively, as shown in FIG.

When writing information is repeated at a cycle of 625 μSec, each of the enable signals 36-1 to 36-3 exists for 125 μsec, and these enable signals 36-1
The deviation of ~36-3 is approximately 3 as shown in Figure 4.
It becomes μSec. The total number of logic gates 17 shown in FIG.
They are divided into two groups, and three types of enable signals 36-1 to 36-3 are assigned and supplied to these groups. Therefore, the light emitting diode 7
The energization is controlled for a time of , and the deviation in lighting control of the three groups of light emitting diodes 70 is 3 μsec. Here, the time difference of approximately 3 μsec is set as a time amount larger than the generation time width of the surge pulse, and there is no need to limit it to this value.

FIG. 5 corresponds to FIG. 8 as the prior art.
The driving timing of the two light emitting diodes 7 and the variation of the power supply voltage that occurs at that time are shown for the information writing device of this embodiment. light emitting diode H1,
H4 (a, d in the figure) is driven by the enable signal 36-1, light emitting diodes H2, H5 (e, in the figure) are driven by the enable signal 36-2, and the remaining light emitting diode H3 (C in the figure) is driven by the enable signal 36-2. is driven by the enable signal 36-3. In this case, even in the fifth time when all of these light emitting diodes H1 to H5 are driven, the drive timing is shifted three times by approximately 3 μsec, so the fluctuations in the power supply voltage are dispersed and surges occur, as shown in Figure f. Voltage decreases significantly. Even in the 2nd to 4th, 6th, and 7th times 1, in which the light emitting diodes 7 are driven two at a time, the timing of power consumption is shifted for the same reason, and the surge voltage is significantly reduced. It turns out.

In the embodiment described above, the light emitting elements constituting the optical writing head of the information writing device are divided into three groups and driven by an enable signal as a drive pulse, but they may be divided into four or more groups. , may be divided into two groups and driven.

Further, in the embodiment, signal information for shifting the drive timing is created using a read-only memory, but the present invention is not limited to this, and it goes without saying that the same drive control can be performed using various methods.

"Effects of the Invention" As described above, according to the present invention, the surge voltage can be significantly reduced, so the life of the light emitting element can be extended, and abnormal light emission caused by the surge voltage can also be prevented.

[Brief explanation of the drawing]

Figures 1 to 5 are for explaining one embodiment of the present invention, of which Figure 1 is a block diagram showing the main parts of the information writing device, and Figure 2 is a block diagram of the signal generation circuit. , Fig. 3 is an explanatory diagram of the contents of the read-only memory, Fig. 4 is a timing diagram showing the operation of each part of the information writing device, and Fig. 5 is a diagram showing the drive timing of the light emitting diode and fluctuations in the power supply voltage. 6 is a schematic configuration diagram showing the main parts of an example of an information writing device, FIG. 7 is a block diagram showing the main parts of the circuit of a conventionally proposed optical writing head, and FIG. FIG. 3 is a waveform diagram showing the drive timing of a light emitting diode and fluctuations in power supply voltage in an information writing device using the proposed circuit. 7... Light emitting diode (light emitting element), 25...
...Power terminal, 31... Information writing device, 3
2... Signal generation circuit, 36-1 to 36-3... Enable signal, 41
...2600 decimal counter, 42 ... Read-only memory.

Claims (1)

[Claims] An optical writing head in which a plurality of light emitting elements are arranged in a row to write and scan information by light, a power source for driving this optical writing head, and all the light emitting elements constituting the optical writing head. What is claimed is: 1. An information writing device comprising drive timing control means for dividing the information into a plurality of groups and controlling the groups so that the groups are driven at different timings.