JPS63206835A - Logic circuit simulating system - Google Patents

Abstract

PURPOSE:To shorten a simulating time, by transferring an input signal string required for each real parts, performing a logical operation in each real parts in parallel, and transferring respective computed result to a software simulation comprehensively. CONSTITUTION:Input vectors 108 and 109 for integrated circuits A and B registered on a real parts event table are collected in one packet, and is transferred from a software logical simulator 101 to a real parts logical simulation device 102. The device 102 divides it into input circuits A and B, and drives two real parts 105 in parallel. After the simulation of the real parts being completed, and output vectors of the circuits A and B are collected in one packet consisting of 110 and 111, and it is transferred to the simulator 101. During that time, the simulator 101 waits the transfer of the calculation result from the device 102, and then it is transferred, registers the output vector on the event table. After that, the simulation of a software model is performed. In such a way, it is possible to perform the parallel operation of the real parts to be processed, and to accelerate processing speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic circuit simulation method, and particularly to a logic simulation method for a circuit including an element whose internal logic is unknown, such as a microprocessor.

[Conventional technology]

Conventionally, simulations of digital logic circuits have generally been realized using software using general-purpose computers. An equivalent logic circuit is configured using basic circuits such as AND gates and OR gates using software in an integrated circuit, and a general-purpose computer program is used to create AND gates,
This was achieved by calculating the output in response to an input stimulus, such as an OR gate. However, with this method, it is difficult to accurately create an equivalent circuit for a highly integrated device such as a commercially available microprocessor whose internal logic circuit diagram is not made public.

As a solution to this problem, there is an interlocking simulation method of software models and real parts.

In this method, for integrated circuits whose internal logic circuits are unknown, actual components are used as simulation models, and for other logic circuits, logic simulations are performed using software models as before, and the calculation results of the software models are implemented. By sending the output value of the actual component back to the software model, the entire target logic circuit is simulated.

In addition, as a publicly known example related to this, for example, equity M6
1-36262 can be mentioned.

[Problem that the invention seeks to solve]

Interlocking simulator 1 of the above software model and real parts
According to this method, it is relatively easy to simulate a logic circuit that is highly integrated, such as a commercially available microprocessor, and includes elements whose internal logic circuit diagrams are not made public. However, conventionally, no consideration has been given to improving performance when there are multiple integrated circuits whose internal logic is unknown in the logic circuit to be simulated.As a result, as the number of integrated circuits whose internal logic is unknown increases, software Because the number of communications between the model and real parts increases, and communication between the software model and real parts is done serially, the time required for logic simulation increases in proportion to the number of real parts in the circuit targeted for logic simulation. There was a problem.

An object of the present invention is to provide a logic circuit simulation method in which, like a commercially available microprocessor, elements whose internal logic is unknown are represented by real parts in a logic circuit to be simulated, and other parts are represented by software models. One object of the present invention is to provide a logic circuit simulation method for quickly simulating a logic circuit including a plurality of unknown elements.

[Means for solving the problem] ゛The above purpose is to select a plurality of real parts that can be operated simultaneously from among a plurality of real parts by a logic simulator realized by a software model, and to The input signal sequence required for (
This is accomplished by simultaneously transferring the input vectors), performing logic operations in parallel on each of the real components, and transferring the results of each logic operation all at once to a software logic simulator.

[For production]

In a logical simulation method that links real parts and software models, the processing time T required per unit simulation time is the time t required for logical simulation of the software model, and the processing time t required for the logical simulation of the software model, and the processing time T required for multiple real parts (RMl, R
M,, ・RMn) It is the sum of the time required for each logic simulation tHL e tll t..., t□. That is, 2N, a plurality of real parts 1, for example RM Yu.

When RM and RM operate in parallel, the time required for logical simulation of RML and RM is the largest value (for example, 70i) of tll and t□, and the sum of each (
1N, +1. , ).Therefore, the time T' required for logic simulation in this case is T', and the logic simulation time can be shortened.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. In this embodiment, an example will be described in which an event-driven method, which is widely used as a software logic simulation method, is used.

The event-driven method tracks only the elements that generate signals in the circuit being simulated.

It is used as a method to reduce processing time. A signal change request is called an event, and a table in which the events are recorded is called an event 1 table. Also, as a means of managing time within the logic simulator,
Usually, a time loop table is provided. The time loop table is divided into a plurality of slots, each slot representing the smallest unit of time in the simulator, and each event is defined as:
Connected to the time loop table slot corresponding to the time to be processed.

FIG. 5(a) is an example of a logic circuit including two integrated circuits whose internal logic is unknown, and integrated circuit A and integrated circuit B are simulated using real components mounted on a real component logic simulation device. , the other circuits are simulated on a software logic simulator. 501 and 502 in the figure are the input signal line and output signal line of the NAND gate G1, respectively, and 503 and 50 in the same figure (b)
4 is a signal waveform on signal lines 501 and 502. Here, t□+tzt t3 is the time in the logic simulator. The difference from time t to t3 is due to the gate delay of NAND gate G1.

Figure 6 shows the relationship between the time loop table and the event table in the software logic simulator when the signal change shown in Figure 5 occurs. The illustrated step t tzt t3 corresponds to txe tay ta in FIG. Also, 6 in the figure
02 is an event to be processed at time t, indicating that the output values of integrated circuit A, integrated circuit B, and AND gate G2 must be calculated from 2 to 2.

FIG. 7 shows the contents of each event table. In the figure, 701 indicates whether the element to be simulated is a real component or a software model. 702 is the type of element, which is used in a real component logic simulation device.

This determines which real part should be given the input vector and driven. 703 stores an input vector to be supplied to the corresponding model; 704 stores the address of an element to which the calculated output value of the model is to be transmitted; and 705 stores the address of another event table to be processed within the same time.

FIG. 8(a) shows a real parts event table 801 that stores only events related to real parts to be processed at the same time.
b) shows a software model event table 802 dedicated to software models.Each record in these two types of tables includes element identification name 7 among the information in the event table in FIG.
Information of 02 to cutting edge pointer 704 is stored.

FIG. 1 is a block diagram of one embodiment of the present invention.

This shows a system configuration in which a software logic simulator and a real component logic simulation device are connected. 1
01 is a software logic simulator realized on a general-purpose computer. The time loop table and each event table explained in FIGS. 6 to 8 are prepared in the software logic simulator 101. Reference numeral 102 denotes a real component logic simulation device, which is equipped with the integrated circuit itself to be simulated, and receives and receives its input signal sequence (input vector) from the software logic simulator 1.01.

In this example, two real components, 105 integrated circuits A and B, are mounted on the real component logic simulation device 102. The real component logic simulation device includes 102 controller 103, and an input register 1 that stores input vectors given to each real component 105.
04, output register 106 for storing the output vector of each real component 105 and output register 1 of each real chip 105
06 into one packet, and has the function of operating two or more real parts at the same time.

108.109 is software logic simulator 101
The input vectors for the integrated circuits A and B of 105 are packetized, and the data contents for each actual component include an element identification name 120 indicating the type of the actual component and the actual component as shown in FIG. 2(a). Input vector 12 for the part
Consists of 1. 101.111 are 105 integrated circuits A and B
The data contents for each real part consist of an element identification name 122 and an output vector 123 of the real part, as shown in FIG. 2(b).

FIG. 3 shows an example of the processing flow according to the present invention. When there are multiple real parts that can operate at the same time, the software logic simulator 101 detects these real parts and calculates the input vector for the plural real parts. Logic simulation proceeds by transferring the data as one packet to the real component logic simulation device 102.

First, in process 310, the simulation start time is initialized, and in simulation time end determination process 302, if the simulation end time has not been reached, simulation processing begins. Hereinafter, the explanation will be given using FIGS. 5 to 8 as examples.

Through processes 303 to 306, for all event tables connected to the time loop indicated by timer T, it is determined whether the registered element is a real component or a software model, and if it is a real component, it is determined whether it is a real component event table or if it is a software model, it is a software model event. They are registered while being sorted into a table.

In this case, the events registered in the real component event table and the software model event table only need to be processed within the same simulation time, and even if the processing order among these events is changed, there is no effect on the simulation results. No. Now, when timer T is at time t in FIG. 5(b), there are three events to be processed,
Two of them are integrated circuits A and B, which are simulated using real components, and one is a software model, A.
Since it is the ND gate G2, the actual parts event table and software model event table become as shown in FIGS. 8(a) and 8(b) through processes 303 to 306.

In process 307, the input vectors for integrated circuits A and B registered in the real component event table 801 are converted to 1 in FIG.
08,109 as one packet (first
1 (a) is the format of the packet), and is transferred to the real component logic simulation device 102 in process 308. By this packetization, the software logic simulator 101 is transferred to the real component logic simulation device 1.
The number of input signal transfers to ゜2 is reduced (in this example, 1
/2), usually this software logic simulator 10
The time required for communication between 1 and the real component logic simulation device 102 is the data transfer processing time that depends on the data, etc., and the pre-processing and post-processing such as channel deallocation that depends on the number of communications, that is, the overhead time in packet units. determined by Therefore, if the data transfer path is the same, the processing time will be shorter if the number of communications is smaller, and the method of this embodiment can reduce the communication time between the software logic simulator 101 and the real component logic simulation group [102].

In the real component logic simulation device 102, the controller 103 divides the input packet into integrated circuits A and B, stores it in the input register 104, and divides the input packet into two real components 10.
5 are lined up and driven. At this time, the required time is the better of the times required for each of the 105 integrated circuits A and B to operate, and is clearly shorter than the time required for these two actual components to operate serially. When the simulation of the actual part is completed, the output vector buffer device 10
7 is an output register 10 for output vectors of integrated circuits A and B.
6, the packets are collected into one packet as in the first packet 110 and 111 (FIG. 2(b) is the format of this packet), and transferred to the software logic simulator 101.

Note that this also has the same effect as reducing the number of communications from the software logic simulator 101 to the real component logic simulation device 102.

During this time, in the software logic simulator 101, the real component logic simulation device 102 performs processing 309.
The process of waiting for the calculation results to be transferred can be realized using the same mechanism as the data exchange with an external storage device that is normally performed in a general-purpose computer system or the like. When the calculation results are transferred, the output vectors are newly registered in the event table for each signal in step 310. This process can be realized using exactly the same procedure as the event registration process normally performed in a software logic simulator. Thereafter, in process 311, the software model is simulated. In this process as well, for an element whose output signal value has newly changed, the element connected to that output signal line is newly registered in the event table.

As described above, when all events to be processed at time T are exhausted, the simulation time is advanced by one unit and the same process is repeated.

Through the above processing, real parts to be processed at the same time can be operated in parallel, and simulation processing speed can be improved.

Furthermore, even when the number of integrated circuits to be operated in parallel is three instead of two as in this embodiment, the controller 102 in FIG. It has three sets of circuits that control the timing to supply and the timing to latch output data, and further 104,
It is equipped with three sets of functions for driving real components 105 and 106, and searches for up to three integrated circuit events that can be simultaneously driven on the simulator 101 side of the software model from the event table and combines them into one packet. This can be realized by having a function to transfer data to the real component logic simulation device 1028.

Similarly, it can be easily inferred from this embodiment that four or more integrated circuits can be operated in parallel.

Even when three or more real parts are operated in parallel in this way, the 4 hours required for real part simulation is the longest time out of the time required to operate all real parts individually, and This is clearly shorter than the time it takes for parts to operate serially.

〔Effect of the invention〕

As explained above, according to the present invention, in a logic simulation method in which real parts and software models coexist, such as real parts linked logic simulation, it is possible to operate real parts to be processed at the same time in parallel. Therefore, the effect of shortening the simulation processing time can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a diagram showing the contents of input packets and output packets, and Fig. 3 is a block diagram of an embodiment of the present invention.
Logic simulation processing flowchart with diagrams,
FIG. 4 is a diagram explaining a logic circuit including an integrated circuit, FIG. 5 is a diagram showing an example of a circuit configuration targeted for logic simulation of the present invention, and FIG. 6 is a diagram showing the relationship between a time loop table and an event table. Figure 7 is a diagram showing the contents of the event table,
FIG. 8 is a schematic diagram of a table that separates real parts and software model events. 101... Software logic simulator, 102.
・Real component logic simulation device. 103...Controller, 104...Input register, 105...Actual part, 106...Output register. 107...Output vector patho device. First cause Figure 4 Figure 5

Claims (1)

[Claims] (1) In a method of simulating logic circuits by linking a software logic simulator and real components, the software logic simulator selects multiple real components that can operate simultaneously when supplying logic operation signals to the real components, A necessary logical operation signal is given to the plurality of real parts, and on the real part side, the plurality of real parts to which the said logic operation signal is given perform the logical operation in parallel, and the plurality of real parts A logic circuit simulation method characterized by sending the results of logic operations in bulk to a software logic simulator.