JPS6320640A - Memory access controller - Google Patents

Abstract

PURPOSE:To improve the performance of memory access processing by suppressing the write to a cache memory if cache mishit occurs during sweep of the cache memory. CONSTITUTION:A rewrite control part (RE WRT CNT) 10C, a write suppression control part (WRT ST CNT) 114 for a DA CNT 109, a timing priority control part (TMG CNT) 10F, an OR gate 110, an AND gate 111, a signal line (BYPS) 115, and a cache memory address control part (AACNT) 113 are provided.If a sweep instruction is set to a mode register (SMDR) 10E and a signal WRTMISS 112 indicating that the write request fails to hit exists, the write of merge data to a cache memory data part (CDA) 106 is suppressed in accordance with the output of the AND gate 111 by the control of the WRT ST CNT 114 in the DA CNT 109. The CDA 106 is by-passed through the BYPS 115, and this merge data is selected by the control of the RE WRT CNT 10C and is stored in a swap data buffer (SDB) 107.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory access control device that handles a cache memory and is capable of executing data transfer between a main storage device and a main storage device using block data. The present invention relates to a control method when a memory access request, which is a write request from a device, causes a cache miss.

[Conventional technology]

In conventional memory access control devices, a cache memory is provided for the purpose of improving the performance of memory access processing and reducing the load on the main storage device, and caches memory access requests from the processing device with a probability of 90% or more. In the case of a cache miss, cache memory data is replaced, and at this time, cache-memory data is swapped out as necessary to maintain the latest data.

Swap-out control of cache data when a memory access request from a processing device hits the cache is performed by the M bit of address play, as will be described later. Kiya.

When data is written to the memory, the M bit provided at the corresponding address in the address array is updated and set to logic 1. When a memory access request from a processing device causes a cache miss, the longest unused history section (1st recently used or less L
If the M bit corresponding to the replacement level determined by the RU (referred to as RU) is logical 1, the cache memory data is swapped out.

As described above, when a memory access request from a processing device is cached, the memory access control device performs 10 data transfers with the main storage device and replaces cache memory data. If the cache-missed memory access request is a write request, the memory successive data will be merged with the write data from the request source and written to the cache memory.

FIG. 2 is a block diagram showing a general computer system. In a memory access control unit (hereinafter referred to as 8IU) 201, each processing unit (hereinafter referred to as dcPU for central processing unit and dIOP for input/output processing unit) )20
3. When a memory access request is received from the l0P204, it is processed according to its priority and transferred to the main memory (hereinafter referred to as MM
A memory access request is sent to 202 (referred to as U).

If the memory access request is a write request, the write data is written to the corresponding address of the MMU 202, and if the memory access request is a read request, the data at the corresponding address of the MMU 202 is read out and sent to the requesting processing device via the S IU 201. will be returned to.

In this 8IU 201, when a cache memory is provided for the purpose of improving the performance of memory access processing and reducing the load on the MMU 202, the CPU 203, l0
A memory access request from P204 will be cache-hit with a probability of over 90%, and processing for the request can be executed without going through MMU2O5, and in the case of a cache miss, memory data will be successively transferred to and from riMMU 202 and the necessary Accordingly, swap out the block data and write the latest data to the cache memory.

The memory access processing is performed by the other system memory access control device 8IU211. Main storage device MMU212 and processing device CPU213. The same applies to l0P214.

In the computer system, when the S IU 201 is disconnected due to a malfunction or other cause, when the S IU 201 is connected, the cache memory data in the S IU 201 is exported to the MMU 202 for the purpose of retaining the latest data. An instruction to write out essential memory data is issued, and the cache memory data at the corresponding address according to the instruction is transferred to the MMU 202.
swapped out.

FIG. 3 is a 10-step diagram of a conventional memory access control device.

CPU203. If a memory access request, which is a write request from l0P204, causes a cache miss, the third
In the memory access control device 5IU301 shown in the figure,
A memory data read command is issued to the MMU 302 under the control of a read control unit (hereinafter referred to as RDCNT) 30A. The MMU 302 receives the read command and reads the data at the corresponding address (Profile).

data) is read out and sent to the 5IU 301.

In the S ItJ 301, the timing of the data reply from the MMU 302 is recognized, and when the memory read data is accepted, the write data stored in the miss door data buffer (hereinafter referred to as MSDB) 303 is data and memory data register (hereinafter referred to as MDR).
5) Through the cache memory control unit (hereinafter referred to as DACNT) 308, the cache is
The merged data is written into a memory (hereinafter referred to as DA) 306. At this time, if it is necessary to swap out the DA306 data, the data of the relevant DA306 is swapped out, swapped out, and swapped out.
307 and according to a memory write command from the write control unit (hereinafter referred to as WRTCNT) 309? '1Hlr
Send to iU 302.

The above is the process when a memory access request, which is a write request, causes a cache miss.The request is executed when a write request is issued from the mode register (hereinafter referred to as SMD R) 30C, and all cache memory DA306 data is being written out. If it is accepted, after writing the data to the DA306, the data of the DA306 at the corresponding address will be
It will be output to υMMU 302 under the control of WRTCNT 309. That is, when writing data (block data) to the DA 306 is to be read out, it is necessary to write the block data to the DA 306 and read the block data from the DA 306 because the data is written through the DA 306.

Also, the execution of swap-out is determined by the M bit registered in the cache memory address section (hereinafter referred to as AA) 401 in FIG. 4.

SI [J201 cache memory (AA4 o 1 and cache memory data section (hereinafter referred to as ODA) 407
This level is the target of data replacement. CPU203” or l0P2
The replacement level when the memory access request from 04 causes a cache miss is indicated by LRU 402. LRU402ri Indicates the least recently used level for replacement.

For example, cache memory levels 0 to 3 are o → 1 → 2
When accessed in the order of →3, level 3 has the highest priority, and the priority is riO→l→2→3. Next, when the cache memory is accessed in the order of level 2 → level 0, the priorities change as ri1 → 3 → 2 → 0, and the replacement level indicated by the LRU 402 is level 1, which has the lowest priority.

In this way, a replacement level is indicated under the control of the LRU 402, but swapping out of data at a corresponding address within this level is executed only when the M bit=111.

Mh't) It is registered in dAA401, and CDA4
When there is a write to 07, the M bit of the target address in AA401 is updated to 111. Part M bit = 11
When it is 1, it indicates that data is written to the dCDA 407, that the data is the latest, and that it is different from the data at the target address in the main memory device MMU2O5. Swap out is performed to maintain this latest data.

AA40 corresponding to the cache miss address
1) is stored in the riM pit register (hereinafter referred to as MAAR) 4o3, and its output and the replacement level LVLO~3 which is the output of the LRU 402
(NAND game) 405 is the condition. Tsumashi L
Swap out is performed only when the M bit of the replacement level indicated by RU 402 = 11''.

5 As for the operation of the IU 201, if a memory write request from the CPU 203 or the 10P 204 causes a cache miss, as shown in FIG. =
l lt ), the data at the corresponding address of the CDA 407 is flopped out to the MMU 2 Q 2 . The completion of the swap-out is performed upon the completion of the swap-out to the memo IJa ratio data to the corresponding level. When N (beep) = "O", the memory read data is written to the corresponding address of the CDA 407 without performing tit.

[Problem that the invention seeks to solve]

The conventional memory access control device described above transfers block data to and from the main storage device when a memory access request from the processing device causes a cache miss.
If the memory access request is a write request, the memory read data at this time is merged with the write data from the request source.
Cache - will be written to memory.

Here, even though all cache memory data is being read out, if a memory access request, which is a write request from the processing device, is missed and a cache miss occurs, the memory read data and the request source are The data merged with the write data is written to the cache memory once, so after the data is merged, the data must be written to the cache memory before being sent as write data to the main storage device. This method has the disadvantage that it is necessary to perform block data write processing and read processing of the same block data, resulting in time loss.

In addition, when a memory access request causes a cache miss, reading of memory data, saving to the cache memory, and smoothing out cache memory data as necessary are performed using block data, so the performance of the processing is improved. There is a problem with the decline. especially the cat-
In the memory data swap-out process, data is read from the cache memory and data is written to the main storage device using block data, so if the probability of a short-out is high, the performance will be severely degraded.

[Means for solving problems]

The device of the present invention has a store-in type cache memory, and when a memory access request from a processing device causes a cache miss, the device transfers data to and from the main storage device in units of a predetermined data length. In the access control device, when the cache-missed memory access request is a write request, the merged data obtained by merging the memory successive data from the main storage device and the write data from the processing device is stored in the cache memory. swap data buffer storage data selection means for selecting the merge data as data to be stored in the swap data buffer bypassing the cache memory; A command conversion means for converting a read command into a memory rewrite command, a memory read command accompanying a memory access request which is a write request that has caused a cache miss, a memory write command at the time of a short-out, and the command conversion means. memory access request means for selecting the converted memory rewrite command and sending it to the main storage device; Means for suppressing updating of a bit indicating a match with information stored in an address of a storage device; and a means for suppressing update of a bit indicating a match with information stored in an address of a storage device; and write inhibiting means for inhibiting writing of the merge data to the cache memory only when there is a hit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The main difference from the conventional device shown in FIG. 3 is the rewrite control unit (hereinafter referred to as R, EWRT CNT) IOC.

Write inhibition control unit (hereinafter referred to as WRT) in the DACNT109
(referred to as ST CNT)114. Timing ply 1st
Note control unit (hereinafter referred to as TMGCNT) 10F, OR
Gate 110. AND game) 111. The signal ax1s (hereinafter referred to as BYPS) and the cache memory address unit control unit (hereinafter referred to as AACNT) 113 are set to the cache memory address unit (hereinafter referred to as AACNT).
108°) and a cache memory data section (hereinafter referred to as ODA) 106.

Next, the operation of this embodiment will be explained with reference to FIG.

A memory access request, which is a write request from the processing device, is automatically processed.2. ．． If the memory read command is created by RDCNTloB, the main memory device MMU1
02. When MMU l 02 receives a memory read command, it reads the data at the corresponding address and writes 5IUI
It recognizes the data reply timing from the 8IUi01t-tMMU102, and when it receives memory successive data, it merges it with the data in the MSDB 103 and stores the merged data in the register MDRIQ5. The MDR
The merge data stored in DACNT 105 is
is written to 0DAIQ5 under the control of . At the same time, 0
The merge data bypassing DAIQ5 via the signal line 115 is selected under the control of REWRTCNTloC and stored in 5DRIQ7. The memory read command created by R, DCNTIOB and sent to MMU IQ 2 is converted into a memory refill command by REWRTCNTloC, and its typing and priority are controlled and selected by 1GcNT10F at T, and then sent via register ADR10D. kIMU 102. The merge data stored in the 5DB 107 and bypassing the DA 106 is written to the MMU 102 in accordance with the memory rewrite command. By the way, the address information for the merge data written in the CDA 106 is registered in the AA 108, but in this case, the M bit of the AA 108 corresponding to the address is not updated under the control of the AACNT 113.
It is.

Incidentally, in this cache-miss-hit processing, a short-out processing is executed as necessary.

The above processing operation is performed by the SMDR10E output which indicates the same function as the SMDR30C explained in FIG.
The output of the OR gate 110, which is the logical sum of the control signal WRTMI8S112 indicating that the write request has caused a cache miss, is output as TMGCNTloF and REWRTCNT.
By sending it as loC, the memory read command is changed to a memory rewrite command, and the timing is controlled to select this memory rewrite command. Furthermore, the AND gate 111 output, which is a logical product, is sent to the DACNT 109.
Writing to 106 is prohibited only when the carriage is being ejected, and the control signal WRT MI S 8112 is set to AACN
The above processing is executed by transmitting the data to T 113 and suppressing the update of the M bit.

Next, the operation when a memory access request, which is a write request, is accepted during the entire cache-memory data flushing process and a cab mismatch occurs will be described below.

When the SMDRIOE receives this write instruction and there is a WRTMIS8112 signal indicating that the write request has missed, the output of the AAND gate 111:
WR, T ST in CNT 109. Writing of merge data to 0DA 106 is suppressed under the control of CNT 110, CDA 106 is bypassed via BYPS 115, and this merge data is selected under the control of IIWRTCNT and toC and stored in 5DB 107. (This merge data is block data). Created with R, D CNT10B due to cache miss, v processing q, MM
Memory read command riREWRT sent to U 102
CNT10CK is converted into a memory rewrite command. This memory rewrite command is selected with timing controlled by TMG CNT 10F and sent to MMU 1o2. TMGCN T10 Fri key?
? '/-When there is a mishit (DM Recognizes the data reply timing from the MMU 102 and controls the selection timing of the memory rewrite command to the MMU 102 in consideration of it. 5 Merge data stored in the DB 107 MMU l according to this memory rewrite command
It is written to a predetermined address of 02.

〔Effect of the invention〕

As explained above, in the present invention, only when a memory access request, which is a write request from a processing device, causes a cache miss, memory read data from the main storage device,
The merge data with the write data from the processing device is written to the cache memory, and is written to the main memory, and furthermore, the update of the M bit indicating where data has been written from the processing device is suppressed. This method improves the performance of memory access processing by reducing the probability of cache memory data being swapped out, and by inhibiting writes to the cache memory when there is a cache miss as described above during cache memory flushing. It has the effect of being able to do things.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a professional computer system diagram, Fig. 3 is a block diagram showing a conventional device, and Fig. 4 is a block diagram explaining setup and pullout. It is a diagram. 101...Memory access control unit (SIU)
, 102... Main memory unit (MMU), 103.
...Miss store data buffer (MSDB)
), 104...Memory data register (MD
R), 105-...Memory data register (MD
R), 106... Catch-memory data section (CDA), 107... Swap data buffer (SDB), 108... Catch-memory address section (AA), 109 ---DA control section (D
ACNT), IOA...Write control unit (WRT
CNT), 10B--Read control unit (RDCNT)
, IDC...Rewrite control unit (RBWRTCNT
), IOD...Memory access register (AD
R), IOE...Mode register (SMDR), 10F...Timing priority control unit (TMGCNT), 110...OR gate,
111+++ +++ A N D gate, 112...
...Signal line (WRT MISS), 113.
...A A f! 1TIJ both parts, 114...
...Write inhibition control unit (WRT 5TCNT), 11
5...Signal line (BYP8), 201...
・Memory access control device (SI tJ'), 2Q
2... Main memory unit (MMU), 203...
...Processing unit (CPU), 204...Processing unit (IOP), 211...Memory access control unit (SIU), 212...Main storage device (f to M
U), 213...processing unit (CPU), 214
...--Processing device (IOP), 301...
Memory access control unit (SIU), 302...
- Main memory unit (MMU), 303... Mishit store data buffer (MSI) B), 304...
...Memory data register (fDR), 305.
...Memory data register (MDR), 306.
Old memory for cache (DA), 307...-
Swap data <Zuffa (SDB), 308...-
・Cache memory control unit (DACNT), 309・
...Write control unit (WRTCNT), 30A...
...-Read control unit (RDCNT), 30B...
Memory access register (ADR), 30C...-
Cache memory address section (AA), 402... Longest unused history section (LRU), 403... M bit register (MAARl), 404, ring...D to control section (DACNT), 405...NAND game)
(NAND), 406...-NAND gate (NAND) 407... Cache memory data section (CDA), 408... Address register (AR). \, Nino' 1st side F 2T:! 3

Claims (1)

[Claims] Memory access that has a store-in type cache memory and executes data transfer to and from the main storage device in units of a predetermined data length when a memory access request from a processing device results in a cache miss. In the control device, when the memory access request causing the cache miss is a write request, writing merged data obtained by merging memory read data from the main storage device and write data from the processing device to the cache memory; Swap data buffer storage data selection means for selecting the merged data as data to be stored in the swap data buffer bypassing the cache memory; and memory read data sent to the main storage device when the memory access request results in a cache miss. a command conversion means for converting a command into a memory rewrite command; a memory read command associated with a memory access request which is the write request that caused the cache miss; a memory write command at the time of swap out; memory access request means for selecting the converted memory rewrite command and sending it to the main storage device; and when writing the merge data to the cache memory,
means for suppressing updating of a bit indicating a match between information stored in a cache memory and information stored at a corresponding address in the main storage device; 1. A memory access control device comprising write inhibiting means for inhibiting writing of said merge data to a cache memory only when there is a memory access request, which is a write request, and a cache miss occurs.