JPS63206025A - Mute circuit - Google Patents

Abstract

PURPOSE:To prevent muting from being conducted due to a voice during communication by applying muting for a prescribed time only from the point of time of high frequency signal arrival in an FSK receiver. CONSTITUTION:A delay signal (g) goes to an H level while a high frequency signal is being received, resulting that a mute control signal (h) outputted from an AND circuit 19 goes to an H level while a data signal is received after an MPU 17 detects a bit synchronizing signal, the mute switch 12 is opened to apply muting. On the other hand, when the reception of a data signal is finished and the audio signal is received, since a noise squelch control signal (e) and a mute control signal (h) go both to an L level, the mute switches 11, 12 are both closed and the muting is released. As a result, even when a signal similar to the bit synchronizing signal is generated during communication, it is not intermitted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a mute circuit for an FSK receiver in a subcarrier modulation system.

[Conventional technology]

Conventionally, FSK receivers have built-in mute circuits for erasing the data signal sound of the data portion included in the received signal. At this time, the mute circuit is generally configured to operate when a bit synchronization signal in the data signal is detected. In other words, the conventional FS
As the block diagram of the K receiver is shown in FIG. In addition to the mute circuit, a decoder 16, an MPU (microprocessor) 17
and a second mew switch (SW) 12, MP
When U 17 detects a bit synchronization signal in the digital signal supplied from decoder 16, it switches on second mute switch 1.
2 is provided with a second mute circuit that opens the second mute circuit.

By the way, the FSK receiver starts a voice call after receiving data, but depending on the voice signal, a signal similar to a bit synchronization signal may be generated.

Then, the MPU 17 erroneously detects a signal similar to the bit synchronization signal as a bit synchronization signal, and the second mute circuit is activated, resulting in a problem that the call is interrupted.

Therefore, in order to eliminate the above problem, the first step is to select a frequency that does not cause audio malfunctions as a subcarrier.
A second method has been proposed in which the number of bits of the bit synchronization signal to be detected is increased.

[Problem that the invention seeks to solve]

However, in the case of the first method, the voice band of the land mobile station is 300 Hz to 3 kHz, and although it is possible to reduce voice malfunctions depending on how the subcarrier frequency is selected, the subcarrier frequency is Because it is in-band, it cannot be completely prevented, and
In the case of the second method, since the mute operation is delayed, the time during which the data signal sound is generated becomes longer, which goes against the original purpose of the mute circuit, which is to erase the data signal sound.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a mute circuit that prevents malfunctions caused by voices during a call.

[Means for solving problems]

In order to achieve the above object, according to the present invention, as shown in FIG. A high frequency signal detection means A for detecting a signal, a predetermined time setting means B for setting a predetermined time, a bit synchronization signal detection means C for detecting a bit synchronization signal, and a time point when the high frequency signal detection means A detects a high frequency signal. A mute circuit is provided, comprising a control means for opening the switching means E when the bit synchronization signal detection means C detects a bit synchronization signal within a predetermined time set by the predetermined time setting means B. Ru.

[For production]

If the predetermined time set by the predetermined time setting means B is exceeded from the time when the high frequency signal detection means A detects the high frequency signal, that is, from the time when the radio wave arrives, even if the bit synchronization signal detection means C detects the bit synchronization signal, the control The means do not cause the switching means E to open. This results in
Audio malfunctions of the mute circuit are prevented.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a pronk configuration diagram of an FSK receiver to which a first embodiment of the mute circuit according to the present invention is applied. In the figure, 10 indicates a demodulation circuit, and this demodulation circuit 10
demodulates the high frequency signal to an audio frequency, and uses the demodulated audio frequency signal as the demodulated signal d, which is transmitted to the noise squelch circuit 15, the decoder 16, and the first mute switch (S
W) Supply to 11. The noise squelch circuit 15 detects the presence or absence of a high frequency signal from the noise in the supplied demodulated signal d, and when the arrival of the high frequency signal is detected, it outputs a noise squelch control signal of "L" level, and when not detected, it outputs a "H" level noise squelch control signal. e is supplied to the first mute switch 11 and the delay circuit 18.Then, the first mute switch 11 supplies "H3
When the level noise squelch control signal e is supplied, the signal is opened.

Note that the noise squelch circuit 15 corresponds to the high frequency signal detection means A in FIG.

The decoder 16 receives a demodulated signal d supplied from the demodulation circuit 10.
The data signal in the subcarrier contained in the subcarrier is converted into a digital signal and supplied to a microprocessor (MPU) 17. The MPU 17 processes the digital signal supplied from the decoder 16, and when detecting a bit synchronization signal in the digital signal, supplies an "H" level detection signal f to one input terminal of the AND circuit 19 for a predetermined period of time. . Note that the decoder 16 and the MPU 17 correspond to the bit synchronization signal detection means C in FIG.

The delay circuit 18 supplies a delayed signal g obtained by delaying the noise squelch control signal e supplied from the noise squelch circuit 15 by a predetermined time to the other input terminal of the AND circuit 19. This corresponds to the predetermined time setting means B in FIG.

When the AND circuit 19 is supplied with the "H" level detection signal f and the delay signal g to its input terminals, it supplies an "H" level mute control signal that causes the second mute switch (SW) 12 to open it. do. In addition, the AND circuit 19
The second mute switch 12 corresponds to the control means and the switching means E in FIG. 1, respectively.

Reference numeral 13 indicates an AF amplifier, and this AF amplifier 13 amplifies the audio frequency signal supplied from the demodulation circuit 10 via the first mute switch 11 and the second mute switch 12, and outputs it to the speaker 14, causing the speaker 14 to ring. .

In addition, in FIG. 2, the portion surrounded by a broken line is the mute circuit according to the present invention.

Next, the operation of the above configuration will be explained with reference to the timing chart shown in FIG. In addition, in the same figure, (A),
(B) and (C) do not indicate the waveforms of the high frequency signal, data signal, and audio signal, but indicate the presence or absence of these signals.

First, when the receiver is not receiving a high-frequency signal, that is, when only noise is included in the demodulated signal d, as shown in region I of (D), the noise squelch circuit 15 outputs an "H" level signal. Noise squelch control signal 6 ((E
)) is output. As a result, the first mute switch 11 is opened and a mute operation is performed.

Next, when a high frequency signal arrives, the noise squelch circuit 1
5 detects the arrival of a high frequency signal from the demodulated signal d, and sets the noise squelch control signal e it outputs to the "L" level (see (E)). As a result, the first miyu switch 1
1 is closed.

By the way, the high frequency signal is composed of a data signal and an audio signal (see (A), (B), (C), and (D)).
, the data signal (area (D)) is transmitted first. When the MPU 17 detects a bit synchronization signal that constitutes a part of the data signal in the digital signal supplied from the decoder 16, the MPU 17 calculates a predetermined time, that is, the time required for transmitting the data signal, to detect the bit synchronization signal. The “H” level detection signal f(
(F)) is supplied to one input terminal of the AND circuit 19.

The delay signal g is supplied from the delay circuit 18 to the other input terminal of the AND circuit 19, and this delay signal g is determined by the noise squelch control signal e for a predetermined time, which in this embodiment is the time required for transmitting the data signal. It was only delayed. Therefore, as shown in (G), the delayed signal g is at the "H" level at least from the time when the high frequency signal arrives until the time when the reception of the data signal is finished, but after the reception of the data signal is finished, At least while receiving the high frequency signal, the delayed signal g is at "L" level.

As a result, while the MPU 17 is receiving the data signal after detecting the bit synchronization signal, the mute control signal output by the AND circuit 19 becomes "H" level, the second mute switch 12 is opened, and the mute operation is performed. will be held.

As a result, the data signal tone is erased.

Since reception of the data signal is completed and the level of the audio signal ((D) is reached, the first mute switch 11 and the second
Both mute switches 12 are closed and the mute operation is released. As a result, voice communication becomes possible. Moreover,
For example, point 1. Even if the MPU 17 erroneously detects the audio signal as a bit synchronization signal and outputs an "H" level detection signal (see (F)), the mute control signal will be "L" since the delayed signal g is at the "L" level. Therefore, the second mute switch 12 remains closed, so the voice call is not interrupted.

A specific example of the delay circuit 18 is shown in FIG. The delay circuit shown in FIG. 4 is a known one.

FIG. 5 is a block diagram of an FSK receiver to which a second embodiment of the present invention is applied. In this second embodiment, the operations of the delay circuit 18 and AND circuit 19 of the first embodiment shown in FIG. 2 are processed by a program of the MPU 27. It should be noted that throughout the discussion, identical or equivalent parts are provided with the same reference numerals. Furthermore, the portion surrounded by the broken line is the mute circuit according to the present invention.

The mute operation of the MPU 27 used in the second embodiment shown in FIG. 5 will be described below with reference to the flowchart shown in FIG.

First, in step 601, the noise squelch circuit 1
Based on the noise squelch control signal supplied from 5, it is determined whether or not a high frequency signal is sensed, and the determination result is positive.
If YES), that is, when a high frequency signal is sensed, the process proceeds to step 602; if NO, the process returns and waits.

In step 602, the internal timer in MPtl 27 is reset to 1-0 and timing is started at the same time.

Next, the process proceeds to step 603, in which it is determined whether or not a bit synchronization signal is detected in the digital signal supplied from the decoder 16. If the determination result is affirmative, that is, if a bit synchronization signal is detected, the process proceeds to step 604. On the other hand, if the answer is negative, the process returns to step 601.

In step 604, it is determined whether the elapsed time t since the internal timer started timing, in other words, the elapsed time t+ from the time when the bit synchronization signal was detected, is less than a predetermined time t0, and if the determination result is affirmative. In other words, when the elapsed time t is less than the predetermined time t0, the process proceeds to step 605, and a mute operation is performed in which a 1H'' level control signal is output to the second mute switch 12. The time required to detect the bit synchronization signal is subtracted from the time required to detect the bit synchronization signal.
As described in the description of the first embodiment above, it is possible to set it in advance.

Next, in step 606, it is determined whether the elapsed time t has reached the predetermined time t0, and if the determination result is negative, that is, if the elapsed time t has not reached the predetermined time t, the process returns to step 605, Continue mute operation. This erases the data signal tone. and,
When the elapsed time t reaches the predetermined time t0 (step 606
(if the determination result is affirmative), the process advances to step 607 and the mute operation is canceled.

Next, proceeding to step 608, it is determined whether or not there is a high frequency signal, and if the determination result is affirmative, that is, when a high frequency signal is being received, it is determined that a voice call is in progress,
The process returns to step 607 to continue canceling the mute operation. This prevents the mute operation from occurring during a voice call. On the other hand, if the determination result in step 608 is negative, it is determined that the call has ended, and the process returns to step 601.

Note that if the determination result in step 604 is negative, the process advances to step 607.

〔Effect of the invention〕

As explained above, according to the mute circuit of the present invention,
Since the mute operation is performed only for a predetermined period of time from the arrival of the high-frequency signal, it is possible to prevent malfunctions caused by voices during a call.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block configuration diagram of an FSK receiver to which the first embodiment of the present invention is applied, Fig. 3 is a timing chart, and Fig. 4 is a delay circuit diagram. A specific circuit diagram, FIG. 5 is a block configuration diagram of an FSK receiver to which the second embodiment of the present invention is applied, FIG. 6 is a flowchart, and FIG. 7 is a diagram to which a conventional mute circuit is applied. FIG. 2 is a block configuration diagram of an FSK receiver. 14...Speaker, 17, 27...Microprocessor (MPU), 1
9...AND circuit. Flowchart Figure 6

Claims (1)

[Claims] 1. A mute circuit for an FSK receiver, which includes switching means for opening and closing a transmission path for audio frequency signals, high-frequency signal detection means for detecting high-frequency signals, and setting a predetermined time. a bit synchronization signal detection means for detecting a bit synchronization signal; and a bit synchronization signal detection means for detecting a bit synchronization signal within a predetermined time set by the predetermined time setting means from the time when the high frequency signal detection means detects the high frequency signal. A mute circuit comprising: control means for opening the switching means when the detection means detects a bit synchronization signal.