JPS63202017U - - Google Patents
Info
- Publication number
- JPS63202017U JPS63202017U JP9365487U JP9365487U JPS63202017U JP S63202017 U JPS63202017 U JP S63202017U JP 9365487 U JP9365487 U JP 9365487U JP 9365487 U JP9365487 U JP 9365487U JP S63202017 U JPS63202017 U JP S63202017U
- Authority
- JP
- Japan
- Prior art keywords
- patterns
- guard
- signal source
- output line
- line side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011159 matrix material Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 1
Landscapes
- Keying Circuit Devices (AREA)
Description
第１図は本考案に係る信号切替装置の要部断面
を示した図、第２図は第１図の装置を上面から見
た電気的接続図、第３図は第２図におけるリレー
の接続を示す図、第４図は６線式伝送方式を説明
するための図、第５図と第６図は従来の信号切替
装置を説明するための図、第７図は本考案の別の
構成例を示す図である。
１０……信号源、３０……信号切替装置、ＧＰ
……ガードパターン、ＧＤ……ガード電極、Ｓ…
…センスパターン、Ｆ……フオーカスパターン。
Figure 1 is a cross-sectional view of the main parts of the signal switching device according to the present invention, Figure 2 is an electrical connection diagram of the device in Figure 1 seen from above, and Figure 3 is the connection of the relay in Figure 2. FIG. 4 is a diagram for explaining the 6-wire transmission system, FIGS. 5 and 6 are diagrams for explaining the conventional signal switching device, and FIG. 7 is another configuration of the present invention. It is a figure which shows an example. 10... Signal source, 30... Signal switching device, GP
...Guard pattern, GD...Guard electrode, S...
...Sense pattern, F...Focus pattern.
Claims (1)
、複数本の出力線のそれぞれに切替えて接続する
マトリクス構造をした信号切替装置において、 左右にガードパターンが形成された多数本の信
号源側のパターンを多層プリント板の内層に設け
、この信号源側のパターンとガードパターンが設
けられた層の上下の層をガード電極とし、 更に、この多層プリント板の別の内層へ左右に
ガードパターンが形成された多数本の出力線側の
パターンを設け、この出力線側のパターンとガー
ドパターンが設けられた層の上下の層をガード電
極とし、 前記信号源側のパターンと出力線側のパターン
が立体交差する各位置に信号源側のパターンと出
力線側のパターンの接続をオン・オフするリレー
手段を設けた信号切替装置。[Claim for Utility Model Registration] In a signal switching device with a matrix structure that switches and connects each of a plurality of signals output from a signal source to each of a plurality of output lines, guard patterns are formed on the left and right sides. A large number of signal source side patterns are provided on the inner layer of a multilayer printed board, the layers above and below the layer on which the signal source side patterns and guard patterns are provided are used as guard electrodes, and furthermore, another inner layer of this multilayer printed board is provided. A large number of output line side patterns with guard patterns formed on the left and right sides are provided, and the output line side patterns and the layers above and below the layer on which the guard patterns are provided are used as guard electrodes, and the signal source side patterns and A signal switching device that is provided with a relay means for turning on/off the connection between the signal source side pattern and the output line side pattern at each position where the output line side patterns intersect.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9365487U JPS63202017U (en) | 1987-06-18 | 1987-06-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9365487U JPS63202017U (en) | 1987-06-18 | 1987-06-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63202017U true JPS63202017U (en) | 1988-12-27 |
Family
ID=30956411
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9365487U Pending JPS63202017U (en) | 1987-06-18 | 1987-06-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63202017U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998057282A1 (en) * | 1997-06-13 | 1998-12-17 | Hitachi, Ltd. | Semiconductor integrated circuit for verification, circuit simulator, and circuit simulation method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50100906A (en) * | 1973-12-31 | 1975-08-11 | ||
| JPS53132773A (en) * | 1977-04-25 | 1978-11-18 | Hitachi Ltd | Multilayer circuit board |
-
1987
- 1987-06-18 JP JP9365487U patent/JPS63202017U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50100906A (en) * | 1973-12-31 | 1975-08-11 | ||
| JPS53132773A (en) * | 1977-04-25 | 1978-11-18 | Hitachi Ltd | Multilayer circuit board |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998057282A1 (en) * | 1997-06-13 | 1998-12-17 | Hitachi, Ltd. | Semiconductor integrated circuit for verification, circuit simulator, and circuit simulation method |
| WO1998057281A1 (en) * | 1997-06-13 | 1998-12-17 | Hitachi, Ltd. | Semiconductor integrated circuit for inspection, circuit simulator and circuit simulation method |