JPS631994A - Time control circuit of digital time-piece - Google Patents

Time control circuit of digital time-piece

Info

Publication number
JPS631994A
JPS631994A JP14531786A JP14531786A JPS631994A JP S631994 A JPS631994 A JP S631994A JP 14531786 A JP14531786 A JP 14531786A JP 14531786 A JP14531786 A JP 14531786A JP S631994 A JPS631994 A JP S631994A
Authority
JP
Japan
Prior art keywords
time
vdd
switch
feed
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14531786A
Other languages
Japanese (ja)
Inventor
Kenji Tanaka
賢治 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP14531786A priority Critical patent/JPS631994A/en
Publication of JPS631994A publication Critical patent/JPS631994A/en
Pending legal-status Critical Current

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  • Electric Clocks (AREA)

Abstract

PURPOSE:To obtain an inexpensive time control circuit capable of freely determining the arrangement of switches, by making a slow feed crown type switch and a quick feed push button type switch respectively independent and connecting both of them to the time control input terminal of the clock circuit of each switch. CONSTITUTION:When a control signal is inputted to the time control input terminal 1a of a clock circuit 1 and a VDD level is set at an advance slow feed time and a VSS level is set at a rearward slow feed time, the display times of a display device 2 respectively change every 1min. Further, at an advance quick feed time, an AC signal of a -VDD/2 level is inputted on the basis of VDD and, at a rearward quick feed time, an AC signal of the -VDD/2 level is inputted on the basis of VSS. Whereupon, displays respectively change in a quick feed manner. At a slow feed control time, the VDD and VSS levels are applied to the terminal 1a by a crown type switch 3 and advance quick feed control is performed by inputting the AC signal set by resistors 5a, 5b, 5c by a push button switch 4. By this constitution, the time control circuit of a digital time-piece is formed inexpensively and the arrangement of each switch can be freely selected.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、ディジタル時計の時刻調整回路に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a time adjustment circuit for a digital watch.

従来の技術 従来、ディジタル時計の時刻調整回路は、時刻調整用リ
ューズ式スイッチに時刻早送り用押しボタン式スイッチ
が一体化されたものを使用するものであり、また、時刻
調整用リューズ式スイッチがない回路については押しボ
タン式スイッチのみで早送り(前進・後進)、緩送り(
前進・後進)2へ−7 の回路を構成して時刻調整をするようにしていた。
Conventional technology Conventionally, the time adjustment circuit of a digital watch uses a crown-type switch for adjusting the time and a push-button switch for fast forwarding the time, and there is no crown-type switch for adjusting the time. Regarding the circuit, fast forward (forward/reverse) and slow forward (
Forward/reverse) 2 to 7 circuits were configured to adjust the time.

発明が解決しようとする問題点 ところが、このような従来の時刻調整回路は、押しボタ
ン式スイッチを一体化したリューズ式スイッチは、部品
構造が非常に複雑なために部品コストが非常に高くなる
ので、時刻調整回路全体のコストも高くなるという欠点
があった。−方、後者の場合は緩送り(前進・後進)を
押しボタン式スイッチで構成するためにリューズ式スイ
ッチに比べて緩送り(前進・後進)の調整がしにくいと
いう欠点を有1〜でいた。
Problems to be Solved by the Invention However, in such conventional time adjustment circuits, the crown-type switch that integrates the push-button switch has a very complicated component structure, resulting in extremely high component costs. However, there was a drawback that the cost of the entire time adjustment circuit was also high. - On the other hand, in the latter case, since the slow feed (forward/backward) is configured with a push button switch, it has the disadvantage that it is difficult to adjust the slow feed (forward/backward) compared to a crown type switch. .

そこで、本発明はこのような従来の問題点を解決するも
のであり、緩送り(前進・後進)はリューズ式スイッチ
により、早送り(前進)は押しボタン式スイッチにより
形成し、コスト的にも安価で、調整のし易い非常に優れ
た時刻調整回路を提供するものである。
Therefore, the present invention solves these conventional problems. Slow feed (forward/backward) is controlled by a crown-type switch, and rapid feed (forward) is controlled by a push-button switch, which is also inexpensive in terms of cost. This provides an excellent time adjustment circuit that is easy to adjust.

問題点を解決するだめの手段 本発明のディジタル時計用時刻調整回路は、緩送り(前
進・後進)はリューズ式スイッチにより、3ヘ−ノ 早送り(前進)はリューズ式スイッチから独立した押し
ボタン式スイッチにより夫々構成したものである。
Means to Solve the Problem The time adjustment circuit for a digital watch of the present invention uses a crown type switch for slow movement (forward/reverse), and a push button type independent from the crown type switch for rapid movement (forward). Each of these is configured by a switch.

作  用 本発明のディジタル時計用時刻調整回路は、早送りを独
立した押しボタン式スイッチにしたことにより、ボタン
を2個つけることが可能になり、2個のボタン式スイッ
チで早送り(前進)と早送シ(後進)の両方を設定する
こともできる。
Function: The time adjustment circuit for a digital watch of the present invention uses an independent push-button switch for fast-forwarding, making it possible to attach two buttons, and the two button-type switches can be used to control fast-forward (forward) and fast-forward. It is also possible to set both forward and backward movement.

実施例 以下、本発明の一実施例のディジタル時計の時刻調整回
路を図面を参照して説明する。
Embodiment Hereinafter, a time adjustment circuit for a digital clock according to an embodiment of the present invention will be explained with reference to the drawings.

図において、1はディジタル時計回路であり、この時計
回路1により時刻表示器2に現在時刻・アラーム時刻等
が表わされる。そして、この表示器2の時刻を任意の時
刻に説定するときには、時計回路1の時刻調整入力端子
1aに制御信号を入力する。その制御信号は、前進の緩
送り時にはvDD レベルを、後進の緩送り時にはvs
s レベルを時計回路1の時刻調整入力端子1aに入力
すると、表示時刻が1分ずつ夫々変化する。さらに前進
の早送り時にrqvpD を基準として−vDD/2レ
ベルの交流信号を、後進の早送り時にはvssを基準と
して−VDD/2レベルの交流信号を入力すると時刻が
夫々早送り状態で変化する。本回路では、緩送り調整に
対しては、リューズ式スイッチ3により、vDD及びv
ss レベルを夫々時計回路1の時刻調整入力端子1a
に入力し、前進の早送り調整は押しボタン式スイッチ4
により抵抗Ra、R,、Roで設定された交流信号を時
計回路1の時刻調整入力端子19に入力して調整を行な
うように構成しである。
In the figure, 1 is a digital clock circuit, and this clock circuit 1 displays the current time, alarm time, etc. on a time display 2. When setting the time on the display 2 to an arbitrary time, a control signal is input to the time adjustment input terminal 1a of the clock circuit 1. The control signal is set to the vDD level during slow forward movement and to the vs level during slow backward movement.
When the s level is input to the time adjustment input terminal 1a of the clock circuit 1, the displayed time changes by one minute. Furthermore, when an AC signal of -vDD/2 level is inputted with reference to rqvpD during forward fast-forwarding, and an AC signal of -VDD/2 level is inputted with vss as a reference during reversed fast-forwarding, the time changes in the fast-forwarding state. In this circuit, for slow feed adjustment, vDD and v
ss level respectively to the time adjustment input terminal 1a of the clock circuit 1.
For forward fast-forward adjustment, use push-button switch 4.
The AC signal set by the resistors Ra, R, . . . Ro is input to the time adjustment input terminal 19 of the clock circuit 1 for adjustment.

発明の効果 以上のように本発明の時刻調整回路は、緩送りリューズ
式スイッチと早送り用押しボタン式スイッチを夫々独立
して構成し、各々のスイッチ時計回路の時刻調整入力端
子に接続したのでコスト的にも非常に安価に作成出来、
夫々のスイッチの配置を自由に決定出来るという面から
も極めて優れたものである。
Effects of the Invention As described above, the time adjustment circuit of the present invention has a slow-forwarding crown-type switch and a fast-forwarding push-button switch independently configured, and each switch is connected to the time adjustment input terminal of the clock circuit, thereby reducing costs. It can be made very cheaply,
It is also extremely superior in that the arrangement of each switch can be freely determined.

5ヘ一75-7

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明の時刻調整回路の一実施例を示す回路図であ
る。 1・・・時計回路、2・・時刻表示器、3−・・リュー
ズ式スイッチ、4・・・・・押しボタン式スイッチ、5
a、6b、5cm抵抗器。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名3−
 リューズ式スイッチ
The figure is a circuit diagram showing an embodiment of the time adjustment circuit of the present invention. 1... Clock circuit, 2... Time display, 3-... Crown type switch, 4... Push button type switch, 5
a, 6b, 5cm resistor. Name of agent: Patent attorney Toshio Nakao and 1 other person3-
crown switch

Claims (1)

【特許請求の範囲】[Claims] 時刻調整用リユーズ式スイッチと時刻早送り用押しボタ
ン式スイッチを夫々独立したスイッチとして構成し、上
記両スイッチを時計回路の時刻調整用入力端子に接続し
たディジタル時計の時刻調整回路。
A time adjustment circuit for a digital watch, in which a reuse-type switch for time adjustment and a push-button type switch for fast-forwarding the time are configured as independent switches, and both of the switches are connected to a time adjustment input terminal of a clock circuit.
JP14531786A 1986-06-20 1986-06-20 Time control circuit of digital time-piece Pending JPS631994A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14531786A JPS631994A (en) 1986-06-20 1986-06-20 Time control circuit of digital time-piece

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14531786A JPS631994A (en) 1986-06-20 1986-06-20 Time control circuit of digital time-piece

Publications (1)

Publication Number Publication Date
JPS631994A true JPS631994A (en) 1988-01-06

Family

ID=15382363

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14531786A Pending JPS631994A (en) 1986-06-20 1986-06-20 Time control circuit of digital time-piece

Country Status (1)

Country Link
JP (1) JPS631994A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05249730A (en) * 1991-12-23 1993-09-28 Xerox Corp Toner composition
US5508139A (en) * 1993-03-25 1996-04-16 Canon Kabushiki Kaisha Magnetic toner for developing electrostatic image
US6013405A (en) * 1997-02-07 2000-01-11 Kabushiki Kaisha Toshiba Developing agent and developing device using the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05249730A (en) * 1991-12-23 1993-09-28 Xerox Corp Toner composition
US5508139A (en) * 1993-03-25 1996-04-16 Canon Kabushiki Kaisha Magnetic toner for developing electrostatic image
US6013405A (en) * 1997-02-07 2000-01-11 Kabushiki Kaisha Toshiba Developing agent and developing device using the same

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