JPS63199322U - - Google Patents
Info
- Publication number
- JPS63199322U JPS63199322U JP8740487U JP8740487U JPS63199322U JP S63199322 U JPS63199322 U JP S63199322U JP 8740487 U JP8740487 U JP 8740487U JP 8740487 U JP8740487 U JP 8740487U JP S63199322 U JPS63199322 U JP S63199322U
- Authority
- JP
- Japan
- Prior art keywords
- auto power
- timer
- storage section
- section
- control device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 1
Landscapes
- Power Sources (AREA)
- Facsimiles In General (AREA)
Description
第1図は本考案の一実施例を示すオートパワー
オフ制御部のブロツク図、第2図はオートパワー
オフ時間変更操作時の表示画面を示す図、第3図
は実施例のタイマ制御回路の特徴的機能であるオ
ートパワーオフ時間変更処理の動作を示すフロー
チヤート、第4図は本考案の他の実施例を示すオ
ートパワーオフ制御部のブロツク図、第5図はオ
ートパワーオフ時刻変更操作時の表示画面を示す
図、第6図は従来のFAX装置を備えたWPを示
す斜視図、第7図はその内部ブロツク図、第8図
は従来のオートパワーオフ機能の動作原理を示す
図である。
51:バツテリ、52:電源回路、53:パワ
ーオフ制御回路、54A,54B:タイマ制御回
路、55:タイマ用カウント記憶部、55A:タ
イマカウント設定値記憶部、55B:時刻設定値
記憶部、56:クロツク発振器、56A:日付時
刻記憶部、57:入力制御部、58:入力装置。
Fig. 1 is a block diagram of an auto power-off control section showing an embodiment of the present invention, Fig. 2 is a diagram showing a display screen during auto power-off time changing operation, and Fig. 3 is a diagram of a timer control circuit of the embodiment. A flowchart showing the operation of the auto power-off time changing process, which is a characteristic function, FIG. 4 is a block diagram of the auto power-off control section showing another embodiment of the present invention, and FIG. 5 is an auto power-off time changing operation. 6 is a perspective view showing a WP equipped with a conventional FAX device, FIG. 7 is an internal block diagram thereof, and FIG. 8 is a diagram showing the operating principle of a conventional auto power off function. It is. 51: battery, 52: power supply circuit, 53: power-off control circuit, 54A, 54B: timer control circuit, 55: timer count storage section, 55A: timer count setting value storage section, 55B: time setting value storage section, 56 : clock oscillator, 56A: date and time storage section, 57: input control section, 58: input device.
Claims (1)
パワーオフ動作を行うオートパワーオフ制御装置
において、前記タイマの動作時間または動作時刻
を設定する入力部と、該入力部から入力された設
定値を記憶する記憶部と、該記憶部に記憶された
設定値に基づいて、オートパワーオフ動作を実行
する如く制御する制御手段を設けたことを特徴と
するオートパワーオフ制御装置。 An auto power-off control device that uses a timer to perform an auto power-off operation after a preset time, which includes an input section for setting the operating time or operating time of the timer, and a setting value input from the input section. An auto power-off control device comprising: a storage section; and a control means for controlling execution of an auto power-off operation based on the setting values stored in the storage section.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8740487U JPS63199322U (en) | 1987-06-05 | 1987-06-05 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8740487U JPS63199322U (en) | 1987-06-05 | 1987-06-05 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63199322U true JPS63199322U (en) | 1988-12-22 |
Family
ID=30944583
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8740487U Pending JPS63199322U (en) | 1987-06-05 | 1987-06-05 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63199322U (en) |
-
1987
- 1987-06-05 JP JP8740487U patent/JPS63199322U/ja active Pending
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