JPS63194330A - Method for exposing semiconductor - Google Patents

Method for exposing semiconductor

Info

Publication number
JPS63194330A
JPS63194330A JP62026280A JP2628087A JPS63194330A JP S63194330 A JPS63194330 A JP S63194330A JP 62026280 A JP62026280 A JP 62026280A JP 2628087 A JP2628087 A JP 2628087A JP S63194330 A JPS63194330 A JP S63194330A
Authority
JP
Japan
Prior art keywords
wafer
light
pattern
resist
incident
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62026280A
Other languages
Japanese (ja)
Inventor
Yoshitada Oshida
良忠 押田
Naoto Nakajima
直人 中島
Yoshihiro Yoneyama
米山 義弘
Toshihiko Nakada
俊彦 中田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62026280A priority Critical patent/JPS63194330A/en
Publication of JPS63194330A publication Critical patent/JPS63194330A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073Alignment marks and their environment
    • G03F9/7076Mark details, e.g. phase grating mark, temporary mark

Abstract

PURPOSE:To realize an alignment accuracy of about 0.2 mum or less and to improve the yield of producing LSI's having a line width of submicron order, by applying P-polarized light to a wafer on which resist is applied, the P- polarized light being incident at a Brewster angle with respect to the resist surface. CONSTITUTION:A target mark 21 is formed on a wafer 2 in repeated pattern having a width of 6 mum and a pitch of 1.4 mum, for example. P-polarized light which is incident at a Brewster angle with respect to the pattern is applied against the target. For the purpose of obtaining high directivity, laser beams are used. Since all the P-polarized light incident at a Brewster angle is transmit ted, no light is reflected from the resist surface while reflected light represents uneven configurations of the wafer target pattern. If the resist surface is uneven, the reflected light from the target mark performs change in phase corresponding to variances in thickness of the resist but it does not present an extremely asymmetrical waveform. Thus, the pattern position can be detected with high precision.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、マスクとウェハとをアライメントしてマスク
上の回路パターンをウェハ上に正確に重ね露光するため
の半導体露光方法に係り、特にウェハ上に塗布されたレ
ジストの塗布むらに対して好適な半導体露光方法に閃す
る。
Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor exposure method for aligning a mask and a wafer to accurately overlay and expose a circuit pattern on the mask onto the wafer. A semiconductor exposure method suitable for dealing with uneven coating of a resist coated on top was discovered.

〔従来の技術〕[Conventional technology]

従来の半導体露光方法としては、特開昭60−9862
5号公報が知られている。
As a conventional semiconductor exposure method, Japanese Patent Application Laid-Open No. 60-9862
Publication No. 5 is known.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

半導体の回路パターンの焼付けは主に縮小露光装置を用
いて行なわれるが、広い露光領域を高解像で低歪に露光
するため、縮小レンズはスペクトル幅の狭い光に対して
のみ解像する。従って広帯域のスペクトル光に対しては
色収差が発生し、解像度が極端に低減する。このため、
マスクとウェハの位置合せのためのアライメントに用い
る光も狭スペクトルにせざるを得ない。しかるに狭スペ
クトルの元でウェハのパターンを検出すると、つエバの
アライメント用ターゲットマークと+(7)上に塗布さ
れたレジストの表面の間で多重干渉が発生ずる。他方近
年半導体の生産歩留りを向上するため1益々大口径のウ
ェハな用いるようになっている0所がウェハの口径が大
きくなると、レジストをウェハに一様に塗布することが
益々難しくなっており、特に、ターゲットマークの段差
部に対し対称なレジスト厚とならず、多重干渉により、
ターケラトマーク検出信号に非対称性が生じアライメン
ト精度が低下してしまう。第2図はこの現象企説明した
図であり、ターゲットマーク21のABC点に於るレジ
スト膜厚がto、 d+、 do+Δdにな恨A点と0
点で塗布むらによる膜厚差が生じている場合、第2図C
b)に示すように検出波形はA点と0点で非対称になる
。このためパターンの中心が検出できなくなり、アライ
メント精度が低下する。
Printing of semiconductor circuit patterns is mainly performed using a reduction exposure device, but in order to expose a wide exposure area with high resolution and low distortion, the reduction lens resolves only light with a narrow spectral width. Therefore, chromatic aberration occurs for broadband spectral light, and the resolution is extremely reduced. For this reason,
The light used for alignment for aligning the mask and wafer must also have a narrow spectrum. However, when a wafer pattern is detected under a narrow spectrum, multiple interference occurs between the alignment target mark of the evaporator and the surface of the resist coated on +(7). On the other hand, in recent years, in order to improve semiconductor production yields, increasingly larger diameter wafers have been used.As the diameter of the wafer increases, it becomes increasingly difficult to apply resist uniformly to the wafer. In particular, the resist thickness is not symmetrical with respect to the step part of the target mark, and due to multiple interference,
Asymmetry occurs in the Turkerato mark detection signal, resulting in a decrease in alignment accuracy. Figure 2 is a diagram explaining this phenomenon, and shows that the resist film thickness at point ABC of target mark 21 is to, d+, do+Δd, and point A and 0.
If there is a difference in film thickness due to uneven coating at points, see Figure 2 C.
As shown in b), the detected waveform becomes asymmetric between point A and point 0. As a result, the center of the pattern cannot be detected, resulting in a decrease in alignment accuracy.

このように上記従来技術ではレジスト膜厚が1塗布むら
によりパターンの両サイドで非対称となるため、多重干
渉により干渉強度がわずかな膜厚で急激に変化する事に
より、問題が生じている。
As described above, in the above-mentioned conventional technology, since the resist film thickness becomes asymmetric on both sides of the pattern due to one coating unevenness, a problem arises because the interference intensity changes rapidly with a small film thickness due to multiple interference.

本発明の目的はこのわずかな塗布むらの変化に対し干渉
強度が変化することを回避し、塗布むらの影響を受けに
くい検出を実塊し、 マスクとウェハとをアライメント
してマスク上の回路パターンをウェハ上に露光する半導
体露光方法を提供することにある。
The purpose of the present invention is to avoid changes in interference intensity due to slight changes in coating unevenness, to perform detection that is less susceptible to coating unevenness, and to align the mask and wafer to detect circuit patterns on the mask. An object of the present invention is to provide a semiconductor exposure method for exposing a wafer.

〔問題点ご解決するための手段〕[Means for solving problems]

上記目的は、レジストを塗布したウェハに照明する光を
レジスト面に対し、ブリュースタ角で入射し、しかもこ
の入射光をP偏光で入射することにより、レジスト表面
で直接反射する反射光ヲ。
The above object is to make the light that illuminates a wafer coated with resist enter the resist surface at Brewster's angle, and to make the incident light incident as P-polarized light, thereby producing reflected light that is directly reflected on the resist surface.

レベルにし、ウェハ上のパターン部で反射する光のみを
取り出丁ことにより、達成される。
This is achieved by leveling the wafer and extracting only the light reflected by the pattern on the wafer.

〔作用〕[Effect]

ウェハに対しブリュースタ角で入射したP偏光501は
第3図に示すように、レジスト表面で直接反射する光5
02′はほぼ0レベルになる。第3図<b>は入射角と
偏光状態により、反射光の相対振幅がどのようになるか
ご示したものであり、レジストの屈接率約17に対し、
プリー−スタ角は約600 に−なる。レジスト表面で
の反射がないため、反射光成分は総てターゲットマーク
の表面で反射したものとなり、塗布むらの影響が大幅に
低減する。
As shown in FIG. 3, P-polarized light 501 incident on the wafer at Brewster's angle becomes light 5 directly reflected on the resist surface.
02' becomes almost 0 level. Figure 3<b> shows how the relative amplitude of reflected light changes depending on the incident angle and polarization state.
The Priest angle is approximately 600 degrees. Since there is no reflection on the resist surface, all reflected light components are reflected on the surface of the target mark, and the influence of coating unevenness is significantly reduced.

〔実施例〕〔Example〕

以下、本発明の一実施例を第1図を用いて説明する。第
11Aで1は回路パターンの原画となるマスク(レチク
ル)である。マスクのパターンは縮小レンズ3によりウ
ェハ2の上に結像する。4は露光光源であり、ここを出
射した光はマスクを照明し、透過光がウェハ上にマスク
の権小パターンとして結像、露光する。半導体集積回路
ご作るには、何種ものパターン企ウェハに焼付け、現像
、エツチング等の工程を経る。この重ね合せ露光を償度
良く酢なうにはマスク1上の合せマーク11とウェハ上
の合せマーク(ターゲットマーク)21の相対位af正
確に求め、ウェハをテーブル7により所定の位置に追い
込む必要がある。ウェハ2上のターゲットマーク21は
第1d(b)に示すように、j喘6μm1ピッチ14μ
mの繰返しパターンとする。このパターンに対し第1図
(C)のウェハの段面図(側面図)に示すように1人射
角がブリュースタ角のP偏光をターゲットに照射する。
An embodiment of the present invention will be described below with reference to FIG. In the 11th A, 1 is a mask (reticle) that is the original image of the circuit pattern. The pattern of the mask is imaged onto the wafer 2 by a reducing lens 3. Reference numeral 4 denotes an exposure light source, and the light emitted from this illuminates the mask, and the transmitted light forms an image on the wafer as a small pattern of the mask and exposes it. To make semiconductor integrated circuits, a number of different patterns are printed on wafers, developed, and etched, among other steps. In order to achieve this overlapping exposure with good compensation, it is necessary to accurately determine the relative position af between the alignment mark 11 on the mask 1 and the alignment mark (target mark) 21 on the wafer, and to drive the wafer to a predetermined position using the table 7. be. The target mark 21 on the wafer 2 has a pitch of 6 μm and a pitch of 14 μm, as shown in 1d(b).
m repeating pattern. For this pattern, the target is irradiated with P-polarized light having a Brewster angle as shown in the step view (side view) of the wafer in FIG. 1(C).

このような指向性の高い光を照射するため、照明光には
レーザ光が用いられる。ブリエースター角で入射するP
偏光は、総て透過するため、レジスト表面からの反射が
ない、ウェハターゲットパターンの段差形状に忠実な反
射光が得られる。当然のことながらレジスト表面が凹凸
をしている場合には、この膜厚変化に応じた位相変化が
、ターゲットマーク反射光に乗って来るが、従来の多重
反射信号(第2図(b))のような検出1J号レベルの
大1帰に大きな非対称波形とはならない。即ちΔdの塗
布むらに対する位相変化Δφは 2π Δφ=7(ルー1)Δd となるのに対し、多重干渉強度は次式△φ工の位相変化
に対する強度変化△■を受ける ΔI=−6ルΔφ工 即ち△φと△φ上では概ね位相変化の比がrL−1=2
rL−となりn=1.7とすると0.7 : 3.4と
なり、膜厚変化に対する影響は約/に低減される。この
ように膜4変化に対し影9の小さい反射光が得られるが
、ブリュースタ角θBは通常50°〜60°と大きいた
め、第1図に示すように1縮小レンズ3の雛31に正反
射光502は入射しない。そこで、ターゲットマークに
第1図(h)に示すような、微細な繰返しパターンを設
け、その回折光(1次光或いは2次光以上の光)を用い
瞳31を通過させる。瞳31を通過した検出光はレチク
ル1又はこの近傍(色収差がある場合)に俄を結ぶので
、この光を1−チクル1で反射させ検出?35に導き、
ウェハ回折像を検出する。
In order to irradiate such highly directional light, laser light is used as the illumination light. P incident at Briester angle
Since all polarized light is transmitted, reflected light that is faithful to the step shape of the wafer target pattern without reflection from the resist surface can be obtained. Naturally, if the resist surface is uneven, a phase change corresponding to this film thickness change will be carried on the target mark reflected light, but the conventional multiple reflection signal (Figure 2 (b)) It does not result in a large asymmetric waveform at the detection level 1J level such as . In other words, the phase change Δφ due to coating unevenness of Δd is 2π Δφ=7(ru 1) Δd, whereas the multiple interference intensity is ΔI=−6 Δφ which undergoes the intensity change Δ■ with respect to the phase change of Δφ In other words, on △φ and △φ, the ratio of phase change is approximately rL−1=2
When rL- and n=1.7, the ratio becomes 0.7:3.4, and the influence on the film thickness change is reduced to about /. In this way, a reflected light with a small shadow 9 can be obtained with respect to the change in the film 4, but since the Brewster angle θB is usually as large as 50° to 60°, the chick 31 of the 1-reducing lens 3 is Reflected light 502 is not incident. Therefore, the target mark is provided with a fine repeating pattern as shown in FIG. The detection light that has passed through the pupil 31 connects to the reticle 1 or its vicinity (if there is chromatic aberration), so this light is reflected by the 1-ticle 1 and detected. lead to 35,
Detect the wafer diffraction image.

検出される像は繰返しパターンのある部分は明るく、他
は暗くなる。しかもパターン近傍に塗布エラがあっても
そのために第2図(b)に示すような検出1g号の大き
な非対称変化は発生せず、精度の高いパターン位置検出
が可能となる。
The detected image is bright in some parts of the repeating pattern and dark in other parts. Moreover, even if there is a coating error in the vicinity of the pattern, a large asymmetrical change in the detection number 1g as shown in FIG. 2(b) does not occur due to this error, making it possible to detect the pattern position with high accuracy.

第4図は本発明の他の実施例である。ウェハターゲット
マークは第4図(h)に示す棒状の長いマークである。
FIG. 4 shows another embodiment of the invention. The wafer target mark is a long bar-shaped mark shown in FIG. 4(h).

このマークに第4図(b) (0)に示すようにブリー
−スタ角でP偏光で照射し、散乱光を検出する。第4図
の部品に付けた数字と第1図の部品の数字が一致するも
のは同一物を表わす。第1図第4図ともパターン検出器
が1つだけ示してあり・第1図はy方向検出用第4図は
2方向検出用であるが、ともに2方向を検出するため2
つあり、一方はそれぞれの図中で省略されている。第4
図の実施例ではパターンエツジ部が明るく他は暗く検出
されるが、この場合にもレジスト表面での反射はなく、
高精度検出が実現される。
This mark is irradiated with P-polarized light at a breaster angle as shown in FIG. 4(b)(0), and the scattered light is detected. If the numbers attached to the parts in FIG. 4 match those of the parts in FIG. 1, they represent the same thing. Only one pattern detector is shown in both Figures 1 and 4. Figure 1 is for y-direction detection, and Figure 4 is for two-direction detection.
One is omitted in each figure. Fourth
In the example shown in the figure, the edge of the pattern is bright and the rest is dark, but in this case as well, there is no reflection on the resist surface.
High precision detection is achieved.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれは、レーザ照明光のレ
ジスト表面での反射が0となり、ウェハターゲットマー
クの段差情報がより正rイt <こ検出できるようにな
る。この結果従来レジスト塗布むらのために合せ精度が
0.25μm以上となり、極端な場合、0.4μm以上
となっていたものが、o、2μm以内に合せることが可
能となった。この結果、サブミクロンのライン1陽のL
SIの生産歩留りを大幅に同上することが可能となった
As explained above, according to the present invention, the reflection of the laser illumination light on the resist surface becomes zero, and the step information of the wafer target mark can be detected more accurately. As a result, the alignment accuracy, which conventionally was 0.25 μm or more due to resist coating unevenness, and in extreme cases was 0.4 μm or more, can now be adjusted to within 2 μm. As a result, L of submicron line 1
It has become possible to significantly increase the production yield of SI.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す図、第2図は従来の検
出法における信号の出方を示す原理図、第5図は本発明
の検出の基本原理を示す反射光についての説明図、第4
図は本発明の他の実施例図である。 1・・・マスク、      2・・・ウエノ)、21
・・・ウェハターゲットマーク1 3・・・縮小レンズ、    4・・・照明光源15・
・・パターン検出器。 一一ノ′
Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is a principle diagram showing how a signal is output in a conventional detection method, and Fig. 5 is an explanation of reflected light showing the basic principle of detection of the present invention. Figure, 4th
The figure shows another embodiment of the present invention. 1...Mask, 2...Ueno), 21
... Wafer target mark 1 3 ... Reduction lens, 4 ... Illumination light source 15.
...Pattern detector. 11 no'

Claims (1)

【特許請求の範囲】 1、照射する光をP偏光としてウェハ上の合わせマーク
にブリュースター角で入射し、この合わせマークからの
反射光を露光レンズにより合わせマーク像として結像し
、この合わせマーク像を撮像手段により撮像して映像信
号に変換し、この変換された映像信号に基いて合わせマ
ークの位置を検出してマスクとアライメントを行い、マ
スク上に形成された回路パターンをウェハ上に露光する
ことを特徴とする半導体露光方法。 2、上記ウェハ上の合わせマークは、周期的構造を有す
るマークであることを特徴とする特許請求の範囲第1項
記載の半導体露光方法。 3、上記ウェハ上の合わせマークに入射する光は、その
入射面に上記マークの周期的変化の方向が平行になるよ
うにすることを特徴とする特許請求の範囲第2項記載の
半導体露光方法。
[Claims] 1. P-polarized light is incident on the alignment mark on the wafer at Brewster's angle, and the reflected light from this alignment mark is imaged by an exposure lens as an image of the alignment mark. The image is captured by an imaging device and converted into a video signal. Based on the converted video signal, the position of the alignment mark is detected and aligned with the mask, and the circuit pattern formed on the mask is exposed onto the wafer. A semiconductor exposure method characterized by: 2. The semiconductor exposure method according to claim 1, wherein the alignment mark on the wafer is a mark having a periodic structure. 3. The semiconductor exposure method according to claim 2, wherein the light incident on the alignment mark on the wafer is made such that the direction of periodic change of the mark is parallel to the incident plane. .
JP62026280A 1987-02-09 1987-02-09 Method for exposing semiconductor Pending JPS63194330A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62026280A JPS63194330A (en) 1987-02-09 1987-02-09 Method for exposing semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62026280A JPS63194330A (en) 1987-02-09 1987-02-09 Method for exposing semiconductor

Publications (1)

Publication Number Publication Date
JPS63194330A true JPS63194330A (en) 1988-08-11

Family

ID=12188874

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62026280A Pending JPS63194330A (en) 1987-02-09 1987-02-09 Method for exposing semiconductor

Country Status (1)

Country Link
JP (1) JPS63194330A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62291919A (en) * 1986-06-12 1987-12-18 Canon Inc Observation apparatus

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62291919A (en) * 1986-06-12 1987-12-18 Canon Inc Observation apparatus

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