JPS63193782A - Video signal reproduction device - Google Patents

Abstract

PURPOSE:To obtain a noiseless reproduced picture even in slow reproduction by functioning a memory for 1/(n-1) field to function as the temporary storage element and the delay element of a reproduced signal. CONSTITUTION:In a first field of slow reproduction, the normal reproduced output of a video reproduction processing circuit 22 is supplied to an output terminal 58, and the signals for leading 1/3 field are stored in the memory 44. In the next field, the signals for one field are read from the memory 44 by a still action, and are supplied to the output terminal 58. In the next field, the normal reproduced output of the video reproduction processing circuit 22 is supplied to the output terminal 58. Hereafter, the action of three fields is set to one unit, and it is repeated. With providing the memory of a minimum capacity, noiseless slow reproduction is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal reproducing device, and more specifically to a reproducing device that realizes noiseless slow playback.

[Conventional technology]

2. Description of the Related Art Conventionally, as one method for slow reproduction of video signals recorded on a magnetic tape, a method has been proposed in which the magnetic tape is advanced intermittently and normal reproduction and still reproduction are alternately repeated. In addition, as a method of reducing noise on the playback screen when performing still playback using only the head used for normal playback, the playback signal is stored in the -H field memory, and from now on,
A method for repeatedly reading data stored in the field memory is presented. Therefore, in the conventional slow playback method that involves intermittent tape feeding and still playback using this field memory, field memory is required to reduce or eliminate noise in the reproduced video.
Since it requires memory with the capacity for the field,
This has the disadvantage of increasing costs and increasing the size of the circuit.

Another way to achieve noiseless slow playback without using field memory is to install a dedicated playback head, but the rotating drum does not have enough space for such a dedicated head. , and a circuit for a dedicated head is required, which has the disadvantage that the circuit size increases accordingly. In particular, modern playback devices have been made smaller and lighter by using small-diameter drums equipped with four heads spaced at 90° intervals and by winding the magnetic tape around the drum at 270°. If you try to install this dedicated head for slow playback on such a small diameter drum, there is not enough space, and the pitch between the channels of the low cryo transformer will be small, and the playback signal will be distorted due to the cross talk between the channels. This is not desirable because it deteriorates.

[Problem that the invention attempts to explain]

In this way, conventional slow playback leads to an increase in circuit size and/or manufacturing costs, and it is difficult to make products smaller and lighter.
This was an impediment to lower prices.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a video signal reproducing device that uses a small-diameter drum and a small-capacity memory to realize noiseless slow playback.

[Means for solving problems]

The video signal reproducing apparatus according to the present invention can mutually (360/n)
) A tape-shaped recording medium is wound over an angular range of (360X (n-1)/n) or more around a drum equipped with n heads (n is an integer of 3 or more) that rotate with a phase difference of An apparatus for reproducing a recorded video signal, comprising means for intermittently feeding a tape-shaped recording medium when performing slow reproduction by alternately repeating normal reproduction and still reproduction;
A memory capable of storing video signals for 1/(n-1) fields, and controlling writing and reading of the memory in order to cause the memory to continuously read and output one field's worth of reproduced video signals in the still playback state. It is characterized by comprising a memory control means.

[Effect]

In the present invention, the memory for 1/(n-1) fields is made to function as a temporary storage element for the reproduced signal and as a delay element, so that no noise is generated even in the still reproduction state. Of course, no noise occurs during normal playback when the magnetic tape is running, so even when viewed as slow playback, a reproduced image without noise can be obtained.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of an embodiment of a reproducing apparatus using a four-head drum with 270° winding. Second
The figure shows the four-head drum viewed from above. As can be seen from FIG. 2, four heads 10a, 10b,
12a and 12b are arranged perpendicularly to the circumference of the drum 14, and the magnetic tape 16 is wrapped around the circumference of the drum 14 over an angular range of 270° or more. Head 10a, head 10b1, head 12a, and throat 12b have the same azimuth, and when recording a video signal, bend 10as head 12 bz head 10b1 head 12
The video signal is recorded one field at a time with rotation a. Also, during normal playback, the four heads are selectively used in the same rotation as during recording to obtain a playback video signal. In the embodiment shown in FIG. 1, during still playback,
Head 10a and Head 10b2 Head 12a and Head 1
2b act in pairs.

In FIG. 1, the head changeover switch 18 is connected to the head 10.
a, 10b, 12a, 12b, and sends its output to the video playback processing circuit 22 via the head amplifier 20.
supply to. The video playback processing circuit 22 connects one selection contact 24a of the RF double signal changeover switch 24 to the A/D converter 2.
6.

The horizontal synchronization signal pass filter 28 extracts a horizontal synchronization signal based on a signal from an appropriate part of the video reproduction processing circuit 22 and applies it to a voltage controlled oscillator (VCO) 30 .

The terminals 32 include heads LOa, 10b, and 12a.

A signal indicating the rotational phase of the fixed drum 12b is supplied from a so-called pulse generator (PG), and the phase pulse is amplified by an amplifier 34 and then sent to a quadrupler 3.
6 makes the signal four times the frequency, and the six frequency divider 38 reduces the frequency of the output of the four frequency multiplier 36 to 1/6. The output of the quadrupler 36 is connected to the write (WR) address control circuit 40 and the read (R
D) Applied to the address control circuit 42, the output of the divider by 6 is applied to the write address control circuit 40 and the read address control circuit 42 via the normally open switch 39, which is closed during still playback and slow playback. be done.

The write address control circuit 42 instructs writing of reproduction signals for the first 173 fields in the field during still reproduction, and instructs writing of reproduction signals for the first 2/3 fields in the next field. Outputs a write control signal like this. The read address control signal outputs a read address control signal instructing to read data every l fields.

The part surrounded by the broken line is the circuit part that temporarily stores the reproduced video signal during still playback, and 44 is 1/3 of one field.
46 is a write address circuit that designates the write address, and 48 is a read address circuit that designates the read address. The write address circuit 46 instructs the write operation of the memo IJ 44 according to the write control signal 41 from the write address control circuit 40, and is clocked by the output of the VCO 30 to cyclically update the write address value. A/D converter 26, which supplies digital data to be written to memory 44, performs A/D conversion under timing by the output of vC030. On the other hand, the read address circuit 48 instructs the read operation of the memory 44 according to the read control signal 43 from the read address control circuit 42,
It is clocked by the output of the crystal oscillator 50 to cyclically update the read address. The output of the crystal oscillator 50 also defines the conversion timing of the D/A converter 52 that converts the digital signal read from the memory 44 into an analog signal.

The output of the D/A converter 52 is connected to the selection contact 24b of the output selector switch 24. The output switching pulse generation circuit 53 generates an output switching pulse that controls switching of the switch 24 in response to a pulse from the switch 39. The pseudo vertical synchronization (V) signal generating circuit 54 generates a pseudo ① signal at appropriate timing in response to the pulse signal from the switch 39.

Mixer 56 mixes the pseudo V signal from pseudo V signal generation circuit 54 with the video signal from common contact 24c of switch 24, and outputs a reproduced video signal to output terminal 58. A known television broadcasting device (not shown) is connected to the output terminal 58.

Reference numeral 60 denotes a mode selection switch for selecting and instructing various playback modes such as normal playback mode, still playback mode, and slow playback mode, and outputs a signal indicating the mode. The mode switching signal generation circuit 62 receives the mode designation signal from the mode selection switch 60 and the output of the 6-frequency divider 38, and the 11th and 2nd
generates a mode switching signal. However, in the circuit shown in Figure 1,
Since normal playback, still playback, and slow playback are targeted, when the still playback mode and slow playback mode are selected, the mode switching signal generation circuit 62 sets the first mode switching signal to old gh, and the still playback When in mode, the second
The mode switching signal is also the old gh. Head switching pulse generation circuit 64 receives the output of frequency divider 38 and the two outputs of mode switching signal generation circuit 62, and generates two pulses for controlling switching of head selection switch 18. Here, the switch 18 specifies one of the four heads based on the combination of the logic levels of the two pulses generated by the generating circuit 64. Here, the first switching control pulse and the second
The combination of logic levels of the switching control pulses is (Loe
v, Low), the head loa is mi (formerly gh, Low).
) when the head 10b is (Low, High) 7
When the lower 12a is (High, High), the lower 12b
It is assumed that each head is specified, and the playback output of the specified head is output from the switch 18.

Reference numeral 68 denotes a control signal reproducing head which reproduces a control signal (CTL) having a frequency related to the track pitch of the video track from a control signal track extending in the longitudinal direction of the magnetic tape. The signal is inputted via the open switch 72 to a delay circuit 74 with a delay time τ1. The switches 72 and 39 are closed by a mode switching signal from the mode switching signal generation circuit 62. 76 is
A capstan motor 78 rotates a capstan (not shown) that feeds the magnetic tape 16.
, and 80 is a drive circuit for the motor 76 . The drive circuit 80 rotates the motor 76 at a predetermined speed in response to a speed detection signal from the speed detection circuit 78. The drive circuit 80 also applies a braking pulse with a predetermined time width to the motor 76 in response to the braking input, and applies an acceleration pulse with a predetermined time width to the motor 76 in response to the acceleration input.

The reset pulse generation circuit 82 generates Ilig from the generation of the acceleration pulse of the drive circuit 80 to the end of the braking pulse.
A reset pulse equal to h is formed and applied to the reset input of counter 84. The output of the 6 frequency divider 38 is connected to the clock input of the counter 84 via a switch 39. The counter 84 outputs a pulse after counting the output pulses of the 6 frequency divider 38 up to a predetermined count value which can be changed freely.

The output of the counter 84 is connected to the acceleration input of the drive circuit 80 via a delay circuit 86 with a delay time τ1.

The output of delay circuit 74 is connected to the brake input of drive circuit 80.

Next, the operation of the circuit shown in FIG. 1 will be explained. In the case of normal playback, although there is no need to explain in detail, the switch 24 is connected to the contact 24a side, and the switch 18 sequentially selects one of the four heads in the rotation process described above, and the video playback processing circuit 22 RF outputs are output as they are from the output terminal 58. At this time, the head switching pulse generation circuit 64 uses a signal obtained by further dividing the output of the frequency divider 38 by 2 as the first switching control pulse, and uses the output of the frequency divider 38 as it is as the second switching control pulse. It is configured to be used. In this case, since the switch 39 is in the open state, the pseudo-■ signal generating circuit 54 does not generate a pseudo-V signal, and therefore, it is equivalent to the mixer 56 not existing.

Next, field still playback will be explained. FIG. 3 shows a timing chart during still playback. (al～(
pl corresponds to (al to (p)) in FIG. 3, respectively, and indicates signals of adjacent connection lines or signal lines.

Although (g) and (hl) in Figure 3 are originally digital signals, they are shown in the form of analog signal envelopes for ease of understanding. The symbols indicate the heads involved in the reproduction.The time increments in Fig. 3 are provided every 1/3 field.The write control signal (d) and the read control signal (el
Both enable memory writing and memory reading in the old GH.

When still playback is selected with the mode selection switch 60,
In response to the output data (1) of the switch 60, the mode switching signal generation circuit 62 generates a first mode switching signal in synchronization with the immediately subsequent change in the output of the divider by 6 (the falling edge of time 1 in the illustrated example). (If ml is the old gh, then switch 3
9.72 is closed. Along with this, a reproduction control signal (0) from the head 68 is applied to the braking input of the drive circuit 80 via the amplifier 70, the switch 72, and the delay circuit 74. Then, the drive circuit 80 generates a braking pulse (p) to stop the motor 76. In this stopped state, the delay circuit 7 is arranged so that the recording track of the magnetic tape 16 and the reproduction track of the reproduction head have a positional relationship as shown in FIG.
A delay time τ of 4 is set. In order to prohibit movement of the magnetic tape, no signal (from the delay circuit 86) is input to the acceleration input of the drive circuit 80 by the second mode switching signal.

The switch 18 receives first and second head switching pulses (k-1) and (k-2) from the head switching pulse generation circuit 64.
Depending on the head 10a, 1. One of Ob, 12a, and 12b is specified and a reproduction signal of this particular head is output, and the video reproduction processing circuit 22 outputs an RF multiplied signal f). The first head switching pulse (k-1) at this time may be exactly the same as during normal playback, and the second head switching pulse may be set at the first field (k-1) in which the mode switching signal corresponding to the still playback mode is generated. 1+ to t4) (Lotm in the case of FIG. 3) may be maintained. Time 1. Assume that the head 10a starts playing back the tape 16.

The playback video signal (f) output from the video playback processing circuit 22 is the write control signal (f) of the write address control circuit 40.
1/3 field from t under d) is memo IJ44
will be written to. At time t4 when the head 10a finishes reproducing the tape 16, the head 10b is already at a position where it has traced the tape 16 by 1/3 field.

At time t4, the head specified by the bed switching signal (FIG. 3(C)) changes from head 10a to head IQb.
The head 10b starts playing. At the same time as this head switching, 11-1. The playback signal is stored in the memory 44.
At time t, when the output of the video reproduction processing circuit 22 from time t4 onward is written to the same address as shown in FIG. ) is accommodated from time 0, t,
A read from memory 44 and a write to the same address are performed, so that at time t, memory 44 has data at time t,
~t, reproduction signals are accommodated. 1 after time t6
For the /3 field, writing to the memory 44 is prohibited and only reading is performed (FIGS. 3(d) and (e)). ,
As a result, the reproduced signal at time ts4t& is output from the memory 44 between time t and time t7 at the beginning of the next field.

In summary, the first 173 fields of the signal reproduced by the head 10a are delayed by l fields by the memory 44. The head 10b, which is located on the opposite side of the drum center from the head 10a, receives one field's worth of signals.
The last 2/3 field is reproduced, and the memory 44 acts as a delay element by writing and reading the reproduced signal. As a result, signals for one field appear continuously at the output of the memory 44 from t# to t7. Since the magnetic tape 16 is stopped, time 1. Since the RF ratio output f) from time t4 to time t4 is the same as the output of the memory 44 from time t4 to time t, if switch 24 is switched from contact 24a to contact 24b at time t4, , as shown in FIG. 3 (11), the image is the same for two fields. Thereafter, the switch 24 can be switched every other field.

Note that the still playback described here does not require that the head at the start of playback be the head 10a. This can be handled by the switching operation of the head switching switch 18 described above.

Next, slow playback will be explained. Slow playback is achieved by playing stills while moving the magnetic tape intermittently.

FIG. 5 shows an example of the relationship among the tape speed, tape travel amount, and cabs-down motor drive current during slow playback. Fig. 6 shows a timing chart during slow playback at 71/3 times speed.
They correspond to (0) to (Z) and (i) in FIG. 1, respectively. When slow playback is selected by the mode selection switch 60 and the corresponding data (1) is output,
As in the case of still playback, the mode switching signal generation circuit 62
is the first mode switching signal constant) as the old GH, and switch 3
9. Bring 72 into closed state. Opening switch 72 causes a reproduction control pulse (0) from reproduction head 68 to be applied to the braking input of drive circuit 80 via delay circuit 74 .

As a result, the drive circuit 80 generates a braking pulse (
Q) is generated and the motor 76 is stopped. At this stage, the above-mentioned still playback is executed, and the output terminal 56 has the memory 4.
A signal from 4 is output.

At the end of still playback for one field, the divider 38
The output pulse (C) falls, causing the counter 84 to count up. In the 173rd-fold entry-reproduction, the output generation count value of the counter 84 is 1;
Counter 84 therefore generates an output pulse (1). This pulse is delayed by τ2 in delay circuit 86 and then applied to the acceleration input of drive circuit 80. In response, the drive circuit 80 generates an acceleration pulse (r) with a predetermined width T2 to rotate the motor 76. The delay time τ of the delay circuit 86 and the time width T of the acceleration pulse (r) are set so that the head reaches a position where the next recording track on the magnetic tape can be reproduced. In FIG. 6, the deceleration pulse (Q) and the acceleration pulse (rl) are shown with the same polarity, but this is for explanatory purposes, and in the circuit shown in FIG. 24 is connected to the contact 24a side, and the output of the video playback processing circuit 22 is supplied to the output terminal 58.

To summarize, as shown in (X) in FIG. 6, in the first field of slow playback, the normal playback output of the video playback processing circuit 22 is supplied to the output terminal 58, and the first 1/3 field is It is stored in the memory 44. In the next field, one field's worth of signals are read out from the memory 44 by still operation and supplied to the output terminal 58. The next field is the video playback processing row 22.
The normal reproduction output of is supplied to the output terminal 58. This 3
The operation of the field is treated as one unit, and this process is repeated thereafter.

Note that the head switching pulse generation circuit 64 at this time is the first one shown in (v-1) and (v-2) in FIG. A second head switching pulse is output. Although this varies depending on the slow playback magnification, the head fog/epulse generation circuit 64 is configured to generate a pattern corresponding to a desired magnification.

FIG. 7 shows the trajectory of the magnetic head during 1/3 speed slow playback. In this slow playback, the magnetic tape is intermittently fed in two fields, so when the magnetic head finishes playing the first field (accelerating the magnetic tape) of those two fields, the magnetic head in a different azimuth moves on to the next field (accelerating the magnetic tape). It is necessary to be in the position to start playing the magnetic tape (braking). In order to satisfy this relationship, the counter 84
If the output generation count value is determined, the double speed value for slow playback can be changed using that count value. Specifically, if the count value is n (=2m-1; m is an integer), the slow speed is 1/(n+2) times the speed, that is, 1/(2m+1).
) becomes twice as fast.

In the above embodiment, the timing of intermittent feed is controlled by reproducing the control signal of the control track, but auto trunk winding (so-called ATF), which uses a four-frequency pilot signal like an 8mm VTR, can also be used. A playback device adopting this method can achieve the same effect, only the timing signal for intermittent playback is different.

〔Effect of the invention〕

As can be easily understood from the above explanation, according to the present invention, noiseless slow playback can be achieved by providing a memory with a minimum capacity, and the drum diameter and circuit scale can be small, so that the product can be improved. It can contribute to miniaturization and weight reduction.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the configuration of an embodiment of the present invention, Fig. 2 is a top view of a 4-head drum with 270''winding;
Figure 3 is a timing diagram of the circuit in Figure 1 during still playback.
Figure 4 is a diagram showing the positional relationship between recording tracks and reproduction trunks during still playback, Figure 5 is a diagram explaining intermittent feeding of the tape during slow playback, Figure 6 is a timing diagram during slow playback, FIG. 7 is a diagram showing the trajectory of the magnetic head during slow playback. ioa, 10b, 12a, 12b=--head 14.
- Drum 16- Magnetic tape 18 Head selection switch 20- Head amplifier 22-
Video playback processing circuit 24 - Output selector switch
26-A/D converter 28...-Horizontal synchronizing signal passing filter 30--Voltage controlled oscillator (VCO) 34-Amplifier 36-.4 frequency multiplier 38.-6 frequency divider 39.-
Switch 40-・Write address control circuit 42-・-
Read address control circuit 44...Memory 46-
Write address circuit 48--Read address circuit 50
---Crystal oscillator 52 ---D/A converter 53
---Output switching pulse generation circuit 54--Pseudo vertical synchronization signal generation circuit 56--Mixer 58--Output terminal 60-Mode selection switch 62--Mode switching signal generation circuit 64--Head switching pulse generation circuit 68
---Control signal reproducing head 70---Amplifier 72-
- Switch 74 - Delay circuit 76 - Capstan motor 78 - Speed detection circuit 80 - Drive circuit 82 - Reset pulse generation circuit 84 - Counter 86 - Delay circuit Figure 5 Figure 7 Time ( a). Figure 3

Claims (2)

[Claims] (1) A tape-shaped recording medium is placed on a drum equipped with n heads (n is an integer of 3 or more) that rotate with a phase difference of (360/n)° from each other (360×(n-1)/n). A device for reproducing a recorded video signal by winding it over the above angular range, comprising means for intermittently feeding the tape-shaped recording medium during slow playback by alternately repeating normal playback and still playback, and 1/( n-1) A memory capable of storing video signals for fields, and in the still playback state,
A video signal reproducing device comprising memory control means for controlling writing and reading of the memory so that the memory continuously outputs one field's worth of reproduced video signals. (2) The device according to claim (1), wherein the intermittent feeding means includes means for adjusting the intermittent feeding speed.