JPS63193267A - Output feedback type multiplier - Google Patents

Abstract

PURPOSE:To decrease the number of one-bit sum-of-products circuit elements and to reduce the size of a circuit scale by feeding back some of the arithmetic outputs of parallel type multipliers and dividing multiplication processing into plural. CONSTITUTION:A sum-of-products circuit group 1 multiplies inputs (x5, x4...x0), and y1 and y0 with 1st one clock and multiplication results are latched in D type FFs 4. The latch contents of the FFs 4 are fed back with a next clock to sum up the multiplication results of the (x) inputs and y2 and y2, and then while the addition result is latched in the FFs 4, a selector 6 switches FFs 4 where the low-order bits are latched. Then the latch contents of the FFs 4 with a next clock to sum up the multiplication results of the (x) inputs, and y5 and y4, and the result is latched in the FFs 4. The output obtained by passing said latch output through all adder 3 and the output of the FF 4 becomes final multiplication results, and the multiplication processing is performed in three separated parts, so the number of one-bit sum-of-products circuit element is reduced greatly as compared with a processing circuit which requires sum-of- products circuit proportionally as many as input bits and the size of a circuit scale when the number of bits is large is reducible.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This book J Nishimei relates to multipliers in digital signal processing circuits.

BACKGROUND OF THE INVENTION FIG. 3 shows an example of a parallel multiplier circuit. Figure 3 shows a 6-bit X input (15m
X2 m”11”O) and 6-bit Y input (75, 74
, 73, 72, yl.

yo), and the 12-bit multiplication result M(ml
1.11110 +m9. '...”” + 11n
2 T n11 * In□ )' This is a parallel multiplier that obtains jf.

First, 1 is a 1-bit product-sum circuit, and the carry power is 14
．． Addition power 111 Multiplication inputs 12, 13, Carry output 1
5, has an addition output of 16. The 1-bit product-sum circuit 1 multiplies the multiplication inputs 12.13 and then outputs the addition inputs 11. Performs addition with carry human power 14 and outputs the result as carry output 1
6. Output from addition output 16. Next, 2 is a 1-bit multiplier having multiplication inputs 21, 22 and multiplication outputs 23. 3 is a full adder, and the addition input is 31°, 32°, and 34°. Carry output 33 and addition output 35
has.

The entire operation of the parallel multiplier configured as described above will be explained below with reference to FIG.

First, in the 1-bit multiplier 2 at the right end of the top stage, "o s
Multiply by yo and use the result as m. Bind and output. Next, the 1-bit multiplier 2 and the 1-bit product-sum circuit 1 in the second column from the right produce xl·y o +x. The corresponding calculation is performed to obtain a carry output 16 and an addition output m1. Further, the 1-bit multiplier 2 and the 1-bit product-sum circuit group 1 in the third column from the right generate X. - "O"1・yl"O'72 is added with the above carry output to obtain the carry output group 15 and addition output m2 of each 1-bit product-sum circuit 1. Similarly, the i-th column from the right is The 1-bit multiplier 2 and the 1-bit product-sum circuit group 1 also obtain a carry output group 15 and an addition output in each column.

Addition and multiplication are performed in each column as described above, and finally the multiplication output 36, addition output 32, and carry output 31 obtained by the 1-bit multiplier 2 and the 1-bit summation circuit group 1 at the bottom stage are Addition is performed by the full adder 3 to obtain addition outputs m1° to m6 and a carry output "11".

In this way, the X input and the Y input are multiplied to obtain the multiplication result M (m11 to mo).

Problems to be Solved by the Invention However, the above configuration requires a product-sum circuit proportional to the product of the number of input bits, so when the number of input bits is large, the circuit scale becomes extremely large. This has the problem that it becomes

In view of the above problems, the present invention provides an output feedback multiplier that can realize miniaturization of the circuit scale.

Means for Solving the Problems In order to solve the above problems, the present invention feeds back a part of the calculation output of the parallel multiplier, so that the multiplication that was performed in one clock in the conventional parallel multiplier can be performed multiple times. Divide it into two parts. This makes it possible to reduce the number of elements in a 1-bit product-sum circuit to less than half that of the conventional circuit, making it possible to significantly reduce the circuit scale for a single sound.

Function: In accordance with the above-mentioned advantages, the present invention makes it possible to significantly reduce the total number of multipliers. Further, by freely setting the above-mentioned division number according to the calculation speed of the element, it is possible to completely optimize the circuit reduction.

Example Figure ytS1 is a circuit diagram showing an embodiment of the present invention.

In FIG. 1, numerals 1 and 3 are a product-sum circuit and a full adder similar to the conventional example. And 4 is D input 42. Clock human power 43. D-flip 70 tube with output 44,
6 is a selector and has a control input signal 61. Furthermore, 5 is an AND gate.

The operation of the parallel feedback multiplier configured as described above will be explained. First, input at the first clock (“5”
41"31"21"1#"O) and 71*700 multiplication is performed by the product-sum circuit group 1, and the result is latched in the iD flip-flop 4. Then, at the next clock, the output of the D flip-flop 4 is fed back, added to the X input and the multiplication result of 73-72, and the result is latched into the D flip-flop 70 knob 4 again.

At this time, D7 latches the lower bit by selector 6.
Switch the printer flop 4. Then, at the next clock, the output of D flip-flop 4 is fed back again, and
The result of multiplying the input by y5.74 is added and latched into the D clip-flop 4. Finally, the output of the D flip-flop 4 is added by the full adder 3, and the output is 33.35.
The lower bit output PA and the output PB of the D flip-flop 4 for lower bits are X input (X s + X 4.
This is the multiplication result of X s , X 2 * X 1°x o ) and Y input (75+74*5'372*71, y□). Then, before performing the next multiplication, all feedback signals are reset to rLJ by a clear signal.

By performing the above operations continuously, the same multiplication as the parallel multiplier shown in FIG. 3 is performed in three clocks.

Another embodiment of the invention is shown in FIG. Compared with FIG. 1, FIG. 2 differs only in the position of the feedback register, and the operation is exactly the same as FIG. 1. By adopting such a circuit configuration, it is possible to further reduce the number of circuit elements as shown in FIG. . However, since the calculation time within one clock is longer than that in FIG. 1, this is disadvantageous in terms of calculation speed.

As described above, by providing a feedback register and performing multiplication by dividing it into multiple times, it is possible to perform multiplication with a significantly smaller number of elements compared to conventional parallel multipliers.

As described above, the present invention provides a feedback register 'ff: 1.
By dividing the multiplication process into a plurality of times, the number of circuit elements can be significantly reduced, and an optimal design of hardware can be achieved depending on the calculation speed.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an output feedback multiplier according to a first embodiment of the present invention;
・1-bit product-sum circuit, 2...1 bit 14 circuit,
3...Full adder, 4...D flip flow rough-5...AND gate, 6...
Selector.

Claims (1)

[Claims] A 1-bit multiplier that multiplies two 1-bit data, a 1-bit product-sum circuit that multiplies two 1-bit data and then multiplies it with other inputs, and the output of the 1-bit product-sum circuits. An output feedback multiplier characterized by comprising a full adder that adds up and a register that latches and feeds back the output of the full adder.