JPS6319072B2 - - Google Patents

Info

Publication number
JPS6319072B2
JPS6319072B2 JP60003898A JP389885A JPS6319072B2 JP S6319072 B2 JPS6319072 B2 JP S6319072B2 JP 60003898 A JP60003898 A JP 60003898A JP 389885 A JP389885 A JP 389885A JP S6319072 B2 JPS6319072 B2 JP S6319072B2
Authority
JP
Japan
Prior art keywords
electrode
aging
film
electrodes
thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP60003898A
Other languages
Japanese (ja)
Other versions
JPS61161693A (en
Inventor
Kinichi Isaka
Kyoichi Yamamoto
Jun Kawaguchi
Hiroshi Kishishita
Hisashi Kamiide
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP60003898A priority Critical patent/JPS61161693A/en
Publication of JPS61161693A publication Critical patent/JPS61161693A/en
Publication of JPS6319072B2 publication Critical patent/JPS6319072B2/ja
Granted legal-status Critical Current

Links

Description

【発明の詳細な説明】 <技術分野> 本発明は、電極がマトリツクス構造を有する薄
膜ELパネルを交流電圧の印加によつてエージン
グする上で、電極抵抗の影響を少なくし、大表示
容量パネルのエージングを容易にしたエージング
方法に関するものである。
Detailed Description of the Invention <Technical Field> The present invention reduces the influence of electrode resistance when aging thin-film EL panels in which the electrodes have a matrix structure by applying an AC voltage, and improves the aging of thin-film EL panels in which the electrodes have a matrix structure. This invention relates to an aging method that facilitates aging.

<従来技術> 二重絶縁膜構造の薄膜ELパネルは、第5図に
示すように、ガラス基板1上にITO等の帯状透明
電極群2を並列に設け、この上に、Si3N4等の誘
電物質層3、Mn等の活性剤をドープしたZnSの
EL発光層4、Si3N4等の誘電物質層5を、この順
に真空蒸着法、スパツタリング法等により形成し
て、三層構造とし、更に誘電物質層5上に、前記
透明電極2と直交する方向に延びる帯状背面電極
群6を設けてなる構造である。
<Prior art> As shown in FIG. 5, a thin film EL panel with a double insulating film structure includes a group of band-shaped transparent electrodes 2 made of ITO or the like arranged in parallel on a glass substrate 1, and a layer of Si 3 N 4 etc. The dielectric material layer 3 is made of ZnS doped with an activator such as Mn.
An EL light-emitting layer 4 and a dielectric material layer 5 such as Si 3 N 4 are formed in this order by vacuum evaporation, sputtering, etc. to form a three-layer structure, and further on the dielectric material layer 5 are layers perpendicular to the transparent electrode 2. This structure is provided with a band-shaped back electrode group 6 extending in the direction shown in FIG.

等価回路的には容量性素子であり、所望の透明
電極と背面電極とに所定の交番電圧を印加するこ
とにより、両電極の交差部に挾持された微小面積
部分が発光し、文字、記号、模様等を表示するた
めの一絵素を構成する。
In terms of an equivalent circuit, it is a capacitive element, and by applying a predetermined alternating voltage to a desired transparent electrode and a back electrode, a minute area sandwiched at the intersection of both electrodes emits light, producing characters, symbols, etc. It constitutes one picture element for displaying a pattern, etc.

上記構造を基本とする薄膜ELパネルは、発光
輝度等の経時変化の安定化と初期故障による不良
素子を除去する等の目的で、薄膜作製後、一定期
間、交流電圧を透明電極群と背面電極群間に印加
しながらエージングを行なうことが必要となる。
エージング時には、表示絵素を同時に処理する必
要性と、駆動回路を簡略するために、第6図の様
に、一方向に引き出されている電極は1つの共通
電極にまとめられ、さらに相対する側の共通電極
を1つにして、1組の共通電極としている。この
一組の共通電極に第6図の様に交流電圧パネルを
印加し、すべての交点を同時に発光させ、エージ
ング処理を行なつている。この場合のELパネル
の等価回路は第7図の様になる。Cは発光絵素の
容量、Rは透明電極の抵抗である。
Thin-film EL panels based on the above structure are manufactured by applying alternating current voltage to the transparent electrode group and the back electrode for a certain period of time after the thin film is fabricated, in order to stabilize changes in luminance over time and to remove defective elements due to initial failure. It is necessary to perform aging while applying power between groups.
At the time of aging, in order to simultaneously process the display pixels and to simplify the drive circuit, the electrodes drawn out in one direction are combined into one common electrode, as shown in Figure 6, and the electrodes drawn out in one direction are combined into one common electrode, and the electrodes drawn out in one direction are combined into one common electrode. The common electrodes are combined into one set of common electrodes. An alternating current voltage panel is applied to this set of common electrodes as shown in FIG. 6, and all intersection points are caused to emit light simultaneously to perform aging processing. The equivalent circuit of the EL panel in this case is shown in Figure 7. C is the capacitance of the light-emitting picture element, and R is the resistance of the transparent electrode.

表示容量が小さい場合、印加パルス幅に対して
時定数C・Rが小さいので、どの絵素に対しても
所定の波形が印加されるが、表示容量が大きくな
り、時定数C・Rがパルス幅より大きくなると、
透明電極の端子部から離れた部分では波形がかか
らなくなる(第8図。)。パルス幅は、他の特性と
の関係で、必要以上に大きく出来ないので、大表
示容量パネルは、全絵素が均一にエージング出来
ない問題がある。
When the display capacitance is small, the time constant C・R is small with respect to the applied pulse width, so a predetermined waveform is applied to every pixel. However, as the display capacitance becomes large, the time constant C・R is If it becomes larger than the width,
The waveform is no longer applied in the portion of the transparent electrode away from the terminal portion (FIG. 8). Since the pulse width cannot be made larger than necessary due to the relationship with other characteristics, a large display capacity panel has the problem that all picture elements cannot be aged uniformly.

<発明の目的> 本発明は上記問題点に鑑みて成されたものであ
り、大表示容量あるいは一方が10Ω/□以上の抵
抗電極を持つ薄膜ELパネルをエージング処理す
る際に、電極抵抗の影響を小さくし、全面を均一
にエージングする方法を提供するものである。
<Purpose of the Invention> The present invention has been made in view of the above-mentioned problems, and is intended to reduce the influence of electrode resistance when aging a thin film EL panel having a large display capacity or one having a resistance electrode of 10Ω/□ or more. The present invention provides a method for uniformly aging the entire surface.

<発明の構成> 本発明による薄膜ELパネルのエージング方法
は、互いに直交する方向に複数本配列された、
ITO等透明導電膜及びAl金属膜より成る2組の
帯状電極部で構成されるマトリツクス電極間に誘
電体層を介して層設されたEL発光層を基板上に
搭載して成る薄膜ELパネルのエージング処理方
法に於いて、上記ITO等透明導電膜より成る電極
部はすべて短絡し、同一信号を印加すると共に、
上記Al等金属膜より成る電極部は複数部分に分
割短絡し、それぞれ異なつた信号を印加すること
を特徴とするものである。
<Structure of the Invention> A method for aging a thin film EL panel according to the present invention comprises:
A thin-film EL panel consists of a matrix electrode consisting of two sets of strip-shaped electrodes made of a transparent conductive film such as ITO and an Al metal film, and an EL light-emitting layer placed on a substrate with a dielectric layer interposed between them. In the aging treatment method, all the electrode parts made of transparent conductive films such as ITO are short-circuited, and the same signal is applied.
The electrode portion made of the metal film such as Al is divided into a plurality of parts and short-circuited, and different signals are applied to each part.

<実施例> 以下、実施例に基づいて本発明を説明する。<Example> Hereinafter, the present invention will be explained based on Examples.

第1実施例 第1の実施例は、背面電極側(低抵抗電極側)
の一方に引き出された電極群(XA群とする)と、
他方に引き出された電極群(XB群とする)に、
位相をずらした波形を印加する。これにより、同
時に発光する絵素を1/2に減らして透明電極に流
れる電流を半減させ、電極抵抗の影響を小さくす
るものである。
First Example The first example is the back electrode side (low resistance electrode side).
A group of electrodes drawn out to one side (referred to as group X A ),
To the electrode group (referred to as group X B ) drawn out to the other side,
Apply phase-shifted waveforms. This reduces the number of picture elements that emit light at the same time by half, halving the current flowing through the transparent electrode, and reducing the influence of electrode resistance.

本実施例に於ける駆動結線図を第1図1に示す 透明電極yiは、すべて共通電極Yに接続されて
いる。Alは電極xiは、奇数ラインが共通電極XA
に、偶数ラインがXBに接続されている。
A drive connection diagram in this embodiment is shown in FIG. 1. All transparent electrodes yi are connected to a common electrode Y. Al is the electrode xi, the odd line is the common electrode x A
, the even lines are connected to X B.

この共通電極のそれぞれに第1図2に示すパル
スを印加すると、Al電極奇数ライン上の絵素と
偶数ライン上の絵素の発光時期がずれるので、各
透明電極yiに流れる瞬時電流はほぼ半減する。
When the pulses shown in Fig. 1 and 2 are applied to each of these common electrodes, the light emission timing of the picture elements on the odd-numbered lines of the Al electrode and the picture elements on the even-numbered lines are shifted, so the instantaneous current flowing through each transparent electrode yi is approximately halved. do.

この駆動による等価回路を第2図に示す。 An equivalent circuit resulting from this drive is shown in FIG.

従つて、この駆動方法により、Al電極側のラ
イン数が従来の2倍の表示容量のパネルまで、電
極抵抗の影響を少ないエージング処理が可能とな
る。
Therefore, with this driving method, it is possible to perform aging processing with less influence of electrode resistance, even for panels with a display capacity that is double the number of lines on the Al electrode side than conventional panels.

第2実施例 第2の実施例は、背面電極側(低抵抗電極側)
の一方に引き出された電極群(XA群)と、他方
に引き出された電極群(XB群)に、逆極性の波
形を印加する。これにより、隣り合う金属電極間
の絵素が逆方向の極性に同時に引つ張られるの
で、透明電極には殆ど電流が流れず、したがつ
て、抵抗の影響は殆ど無い。
Second Example The second example is the back electrode side (low resistance electrode side).
Waveforms of opposite polarity are applied to the electrode group drawn out to one side (X A group) and the electrode group drawn out to the other side (X B group). As a result, the picture elements between adjacent metal electrodes are simultaneously pulled to opposite polarities, so that almost no current flows through the transparent electrodes, and therefore there is almost no influence of resistance.

第1実施例と同じ結線図で、共通電極には第3
図に示すパルスを印加する。
It is the same wiring diagram as the first embodiment, but the common electrode has a third
Apply the pulse shown in the figure.

この駆動方法によれば、発光時期は全面同時で
あるが、Al電極奇数ライン上の絵素と偶数ライ
ン上の絵素では印加電圧の極性が逆になるので、
発光電流はAl電極上を流れるが、透明電極上は
一部しか流れず、透明電極端子部の電流はほとん
ど0になる。
According to this driving method, the light emission timing is simultaneous across the entire surface, but the polarity of the applied voltage is reversed between the picture elements on the odd-numbered lines and the picture elements on the even-numbered lines of the Al electrode.
The light emitting current flows on the Al electrode, but only partially flows on the transparent electrode, and the current at the terminal of the transparent electrode becomes almost zero.

この駆動による等価回路を第4図に示す。図に
於いて、r≒R/n(n:絵素数)である。
An equivalent circuit resulting from this drive is shown in FIG. In the figure, r≈R/n (n: number of picture elements).

従つて、この駆動方法により、透明電極の電極
抵抗の影響はほとんどなくなるので、エージング
時の表示容量の制限がなくなる。
Therefore, with this driving method, the influence of the electrode resistance of the transparent electrode is almost eliminated, so there is no restriction on the display capacity during aging.

<発明の効果> 以上の説明で明らかなように、本発明のエージ
ング方法によれば、大表示容量のパネルのエージ
ングにおいて、電極抵抗の影響による駆動分布や
波形なまりの少ない、あるいはほとんどない処理
が可能になり、エージング効率が改善される。今
後、薄膜ELパネルは大表示容量を目指す方向に
あり、その場合のエージング方法として有効な手
段となる。
<Effects of the Invention> As is clear from the above explanation, according to the aging method of the present invention, processing with little or almost no drive distribution or waveform distortion due to the influence of electrode resistance can be achieved in aging of large display capacity panels. This improves aging efficiency. In the future, thin-film EL panels will aim for larger display capacities, and in that case they will be an effective aging method.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図1は本発明に係るエージング方法の電極
結線図、第1図2は本発明の第1の実施例の駆動
波形図、第2図は同第1の実施例の等価回路図、
第3図は本発明の第2の実施例の駆動波形図、第
4図は同第2の実施例の等価回路図、第5図はド
ツトマトリツクス電極構造を有する薄膜ELパネ
ルの構造を示す斜視図、第6図は従来のエージン
グ駆動時の電極結線図、第7図は従来のエージン
グ駆動時の等価回路図、第8図は透明電極上の駆
動波形のなまりを示す図である。 符号の説明、1:ガラス基板、2:前面透明電
極、3:誘電物質層、4:EL発光層、5:誘電
物質層、6:背面金属電極。
FIG. 1 is an electrode connection diagram of the aging method according to the present invention, FIG. 1 is a drive waveform diagram of the first embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of the first embodiment.
FIG. 3 is a drive waveform diagram of a second embodiment of the present invention, FIG. 4 is an equivalent circuit diagram of the second embodiment, and FIG. 5 is a structure of a thin film EL panel having a dot matrix electrode structure. FIG. 6 is a perspective view, FIG. 6 is an electrode connection diagram during conventional aging drive, FIG. 7 is an equivalent circuit diagram during conventional aging drive, and FIG. 8 is a diagram showing the rounding of the drive waveform on the transparent electrode. Explanation of symbols: 1: glass substrate, 2: front transparent electrode, 3: dielectric material layer, 4: EL light emitting layer, 5: dielectric material layer, 6: back metal electrode.

Claims (1)

【特許請求の範囲】 1 互いに直交する方向に複数本配列された、
ITO等透明導電膜及びAl等金属膜より成る2組
の帯状電極部で構成されるマトリツクス電極間に
誘電体層を介して層設されたEL発光層を基板上
に搭載して成る薄膜ELパネルのエージング処理
方法に於いて、 上記ITO等透明導電膜より成る電極部はすべて
短絡し、同一信号を印加すると共に、上記Al等
金属膜より成る電極部は複数部分に分割短絡し、
それぞれ異なつた信号を印加することを特徴とす
る、薄膜ELパネルのエージング方法。
[Claims] 1. A plurality of wires arranged in mutually orthogonal directions,
A thin film EL panel consisting of a matrix electrode consisting of two sets of strip-shaped electrodes made of a transparent conductive film such as ITO and a metal film such as Al, and an EL light emitting layer placed on a substrate with a dielectric layer interposed between them. In the aging treatment method, all the electrode parts made of the transparent conductive film such as ITO are short-circuited and the same signal is applied, and the electrode part made of the metal film such as Al is divided into multiple parts and short-circuited,
A method for aging thin-film EL panels characterized by applying different signals to each.
JP60003898A 1985-01-10 1985-01-10 Aging of thin film el panel Granted JPS61161693A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60003898A JPS61161693A (en) 1985-01-10 1985-01-10 Aging of thin film el panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60003898A JPS61161693A (en) 1985-01-10 1985-01-10 Aging of thin film el panel

Publications (2)

Publication Number Publication Date
JPS61161693A JPS61161693A (en) 1986-07-22
JPS6319072B2 true JPS6319072B2 (en) 1988-04-21

Family

ID=11570002

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60003898A Granted JPS61161693A (en) 1985-01-10 1985-01-10 Aging of thin film el panel

Country Status (1)

Country Link
JP (1) JPS61161693A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6388786A (en) * 1986-10-01 1988-04-19 シャープ株式会社 Aging of thin film el panel

Also Published As

Publication number Publication date
JPS61161693A (en) 1986-07-22

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